JP2006217502A - Image transmission system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein an image transmission system becomes large for the system as a whole because the number of distribution cables for transmitting a data signal, such as an image signal and a control signal, becomes larger as turning to high resolution and to acceleration makes advance. <P>SOLUTION: In the image transmission system 10 having a transmitter 11 for converting a parallel image signal from the outside into a serial image signal and outputting the serial image signal and a receiver 12 for receiving the serial image signal from the transmitter 11, converting the serial image signal into a parallel image signal and outputting the parallel image signal to the outside, the receiver 12 is provided with a means for generating a clock signal. Consequently, the number of transmission cables for connecting the transmitter 11 and the receiver 12 is reduced, and the image transmission system can be made small. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image transmission system.

  In recent years, image transmission systems used as a part of video equipment are rapidly becoming higher in resolution and speed, and downsizing has become an issue.

  The image transmission system includes a transmitter that serializes and outputs external parallel image signals and control signals, a receiver that receives image signals and control signals from the transmitter, parallelizes the signals, and outputs them to the outside, and a transmitter and receiver And a transmission cable portion having a channel for transmitting an image signal and a control signal from the transmitter to the receiver.

  In addition, when transmitting these signals, a clock signal that matches the phase is required. The clock signal is generated in the transmitter, and the clock signal is used not only in the transmitter but also in the receiver. Therefore, it is necessary to transmit the clock signal from the transmitter to the receiver, and the channel of the transmission cable section requires several channels of cables for transmitting data signals such as image signals and control signals and one channel of cable for transmitting clock signals. (For example, refer to Patent Document 1).

However, as the resolution and speed of the image transmission system have increased, the number of cables for transmitting data signals such as image signals and control signals has increased, and there has been a problem in increasing the size of the entire system.
JP 2002-204377 A (page 6, FIG. 1)

  It is an object of the present invention to reduce the size of a transmission cable between a transmitter and a receiver in an image transmission system and reduce the size.

  According to a first aspect of the present invention, as an image transmission system, a parallel image signal input from the outside is converted into a serial image signal and transmitted to a receiver; the serial image signal is received from the transmitter; A receiver that converts an image signal into a parallel image signal and outputs the signal to the outside; a transmission cable unit that connects the transmitter and the receiver and transmits the serial image signal from the transmitter to the receiver; Has means for generating a clock signal.

  According to the present invention, it is possible to delete the transmission cable for the clock signal between the transmitter and the receiver by independently generating the clock signal not only at the transmitter but also at the receiver, thereby reducing the size of the image transmission system. can do.

  Embodiments of the present invention will be described below with reference to the drawings.

  A first embodiment of an image transmission system according to the present invention will be described with reference to FIGS. FIG. 1 is a block circuit diagram showing an outline of an image transmission system in this embodiment. FIG. 2 is a block circuit diagram showing a transmission unit in the image transmission system in the present embodiment. FIG. 3 is a timing chart showing data conversion of the transmission unit in the present embodiment. Further, FIG. 4 is a flowchart showing a procedure for adjusting the timing of data conversion at the receiver in this embodiment. FIG. 5 is a timing chart showing data conversion of the transmission unit in association with FIG.

  In FIG. 1, an image transmission system 10 includes a transmitter 11 and a receiver 12, which are connected by a transmission cable 13a. The transmitter 11 receives an image signal and a control signal sent from the outside, reproduces each signal, and outputs it to the receiver 12. The receiver 12 is further connected to a device (not shown) having an image display device such as an LCD, such as a personal computer, a monitor, and a television. Alternatively, it may be incorporated in a peripheral device of a computer or a television such as a monitor device or a television device of a personal computer. That is, an image signal sent from the outside is displayed as an image by a device such as a personal computer.

  The transmitter 11 includes an image control circuit 14 and a transmission circuit 15. The receiver 12 includes a receiving circuit 16 and an image processing circuit 17. The transmission circuit 15 and the reception circuit 16 connected by the wiring 13 a are the image signal transmission unit 13 from the transmitter 11 to the receiver 12.

  The image signal and control signal sent from the outside are processed as parallel signals in the image control circuit 14 and sent to the transmission circuit 15. In the transmission circuit 15, the parallel signal is converted into a serial signal and transmitted to the reception circuit 16 through the wiring 13a. The receiving circuit 16 receives the image signal and the control signal and reproduces each signal. Further, the reproduced signal is converted into a parallel signal and transmitted to the image processing circuit 17. In the image processing circuit 17, RGB gradation data in a format corresponding to an image display device (not shown), a control signal for driving the image display device, and the like are generated and output to the outside.

  The receiving circuit 16 may be any circuit that can decode and output data based on a serial signal. For example, an LVDS (Low Voltage Differential Signaling) standard receiving circuit or the like can be used.

  FIG. 2 is a block circuit diagram showing a transmission unit 13 including a transmission circuit 15, channels A to D as transmission cables, and a reception circuit 16. In the transmission circuit 15, an external signal is received by the PLL circuit 21, and a signal having a constant frequency is sent to the parallel / serial conversion circuit 22 as a clock signal for synchronization.

  This clock signal is used only by the transmission circuit 15 and is not transmitted through a cable as used in the reception circuit as in the conventional image transmission system. With such a system, the number of cables for transmission from the transmission circuit 15 to the reception circuit 16 can be reduced as compared with the prior art, and the cable connection can be simplified.

  On the other hand, an RGB parallel signal and a control signal, which are external data signals, are converted into serial signals by the parallel / serial conversion circuit 22. The converted serial signal is converted in voltage by the differential buffer circuit 23 and transmitted from the channels A to D, which are transmission cables, to the differential buffer circuit 24 of the receiving circuit 16.

  These data signals are converted into parallel signals by the serial / parallel conversion circuit 25 and output to the image processing circuit as RGB parallel signals and control signals.

  Next, clock synchronization in the receiving circuit 16 will be described. As described above, the clock differential signal transmission cable from the transmission circuit to the reception circuit 16 is deleted as compared with the conventional transmission unit. Therefore, in the receiving circuit 16, a circuit for correcting the clock timing for serial / parallel conversion of the data signal is added to periodically correct the timing of the clock signal and the data signal.

  In the receiving circuit 16, a signal from the built-in oscillator 26 or external external oscillator 27 is selected by the selector 28 and input to the PLL circuit 30. Along with the output of the clock signal from the PLL circuit 30, the data signal transmitted from the differential buffer circuit 24 is converted by the serial / parallel conversion circuit 25. However, in this state, the data signal and the clock signal are asynchronous.

  Therefore, first, a 1/7 skew adjustment circuit 31 that changes the phase of the clock signal every 1/7 of the clock cycle is provided so that the phase relationship between the clock signal and the data signal can be set, and the signal is sent to the clock generation circuit 32. . Thereby, a relatively coarse phase adjustment is performed. Further, a skew adjustment circuit 29 that finely changes the phase of the clock is arranged at the subsequent stage (or the previous stage) of the PLL circuit 30 so that the expected value data can be picked up. The clock signal pattern and the phase pattern of the control signal bit data transmitted from the differential buffer circuit 24 are adjusted, and a clock signal synchronized with the clock generation circuit 32 is transmitted to the serial / parallel conversion circuit 25.

  For example, FIG. 3A shows a serial-to-parallel data conversion map of 8-bit RGB signals in an LVDS standard transmission system. Among the data contents in each channel, control signal bits DE, HS (H sync), and VS (V sync) are included in channel C together with RGB signal bits such as R1, G1, and B1.

  FIG. 3B is a signal timing chart in each channel. The positions of the control signal bits DE, HS, and VS of the channel C are detected, and for example, the phase of the clock signal is adjusted in the 1/7 skew adjustment circuit 31 and the skew adjustment circuit 29 so as to match the signal bit DE.

  The phase adjustment in the 1/7 skew adjustment circuit 31 and the skew adjustment circuit 29 is automatically executed as described below. In other words, the control signal bits DE, HS, and VS have a predetermined change timing between the high level and the low level in the data for one screen. Therefore, a search is made for a condition in which any three consecutive data values in channel C in FIG. 3B match the expected values of the control signal bits DE, HS, and VS. From the matching conditions, clock skew data is set for the data. Note that the phase shift between the data signal and the clock signal can be corrected by executing this setting periodically, for example, every few minutes.

  FIG. 4 is a flowchart showing an automatic adjustment procedure of data conversion timing setting in the first embodiment, and FIG. 5 is a timing chart of clock timing adjustment. As described below, the X value is automatically set so that the data can be compared with the expected value, while the Y value is automatically read so that the data can be read accurately.

  In FIG. 4, after the start (S10), the clock X = 1 shown in FIG. 5 is set (S12), and the data of time Y = 1 is further set (S11). This cycle time is compared with the horizontal synchronization cycle time (H Sync) (S13). If it is greater than H Sync, the time Y is set to Y = Y + 1 and the loop is turned again (S23).

  On the other hand, if it is smaller than H Sync, this cycle time is compared with the vertical synchronization cycle time (V Sync) (S14). If it is greater than V Sync, the time Y is set to Y = Y + 1, and the loop is rotated again (S23).

  On the other hand, when X is smaller than H Sync, the timing T in FIG. 5 is set to T = 1, that is, (1) of serial data divided into seven periods (S15). In the above process, if the data reading timing is asynchronous with the data timing, the data cannot be read. Therefore, Y is shifted one by one so as to match the expected value.

  Subsequently, the data (2) and (3) are read starting from (1) of the serial data (S16). Further, it is checked whether each data is at high level or low level. When (1) = (2) = “L” (S17), that is, when the data of (1) and (2) are both at the high level, the data bit “DE” and the data bit “VS (V Sync)” "Is likely to be. Therefore, next, the timing T is shifted to T = T + 1 (S18). On the other hand, if (1) = (2) = “L” is not satisfied, the bit positions of (1), (2), and (3) are shifted to adjacent positions (S24).

  After the timing T is shifted to T = T + 1 (S18), the data level of (3) is further examined. When the data of (3) is at the high level (S19), the possibility that the data bit “DE”, the data bit “VS”, and the data bit “HS (H Sync)” are arranged is further increased.

  On the other hand, when the data (3) is at the low level, the bit positions (1), (2), and (3) are shifted to adjacent positions (S24). After shifting the bit positions of (1), (2), and (3) to adjacent positions, including the case where the previous (1) = (2) = “L” is not satisfied, the clock X is set to X = X + 1 And turn the loop again.

  However, if the data of (3) is at a high level (S19), if there is a single comparison, there may be an accidental coincidence due to data variations, so monitor over three cycles (T> 3) (S20). If confirmed, an appropriate output clock is set from the skew data based on the phase relationship between the data signal and the clock signal (S21). On the other hand, if it cannot be confirmed, the process returns to the data reading loop again.

  In the above-described flow, the timing Y is a data reading position. If the bit is set to be divided into, for example, four, it can match an appropriate expected value.

  As described above, in the image transmission system, not only has the clock generation only on the transmitter side, but also sets the clock generation function on the receiver side, so that a cable for transmission from the transmission circuit to the reception circuit can be provided. It can be reduced, and the cable connection can be simplified and downsized.

  A second embodiment of the image transmission system according to the present invention will be described with reference to FIGS. FIG. 6 is a block circuit diagram showing a transmission unit in the image transmission system in the present embodiment. FIG. 7 is a flowchart showing the procedure for adjusting the timing of data conversion at the receiver in this embodiment.

  The outline of the image transmission system in the present embodiment is basically the same as that in the first embodiment, and a description thereof will be omitted.

  FIG. 6 is a block circuit diagram showing a transmission unit 13b including a transmission circuit 15b, channels A to D as transmission cables, and a reception circuit 16b. In the transmission circuit 15b, a signal from the outside is received by the PLL circuit 21, and a signal of a constant frequency is sent to the parallel / serial conversion circuit 22 as a clock signal for synchronization. In addition, when starting transmission of a data signal, the data is stored in the memory circuit 34 in order to send test data capable of matching the phases of the data signal and the clock signal.

  Further, this clock signal is used only by the transmission circuit 15b, and is not transmitted through the cable as used in the reception circuit as in the conventional image transmission system. With such a system, the number of cables for transmission from the transmission circuit 15b to the reception circuit 16b can be reduced as compared with the prior art, and the cable connection can be simplified.

  On the other hand, an RGB parallel signal and a control signal, which are external data signals, are converted into serial signals by the parallel / serial conversion circuit 22. The voltage of the converted serial signal is converted by the differential buffer circuit 23 and transmitted from the channel A to the channel D, which is the wiring 13a, to the differential buffer circuit 24 of the receiving circuit 16b.

  These data signals are converted into parallel signals by the serial / parallel conversion circuit 25 of the receiving circuit 16b, and output to the image processing circuit as RGB parallel signals and control signals.

  On the other hand, in the receiving circuit 16b, the test data from the transmitting circuit 15b is received through a specific channel, for example, channel B, and the circuit is assembled internally so as to recover a signal corresponding to the clock (pseudo clock signal).

  Thus, unlike the conventional image transmission system, transmission through the wiring is not performed so that the clock signal can be used in the receiving circuit. With such a system, the wiring 13a for transmission from the transmission circuit 15b to the reception circuit 16b can be reduced as compared with the prior art, and the cable connection can be simplified.

  In the reception circuit 16 b, the repeated data of the pseudo clock signal from the transmission circuit 15 b is received by the clock generation circuit 32 via, for example, the channel B and transmitted to the selector 33 and also to the skew adjustment circuit 29. In addition, a signal from the built-in oscillator 26 or the external oscillator 27 attached to the outside is selected by the selector 28 and transmitted to the skew adjustment circuit 29. In the skew adjustment circuit 29, the phases of the clock signal from the reception circuit 16 b and the pseudo clock signal from the transmission circuit 15 b are synchronized and sent to the PLL circuit 30 through the selector 33. In accordance with the output from the PLL circuit 30, the data signal transmitted from the differential buffer circuit is converted by the serial / parallel conversion circuit 25.

  FIG. 7 is a flowchart showing the procedure for adjusting the timing of clock synchronization in this embodiment.

  After the start (S30), the reset is released from the reset state (S31) (S32). Subsequently, the transmission circuit 15b on the transmitter side outputs, for example, a pseudo clock signal, which is a test data signal combining a high level signal and a low level signal, at the beginning of transmission of a data signal, for example, through channel B ( S33). The receiver circuit 16b on the receiver side receives the signal by the clock generation circuit 32 and causes the PLL circuit 30 to follow the clock (S34). If there is no problem in the setup time (S35), the clock signal generated by the receiver circuit 16b on the receiver side is generated by the clock generator circuit 32 and switched.

  As described above, in the image transmission system, not only has the clock generation only on the transmitter side, but also sets the clock generation function on the receiver side, so that a cable for transmission from the transmission circuit to the reception circuit can be provided. It can be reduced, and the cable connection can be simplified and downsized.

  Further, since the pseudo clock signal is transmitted from the transmitter side to the receiver side through the channel for data transmission, the circuit configuration for generating the clock on the receiver side is relatively simplified.

  A third embodiment of the image transmission system according to the present invention will be described with reference to FIGS. FIG. 8 is a block circuit diagram showing a transmission unit in the image transmission system in the present embodiment. FIG. 9 is a timing chart showing data conversion of the transmission unit in this embodiment.

  The outline of the image transmission system in the present embodiment is basically the same as that in the first embodiment, and a description thereof will be omitted.

  FIG. 8 is a block circuit diagram showing a transmission unit 13c including a transmission circuit 15c, channels A to D as transmission cables, and a reception circuit 16c. In the transmission circuit 15c, an external signal is received by the PLL circuit 21, and a signal having a constant frequency is sent to the parallel / serial conversion circuit 22 as a clock signal for synchronization. In this embodiment, when transmission of a data signal is started, an index data signal indicating the head of the data signal is transmitted to the receiving circuit 16c together with the data signal. The index data is stored in the memory circuit 34.

  Further, this clock signal is used only in the transmission circuit 15c, and is not transmitted through the wiring as used in the reception circuit as in the conventional image transmission system. By such a system, the wiring 13a for transmission from the transmission circuit 15c to the reception circuit 16c can be reduced as compared with the prior art, and the cable connection can be simplified.

  On the other hand, an RGB parallel signal and a control signal, which are external data signals, are converted into serial signals by the parallel / serial conversion circuit 22. The converted serial signal is converted in voltage by the differential buffer circuit 23 and transmitted from the channels A to D, which are transmission cables, to the differential buffer circuit 24 of the receiving circuit 16c.

  These data signals are converted into parallel signals by the serial / parallel conversion circuit 25 of the receiving circuit 16c, and output to the image processing circuit as RGB parallel signals and control signals.

  In addition to the data signal, an index data signal that is a clock-corresponding signal (pseudo clock signal) is placed at the head of the data signal, and the index data is transmitted from the transmission circuit 15c to the reception circuit 16c through each channel. As a result, a clock is not transmitted, but a signal having the same frequency is transmitted, and therefore, it is effective as a signal corresponding to the clock (pseudo clock signal).

  On the other hand, in the receiving circuit 16c, an index data signal of the data signal is received through each channel of the transmitting circuit 15c, and an internal circuit is assembled so as to recover a signal corresponding to the clock (pseudo clock signal).

  Thus, unlike the conventional image transmission system, transmission is not performed from the transmission circuit 15c to the reception circuit 16c through the cable so that the clock signal can be used in the reception circuit. With such a system, the number of cables for transmission from the transmission circuit 15c to the reception circuit 16c can be reduced as compared with the prior art, and the cable connection can be simplified.

  In the receiving circuit 16 c, the index bit shown in FIG. 9 is determined by the clock generation circuit 32, the clock is recovered based on this pseudo clock signal, and the generated clock signal is input to the PLL circuit 30. The data signal transmitted from the differential buffer circuit is converted in the serial / parallel conversion circuit 25 by the output of the PLL circuit 30 following the recovered clock signal.

  The normal data per clock cycle is 7 bits. On the other hand, in this embodiment, the index bits are increased by, for example, 3 bits. Therefore, the data rate corresponding to that increases.

  As described above, in the image transmission system, not only has the clock generation only on the transmitter side, but also sets the clock generation function on the receiver side, so that a cable for transmission from the transmission circuit to the reception circuit can be provided. It can be reduced, and the cable connection can be simplified and downsized.

  In addition, since the index data signal is transmitted as a pseudo clock signal from the transmitter side to the receiver side through the data transmission channel, the circuit configuration for generating the clock on the receiver side is further simplified.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

  The reception circuit may be any circuit that can decode and output data based on a serial signal. For example, a standard reception circuit can be used in addition to the LVDS standard reception circuit.

  The image display apparatus connected to the image transmission system may be a CRT in addition to the LCD.

1 is a block circuit diagram showing a first embodiment of an image transmission system according to the present invention. The block circuit diagram which shows the transmission part in the 1st Example of the image transmission system by this invention. 3 is a timing chart of data conversion in the first embodiment of the image transmission system according to the present invention. 5 is a flowchart showing a procedure for adjusting the timing of data conversion in the first embodiment of the image transmission system according to the present invention. 3 is a timing chart of data conversion in the first embodiment of the image transmission system according to the present invention. The block circuit diagram which shows the transmission part in the 2nd Example of the image transmission system by this invention. 9 is a flowchart showing a procedure for adjusting the timing of data conversion in the second embodiment of the image transmission system according to the present invention. The block circuit diagram which shows the transmission part in the 3rd Example of the image transmission system by this invention. The timing chart of the data conversion in the 3rd Example of the image transmission system by this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Image transmission system 11 Transmitter 12 Receiver 13, 13b, 13c Transmission part 13a Transmission cable 14 Image control circuit 15, 15b, 15c Transmission circuit 16, 16b, 16c Reception circuit 17 Image processing circuit 21, 30 PLL circuit 22 Parallel / serial conversion Circuits 23 and 24 Differential buffer circuit 25 Serial / parallel conversion circuit 26 Oscillator 27 External oscillators 28 and 33 Selector 29 Skew adjustment circuit 31 1/7 Skew adjustment circuit 32 Clock generation circuit 34 Memory circuit

Claims (5)

A transmitter that converts a parallel image signal input from the outside into a serial image signal and sends it to a receiver;
A receiver that receives the serial image signal from the transmitter, converts the serial image signal to a parallel image signal, and outputs the parallel image signal;
A transmission cable unit for connecting the transmitter and the receiver and transmitting the serial image signal from the transmitter to the receiver;
The image transmission system, wherein the receiver includes means for generating a clock signal.   The receiver detects the timing corresponding to the clock signal from the image signal data and control signal transmitted from the transmitter, and generates the clock signal based on the detected timing corresponding to the clock signal and the phase of the control signal. The image transmission system according to claim 1, further comprising:   Means for generating a pseudo clock signal in the transmitter; means for transmitting the pseudo clock signal from the transmitter to the receiver through the transmission cable; and detecting the pseudo clock signal in the receiver; An image transmission system comprising: means for generating the clock signal based on the phase of the clock signal.   4. The image transmission system according to claim 3, wherein the pseudo clock signal is transmitted as a test data signal from the transmitter to the receiver through the transmission cable unit immediately after resetting the transmitter.   4. The image transmission system according to claim 3, wherein the pseudo clock signal is arranged as an index data signal at the head or tail of one cycle of the serial image signal.

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