JP2007110215A - Receiving apparatus, receiving method, and electronic apparatus using receiving apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a receiving apparatus or the like capable of realizing an operation adaptive to each of a plurality of display forms. <P>SOLUTION: The receiving apparatus 10 includes: a reception section 12 for receiving a display signal including digital video data transmitted by a small amplitude differential system; a video signal description rule detection section 16 for detecting description rules by each technical items about the display signal received by the reception section; a description rule storage section 20 for storing in advance the description rules by the technical items of a prescribed display form; a display form detection section 18 for detecting the display form of the display signal by comparing the description rules by the technical items detected by the video signal description rule detection section 16 with the description rules by the technical items stored in the description rule storage section 20 by each technical item; and an operation mode control section 22 for controlling the operating mode in accordance with the result of the detection by the display form detection section 18. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for receiving a display signal including digital video data transmitted by a small amplitude differential method.

2. Description of the Related Art In recent years, a transmission method called a small-amplitude differential method in which a video / audio transmission device and a reception device are connected by a single cable to transmit video / audio digital data is becoming widespread. In the small amplitude differential method, a signal whose phase is shifted by 180 degrees is passed through two signal lines, so that a strong signal can be transmitted even at a low voltage. Examples of standards conforming to the small amplitude differential method include DVI (Digital Visual Interface) standards and HDMI (High Definition Multimedia Interface) standards. The DVI standard is used for transferring video data, and is a connection standard for a personal computer (hereinafter also referred to as “PC”) and a display. The HDMI standard is an arrangement of the DVI standard for AV (Audio Visual) home appliances. In addition to video data, audio data and control signals between devices can be transferred. Patent Document 1 discloses a technique for multiplexing and transmitting data signals representing other than video during a blanking period of a video signal compliant with the DVI standard.
JP 2003877752 A

  In a receiving device included in an image display device that displays an image using a signal compliant with the small amplitude differential method, a display format that can be supported is determined in advance. Conventionally, a receiving device that receives a signal compliant with the small amplitude differential method has not been provided with a function of detecting the display format of the received signal. Therefore, when a user mistakenly connects a receiving apparatus and a transmitting apparatus that transmits a signal in a display format that does not correspond to the receiving apparatus, the receiving apparatus may malfunction. In this case, when a signal having a frequency higher than the specified operating frequency of the receiving device is input, the receiving device may be damaged beyond the allowable power.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to realize the operation of a receiving apparatus adapted to each of a plurality of display formats.

  One embodiment of the present invention relates to a receiving device. This receiving apparatus includes a receiving unit that receives a display signal including digital video data transmitted by a small amplitude differential method, and a description rule that detects a description rule for each technical item for the display signal received by the receiving unit. A detection unit, a description rule holding unit that holds in advance a description rule for each technical item in a predetermined display format, and a technology held in the description rule for each technical item detected by the description rule detection unit and the description rule holding unit A display format detection unit that detects the display format of the display signal by comparing the description rules for each item for each technical item, an operation mode control unit that controls the operation mode according to the detection result in the display format detection unit, Is provided. Here, the “technical item” may be an attribute that characterizes a signal. The “description rule” may be a specification related to the description of the signal such as the active level and timing of the signal.

  According to this aspect, since the operation mode control unit operates the circuit in accordance with the display format detected by the display format detection unit, it is possible to construct an optimum receiving system by adapting to each of the plurality of display formats. Can do.

  The operation mode control unit may limit the reception operation of the reception unit when the display format detection unit detects an incompatible display format. According to this aspect, when the display format detection unit detects a display format not supported by the receiving device, the operation mode control unit controls, for example, the reception unit to stop the reception operation of the input signal. Thus, malfunction of the receiving device can be avoided.

  The operation mode control unit may stop the operation of a circuit that is not used for processing the display signal whose display format is detected by the display format detection unit. According to this aspect, since the operation mode control unit stops the operation of the circuit that is not used for processing the detected display signal, the power consumption can be reduced accordingly.

  The display signal may conform to the HDMI standard or the DVI standard. As a result, it is possible to realize a favorable operation adapted to each of a plurality of display formats in a receiving device that receives display signals compliant with the HDMI standard or the DVI standard.

  In the receiving device, at least the receiving unit and the description rule detecting unit may be integrated on one semiconductor substrate. Note that “integrated integration” includes the case where all the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated, and is used for adjusting circuit constants. Part of the resistors, capacitors, and the like may be provided outside the semiconductor substrate. By integrating the control circuit as one LSI, the circuit area can be reduced.

  Another embodiment of the present invention relates to an electronic device. This electronic apparatus includes any of the receiving apparatuses described above and an image display unit that displays an image using a signal output from the receiving apparatus. According to this aspect, the receiving device operates in accordance with the display format detected by the display format detecting unit, and the image display unit displays an image using the signal output from the receiving device. As a result, the image display unit can display the image satisfactorily in accordance with the detected display format.

  Another aspect of the present invention relates to a receiving method. This reception method includes a reception step for receiving a display signal including digital video data transmitted by a small amplitude differential method, and a description rule detection for detecting a description rule for each technical item of the display signal received in the reception step. Display format detection step for detecting the display format of the display signal by comparing the description rule for each technical item detected in the step and the description rule detection step with the description rule for each technical item in a predetermined display format for each technical item And an operation mode control step for controlling the operation mode of the receiving device that receives the display signal in accordance with the detection result in the display format detection step.

  According to this aspect, in the operation mode control step, the operation of the receiving device is controlled corresponding to the display format detected in the display format detection step. Therefore, in accordance with each of the signals of the plurality of display formats, The receiving apparatus can be operated satisfactorily.

  It should be noted that any combination of the above-described constituent elements and a representation of the present invention converted between a method, an apparatus, a system, a computer program, etc. are also effective as an aspect of the present invention.

  According to the present invention, it is possible to realize the operation of a receiving apparatus adapted to each of a plurality of display formats.

  An outline of the present embodiment will be described. In the present embodiment, a receiving device included in an image display device that performs image display and audio reproduction using a received audiovisual signal (hereinafter referred to as “AV signal”) is a technical item of an AV signal. Another description rule is detected, and the detected description rule for each technical item and the description rule for each technical item held in advance are compared for each technical item to detect the display format of the AV signal. By determining the operation mode of the receiving device according to the detection result, malfunction of the receiving device is avoided.

  FIG. 1 is a block diagram illustrating a configuration of an electronic device according to an embodiment. This electronic device displays an image using a digital AV signal transmitted by a small amplitude differential method, and reproduces sound. The AV signal includes a video signal and an audio signal. In the present embodiment, the electronic device is described as an image display device that displays an image using an AV signal compliant with the HDMI standard and reproduces sound.

  The image display device 100 is, for example, a television signal receiving device provided with a connection port corresponding to the HDMI standard. This television signal receiver normally displays video received from an antenna. For example, an image is displayed using an AV signal output from a DVD player connected by a cable compliant with the HDMI standard, and audio is output. It is also possible to reproduce.

  The image display device 100 includes a receiving device 10, a speaker 24, and an image display unit 26. The receiver 10 receives an AV signal that conforms to the HDMI standard and is transmitted by the small amplitude differential method. In the HDMI standard, audio data is compressed and multiplexed and superimposed on a blanking period of a video signal. The image display unit 26 displays an image using a video signal included in a signal output from the receiving device 10. The speaker 24 reproduces sound using an audio signal included in a signal output from the receiving device.

  The receiving device 10 includes a receiving unit 12, a video signal description rule detecting unit 16, a display format detecting unit 18, a description rule holding unit 20, and an operation mode control unit 22. The reception unit 12 separates the video signal and the audio signal after decoding the AV signal input to the reception device 10 by TMDS (Transition Minimized Differential Signaling).

  The reception unit 12 includes a signal generation unit (not shown). The signal generation unit generates a horizontal synchronization signal, a vertical synchronization signal, and a data enable signal using a video signal. Specifically, a plurality of unique bits are provided between the video data interval and the blanking interval in the video signal, and the signal generation unit detects the position of the bit and generates a horizontal synchronization signal and a vertical synchronization signal. To do. Here, the value of the bit indicating the horizontal synchronizing signal is different from the value of the vertical synchronizing signal. The signal generation unit detects the value of the bit and generates a horizontal synchronization signal and a vertical synchronization signal, respectively. Further, the data enable signal is generated as a signal that becomes high level in the video data section. Hereinafter, “high level” for a signal is expressed as “high”, and “low level” is expressed as “low”.

  The receiving unit 12 outputs the video signal as a YUV signal that represents a color with three pieces of information: a luminance signal (Y), a difference between the luminance signal and the blue component (U), and a difference between the luminance signal and the red component (V). When the video signal is an RGB (Red Green Blue) signal, the receiving unit 12 converts the video signal into a YUV signal and outputs the YUV signal. The receiving unit 12 and the video signal description rule detecting unit 16 are integrated on a single semiconductor substrate.

  The video signal description rule detection unit 16 uses the synchronization signal and the data enable signal included in the video signal output from the reception unit 12 to detect a description rule for each technical item for detecting the display format of the AV signal. . The detection of the description rule for each technical item will be described later with reference to FIGS. The description rule holding unit 20 holds a description rule for each technical item in a plurality of display formats for detecting the display format of the AV signal. Specifically, the description rule holding unit 20 has a function of registering a description rule conforming to the HDMI standard, and can be realized by a logic circuit or microcomputer software. The display format detection unit 18 compares the description rule for each technical item detected by the video signal description rule detection unit 16 with the description rule for each technical item held by the description rule holding unit 20 for each technical item. The display format of the AV signal is detected.

  The operation mode control unit 22 detects whether or not an audio signal is included in the blanking period of the video signal for the AV signal input to the reception unit 12. Then, the operation mode control unit 22 controls the operation of the circuit in the receiving device 10 according to the display format detection result and the audio signal detection result in the display format detection unit 18. Here, the operation mode control unit 22 is realized by a logic circuit. The operation mode control unit 22 can also be realized by microcomputer software or personal computer software.

FIG. 2 is a block diagram showing a configuration of the video signal description rule detection unit 16. The video signal description rule detection unit 16 includes a horizontal signal description rule detection unit 28, a vertical signal description rule detection unit 30, and a parallel serial conversion unit 32.
The horizontal signal description rule detection unit 28 receives the data enable signal DE and the horizontal synchronization signal HSYNC included in the video signal. The horizontal signal description rule detection unit 28 uses these input signals to detect a description rule for each technical item for detecting the display format of the received AV signal, and the detected description rule for each technical item is detected. The following five types of description rule signals are output. The output signals are five kinds of signals including a horizontal polarity signal HPOL, a horizontal pixel value HPIXVAL, a horizontal front porch value HFPVAL, a horizontal back porch value HBPVAL, and a horizontal synchronization value HSYNCVAL.

  The vertical signal description rule detection unit 30 receives the data enable signal DE and the vertical synchronization signal VSYNC included in the video signal. Similarly to the horizontal signal description rule detection unit 28, the vertical signal description rule detection unit 30 also uses these input signals to detect a description rule for each technical item for detecting the display format of the received AV signal. Then, five types of description rule signals indicating the description rules for each detected technical item are output. The output signals are five types of signals including a vertical polarity signal VPOL, a vertical line value VLINVAL, a vertical front porch value VFPVAL, a vertical back porch value VBPVAL, and a vertical synchronization value VSYNCVAL.

  The parallel-serial conversion unit 32 includes a total of 10 types of description rules including five types of description rule signals output from the horizontal signal description rule detection unit 28 and five types of description rule signals output from the vertical signal description rule detection unit 30. Signals are input in parallel. The parallel-serial conversion unit 32 performs parallel-serial conversion processing on the input description rule signal, and outputs a detection description rule signal DDR that is a serial signal.

  FIG. 3 is a block diagram showing a configuration of the horizontal signal description rule detection unit 28. The horizontal signal description rule detection unit 28 includes a hazard removal circuit 36, an edge detection circuit 38, a video timing counter 40, a video timing register 42, and a polarity detection circuit 44. Here, an outline of the operation of each circuit will be described, and details of the operation will be described later with reference to FIGS.

  The hazard removal circuit 36 outputs a signal data enable signal DE ′ and a horizontal synchronization signal HSYNC ′ from which the hazard of the data enable signal DE and the horizontal synchronization signal HSYNC is removed. The edge detection circuit 38 uses the data enable signal DE ′ and the horizontal synchronization signal HSYNC ′ to generate a data enable rising edge signal DEP, a data enable falling edge signal DEN, a horizontal synchronization rising edge signal HSYNCP, and a horizontal synchronization falling edge signal. Generate and output HSYNCN.

The video timing counter 40 uses the data enable signal DE ′, the data enable rising edge signal DEP, the data enable falling edge signal DEN, the horizontal synchronization rising edge signal HSYNCP, and the horizontal synchronization falling edge signal HSYNCN to generate a horizontal pixel value. The horizontal front porch value, the horizontal back porch value, and the horizontal synchronization value are counted. The count result is output as a horizontal pixel count value HPIXCNT, a front porch count value HFPCNT, a back porch count value HBPCNT, and a horizontal synchronization count value HSYNCCNT.
Here, the horizontal pixel value is the number of pixels in one line of the image, the horizontal front porch value is the number of front porches of the horizontal sync signal, the horizontal back porch value is the number of back porches of the horizontal sync signal, and the horizontal sync value is active for the horizontal sync signal. Indicates a period that is not.

  The video timing register 42 holds the horizontal pixel count value HPIXCNT, the front porch count value HFPCNT, the back porch count value HBPCNT, and the horizontal synchronization count value HSYNCCNT at a predetermined timing. At this time, the holding timing is determined with reference to the data enable falling edge signal DEN, the horizontal synchronization rising edge signal HSYNCP, and the horizontal synchronization falling edge signal HSYNCN. These held values are used as a horizontal pixel value HPIXVAL, a horizontal front porch value HFPVAL, a horizontal back porch value HBPVAL, and a horizontal synchronization value HSYNCVAL, respectively, for detection of a display format.

  The polarity detection circuit 44 generates and outputs a horizontal polarity signal HPOL using the horizontal synchronization signal HSYNC 'and the data enable rising edge signal DEP. The horizontal polarity signal HPOL is a signal for determining whether the horizontal synchronization signal HSYNC is active high or active low.

  The configuration of the vertical signal description rule detection unit 30 is basically the same as the configuration of the horizontal signal description rule detection unit 28 described above. The vertical signal description rule detection unit 30 differs from the horizontal signal description rule detection unit 28 in that a vertical line value VLINVAL indicating the number of lines of one image is derived instead of the horizontal pixel value HPIXVAL. The vertical signal description rule detection unit 30 differs from the horizontal signal description rule detection unit 28 in that the data enable signal DE 'is not used in the counting operation by the video timing counter.

  FIG. 4 is a diagram showing a detailed configuration of the video timing counter 40 and the video timing register 42. The video timing counter 40 includes an HSYNC counter 50, an HPIX counter 52, an HFP counter 54, and an HBP counter 56. The HSYNC counter 50 counts the horizontal synchronization value, the HPIX counter 52 counts the horizontal pixel value, the HFP counter 54 counts the horizontal front porch value, and the HBP counter 56 counts the horizontal back porch value. These values are counted by counting the number of clocks in a predetermined period.

The video timing register 42 includes an HSYNC register 60, an HPIX register 62, an HFP register 64 and an HBP register 66. The HSYNC register 60 holds the horizontal synchronization count value HSYNCCNT, the HPIX register 62 holds the horizontal pixel count value HPIXCNT, the HFP register 64 holds the front porch count value HFPCNT, and the HBP register 66 holds the back porch count value HBPCNT.
The operations of the video timing counter 40 and the video timing register 42 will be described later with reference to FIGS.

The generation of signals in the horizontal signal description rule detection unit 28 will be described. Since the vertical signal description rule detection unit 30 generates the same signal as the horizontal signal description rule detection unit 28, the description of the vertical signal description rule detection unit 30 is omitted.
FIG. 5 is a timing chart showing signal generation in the hazard removal circuit 36, the edge detection circuit 38, and the polarity detection circuit 44. A signal CLK shown in the figure is a clock signal input to the horizontal signal description rule detection unit 28.

  The polarity of the horizontal synchronization signal HSYNC shown in FIG. 5 is positive, that is, active high. However, when the horizontal synchronization signal HSYNC is input to the hazard removal circuit 36, the receiving apparatus 10 does not recognize whether the horizontal synchronization signal HSYNC is active high or active low. The horizontal synchronization signal HSYNC 'changes when the same value is maintained until a predetermined number of clocks elapses after the value of the horizontal synchronization signal HSYNC changes. FIG. 5 shows a state in which the horizontal synchronization signal HSYNC ′ is changed from low to high (arrow a) when three clocks have elapsed after the horizontal synchronization signal HSYNC changes from high to low (arrow a), and the horizontal synchronization signal HSYNC changes from low to high. In the example, the horizontal synchronization signal HSYNC ′ is changed from high to low (arrow b) when the clock has elapsed.

  Generally, when a hazard occurs in the horizontal synchronization signal HSYNC, the value of the signal changes for a very short period. Here, after the value of the horizontal synchronization signal HSYNC changes, if the value is maintained for a predetermined period, it can be determined that the change in the value of the horizontal synchronization signal HSYNC is not due to a hazard. In the present embodiment, after the horizontal synchronization signal HSYNC is changed, the value of the horizontal synchronization signal HSYNC ′ is changed when a predetermined number of clocks have passed with the same value. Therefore, the change in the value due to the hazard is changed to the value of the horizontal synchronization signal HSYNC. It is possible to avoid erroneous detection as a change in polarity.

The data enable signal DE ′ is also generated by a method similar to the generation of the horizontal synchronization signal HSYNC ′ described above. That is, as shown in FIG. 5, the data enable signal DE ′ is changed from low to high when the data enable signal DE has the same value until three clocks have elapsed since the change from low to high (arrow e). . In addition, when the data enable signal DE is the same value until three clocks have passed since the data enable signal DE changed from high to low, the data enable signal DE ′ is changed from high to low (arrow f). Here, it is determined in advance that the data enable signal DE is active high. At the time when the data enable signal DE is input to the hazard removal circuit 36, the receiving apparatus 10 has the horizontal synchronization signal HSYNC active high. I recognize that.
Thus, the generated horizontal synchronization signal HSYNC ′ and data enable signal DE ′ are output from the hazard removal circuit 36.

  In the edge detection circuit 38, the horizontal synchronization rising edge signal HSYNCP becomes high for one clock when the horizontal synchronization signal HSYNC 'changes from low to high (arrow c). The horizontal synchronization falling edge signal HSYNCN becomes high for one clock when the horizontal synchronization signal HSYNC 'changes from high to low (arrow d). That is, the horizontal synchronization edge signal HSYNCP is a signal for detecting the rising of the horizontal synchronization signal HSYNC ', and the horizontal synchronization edge signal HSYNCN is a signal for detecting the falling of the horizontal synchronization signal HSYNC'.

  In the edge detection circuit 38, the data enable rising edge signal DEP becomes high for one clock when the data enable signal DE 'changes from low to high (arrow g). The data enable falling edge signal DEN becomes high for one clock when the data enable signal DE 'changes from high to low (arrow h). That is, the data enable rising edge signal DEP is a signal for detecting the rising edge of the data enable signal DE ', and the data enable falling edge signal DEN is a signal for detecting the falling edge of the data enable signal DE'.

  The polarity detection circuit 44 detects the value of the horizontal synchronization signal HSYNC at the time when the data enable rising edge signal DEP changes from low to high (arrow i and arrow j), and when the detected value is low, the polarity detection circuit 44 The horizontal polarity signal HPOL that changes from high to high and remains low when it is high is generated.

  While the data enable signal DE is active, the horizontal synchronization signal HSYNC is not always active. Thus, by detecting the value of the horizontal synchronization signal HSYNC at the time when the data enable signal DE ′ becomes active, the horizontal synchronization signal HSYNC is detected. It can be determined whether the synchronization signal HSYNC is active high or active low. That is, when the horizontal polarity signal HPOL changes from low to high, it can be determined that the horizontal synchronization signal HSYNC is active high, and when the horizontal polarity signal HPOL remains low, the horizontal synchronization signal HSYNC is active low. In FIG. 5, the horizontal polarity signal HPOL changes from low to high, and it is determined that the horizontal synchronization signal HSYNC is active high.

  FIG. 6 is a timing chart showing a process of acquiring the horizontal pixel count value HPIXCNT. A signal CLK shown in the figure is a clock signal input to the horizontal signal description rule detection unit 28. The conditions for starting and stopping the counting by the HPIX counter 52 and the conditions for the HPIX register 62 to hold the counted value are shown below.

HPIX count start condition: “Detection of rising edge of data enable signal DE ′”
HPIX count stop condition: “Detection of falling edge of data enable signal DE ′”
HPIX holding condition: “Detects rising of horizontal sync signal HSYNC '”

  When the rising edge of the data enable signal DE ′ is detected and the data enable rising edge signal DEP becomes high for one clock, the HPIX count start condition is satisfied, so the video timing counter 40 starts counting the number of clocks. (Arrow k). When the falling edge of the data enable signal DE ′ is detected and the data enable falling edge signal DEN becomes high for one clock, the HPIX count stop condition is satisfied, so the video timing counter 40 stops counting the number of clocks. The value is held as a horizontal pixel count value HPIXCNT (arrow l). When the rising edge of the horizontal synchronization signal HSYNC ′ is detected and the horizontal synchronization rising edge signal HSYNCP becomes high for one clock, the HPIX holding condition is satisfied, so the horizontal pixel count value HPIXCNT is held in the HPIX register 62. (Arrow m and arrow n). At the same time, the value of the HPIX counter 52 is reset to zero.

In the vertical signal description rule detection unit 30, the video timing counter and the video timing register operate in the same manner as the horizontal signal description rule detection unit 28.
However, as described above, the vertical signal description rule detection unit 30 differs from the horizontal signal description rule detection unit 28 in that the vertical line value VLINVAL is derived instead of the horizontal pixel value HPIXVAL. The rise and fall of the data enable signal DE ′ are detected a plurality of times before the rise of the vertical synchronization signal VSYNC ′ is detected. In this case, when the fall of the data enable signal DE ′ is detected, the HPIX counter 52 stops the count operation while holding the value counted up to that point, and the rise of the data enable signal DE ′ is detected. Sometimes the count operation is restarted from that value.

  Since the value to be counted by the HPIX counter 52 is the number of pixels of one screen, and the number is not necessarily small, it may be impossible for the HPIX counter 52 to count the value. In such a case, the HPIX counter 52 can count the number of times the rising edge of the data enable signal DE 'is detected. As a result, it can be recognized that all the pixels of one screen have been counted, so that it is possible to detect a description rule for each technical item.

FIG. 7 is a timing chart showing a process of obtaining the front porch count value HFPCNT, the back porch count value HBPCNT, and the horizontal synchronization count value HSYNCCNT. A signal CLK shown in the figure is a clock signal input to the horizontal signal description rule detection unit 28.
The conditions for starting and stopping the counting by the HFP counter 54, the HBP counter 56, and the HSYNC counter 50, and the conditions for the HFP register 64, the HBP register 66, and the HSYNC register 60 to hold the counted values are shown below.

HFP count start condition: “Detection of falling edge of data enable signal DE ′”
HFP count stop condition: "Detects rising of horizontal sync signal HSYNC '"
HFPCNT holding conditions: (A) “detection of rising edge of horizontal synchronization signal HSYNC ′” and (B) “value of HFP counter 54 is greater than“ 0 ””

HBP count start condition: (A) “detection of falling edge of horizontal synchronization signal HSYNC ′” and (B) “value of HFP counter 54 is“ 0 ””
HBP count stop condition: “Detection of rising edge of data enable signal DE ′”
HBPCNT holding conditions: (A) “detection of rising edge of data enable signal DE ′” and (B) “value of HBP counter 56 is greater than“ 0 ””

HSYNC count start condition: (A) “horizontal synchronization signal HSYNC 'rising detection” and (B) “the value of HFP counter 54 is greater than“ 0 ””
HSYNC count stop condition: "Detects falling of horizontal sync signal HSYNC '"
HSYNCCNT holding conditions: (A) “detection of falling edge of horizontal synchronization signal HSYNC ′” and (B) “values of HFP counter 54 and HBP counter 56 are“ 0 ””

  When the falling edge of the data enable signal DE ′ is detected and the data enable falling edge signal DEN becomes high for one clock, the HFP count start condition is satisfied, so the HFP counter 54 starts counting the number of clocks ( Arrow p). When the rising edge of the horizontal synchronizing signal HSYNC ′ is detected and the horizontal synchronizing rising edge signal HSYNCP becomes high for one clock, the HFP count stop condition is satisfied, and the HFP counter 54 stops counting the number of clocks ( Arrow q). At this time, since the value of the HFP counter 54 is larger than “0”, the conditions (A) and (B) of the HFPCNT holding condition are satisfied, and the value counted by the HFP counter 54 is the HFP register 64 as the front porch count value HFPCNT. (Arrow r and arrow u). At the same time, the value of the HFP counter 54 is reset to “0”.

  When the falling edge of the horizontal synchronization signal HSYNC 'is detected and the horizontal synchronization falling edge signal HSYNCN becomes high for one clock, the value of the HFP counter 54 is reset to "0". Therefore, since the HBP count start condition is satisfied, the HBP counter 56 starts counting the number of clocks (arrow v and arrow w). When the rising edge of the data enable signal DE ′ is detected and the data enable rising edge signal DEP becomes high for one clock, the HBP counter stop condition is satisfied, so the HBP counter 56 stops counting the number of clocks. (Arrow x). At this time, since the value of the HBP counter 56 is larger than “0”, the conditions (A) and (B) of the HBPCNT holding condition are satisfied, and the value counted by the HBP counter 56 is the back porch count value HBPCNT as the HBP register 66. (Arrow y and arrow z). At the same time, the value of the HBP counter 56 is reset to “0”.

  When the rising edge of the horizontal synchronization signal HSYNC 'is detected and the horizontal synchronization rising edge signal HSYNCP becomes high for one clock, the value held by the HFP counter 54 is greater than "0". Accordingly, since the HSYNC count start condition is satisfied, the HSYNC counter 50 starts counting the number of clocks (arrow a 'and arrow b'). When the fall of the horizontal sync signal HSYNC 'is detected and the horizontal sync fall edge signal HSYNCN becomes high for one clock, the HSYNC count stop condition is satisfied, so the HSYNC counter 50 stops counting the number of clocks. (Arrow c '). At this time, since the values of the HFP counter 54 and the HBP counter 56 are reset to “0”, the conditions (A) and (B) of the HSYNCCNT holding condition are satisfied, and the value counted by the HSYNC counter 50 is The horizontal synchronization count value HSYNCCNT is held in the HSYNC register 60 (arrow d ′ to arrow g ′). At the same time, the value of the HSYNC counter 50 is reset to “0”.

  FIG. 8 is a diagram illustrating an example of a table in which description rules for each technical item in the display format held by the description rule holding unit 20 are described. As shown in the figure, the description rule holding unit 20 includes a table 70 (hereinafter referred to as “display format”) that describes description rules for each technical item of a plurality of display formats that are referred to in the display format detection by the display format detection unit 18. Table 70 ”) is stored in advance. All the display formats described in the display format table 70 are display formats supported by the receiving device 10. In the illustrated display format table 70, description rules for six types of technical items “POL”, “FPVAL”, “BPVAL”, “HPIXVAL”, “VLINVAL”, and “SYNCVAL” are described. “POL” indicates whether each of the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC is active high or active low, “FPVAL” indicates the number of front porches, “BPVAL” indicates the number of back porches, and “HPIXVAL” indicates 1 The number of pixels in a line, “VLINVAL” represents the number of lines in one screen, and “SYNCVAL” represents a period in which the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC are not active. In the figure, description rules for each technical item are described in the display format table 70 for the three display formats X, Y, and Z.

  The display format detection unit 18 includes a description rule for each technical item detected by the video signal description rule detection unit 16 and a technical item for each display format described in the display format table 70 held in the description rule holding unit 20. Compare each with another description rule. As a result, when each of the description rules for each technical item detected by the video signal description rule detection unit 16 matches the description rule for each technical item shown in the display format X, for example, the display format detection unit 18 The display format of the AV signal is determined to be display format X. The operation mode control unit 22 controls a circuit in the reception device 10 so as to operate in an operation mode corresponding to the display format X according to the determination result. As described above, the operation mode control unit 22 controls the operation mode according to the detected display format, thereby realizing the operation of the receiving apparatus adapted to each of the plurality of display formats.

The operation of the receiving apparatus 10 based on the above configuration will be described below.
FIG. 9 is a flowchart showing the operation of the receiving device 10. First, the user connects an apparatus for transmitting AV signals, such as a DVD player or a PC, and the image display apparatus 100 with a cable conforming to the HDMI standard. When the user operates the transmission device to transmit an AV signal to the image display device 100, the reception device 10 receives the AV signal (S10). Next, the video signal description rule detection unit 16 detects a description rule for each technical item for specifying the display format of the AV signal (S12). The display format detection unit 18 compares the description rule for each technical item detected by the video signal description rule detection unit 16 with the description rule for each technical item of the display format held in the description rule holding unit 20. The display format of the received AV signal is detected (S14).

  When the detected display format is one of the display formats held in the description rule holding unit 20 as a result of the display format detection by the display format detection unit 18 (Y in S16), the operation mode control unit 22 It is determined whether there is a circuit in the receiving apparatus 10 that is not used for processing the AV signal (S18). As a result of the determination, if there is a circuit that is not used (Y in S18), the operation mode control unit 22 performs control to stop the operation of the circuit by stopping power supply by stopping the supply of the clock to the circuit that is not used. Execute (S20). Thereby, the power consumption of the receiving device 10 can be reduced.

  Further, as described above, the operation mode control unit 22 detects the audio signal included in the blanking period of the video signal for the AV signal input to the reception unit 12. As a result, when an audio signal is not detected, the operation mode control unit 22 can also perform control to limit the operation of the circuit in the receiving apparatus 10 that is not used for processing the audio signal. In this case, for example, the operation mode control unit 22 powers down a circuit used for processing an audio signal and stops the operation of the circuit. Specifically, control is performed to stop the supply of clocks to circuits that are not used for processing these audio signals. This also makes it possible to reduce the power consumption of the entire receiving apparatus 10.

  In S16, when the detected display format is not one of the display formats held in the description rule holding unit 20 (N in S16), the display format detecting unit 18 determines that the received AV signal is displayed in the receiving device 10. Is not a compatible display format, that is, the display format is not compatible. And the operation mode control part 22 performs control which stops operation | movement of the circuit of the receiving part 12 (S22). For example, the operation mode control unit 22 powers down the circuit in the reception unit 12. Specifically, for example, the operation mode control unit 22 performs control to stop the supply of the clock to the reception unit 12 and restricts the reception operation. Thus, by stopping the reception of the AV signal, it is possible to avoid malfunction of the receiving device 10 due to the AV signal in the display format that the receiving device 10 does not support. Further, when the AV signal in a display format that is not supported by the receiving device 10 is a signal having a specified operating frequency or higher, damage to the receiving device 10 due to exceeding the allowable power can be avoided. In S18, when there is no circuit that is not used for processing the received AV signal (N in S18), the operation of the circuit in the receiving device 10 is not stopped, and the receiving device 10 operates in an operation mode corresponding to the detected display format. It works by.

  The present invention has been described based on the embodiments. The embodiments are exemplifications, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. . For example, the following modifications can be considered.

  In the present embodiment, the signal transmitted to the image display apparatus 100 conforms to the HDMI standard, but as a modification, the transmitted signal may be a signal conforming to the DVI standard. Also by this, when the display format of the received signal is not the display format that the receiving device 10 corresponds to, the receiving operation of the receiving unit 12 is stopped, and the malfunction of the receiving device 10 can be avoided. Further, since the audio data is not included in the signal conforming to the DVI standard, the operation mode control unit 22 can execute the control to stop the operation of the circuit that processes the audio signal, thereby realizing reduction in power consumption. .

In the present embodiment, the example in which the operation mode control unit 22 limits the operation of the circuit in the receiving device 10 according to the detection result of the display format detection unit 18 has been described. As a modification, a data processing unit may be provided in the receiving device 10, and the data processing unit may process data according to the detection result in the display format detection unit 18.
In general, in the receiving apparatus, a predetermined calculation is performed on video data in each display format, and scaling processing is performed to interpolate or thin out pixel data so as to be displayed on the image display unit 26 satisfactorily. For example, in this modification, the data processing unit holds in advance a table in which each display format is associated with the result of the scaling process, and refers to the table according to the detection result of the display format detection unit 18. The result of the scaling process can be easily obtained without performing the calculation of the scaling process. Thereby, the burden of the circuit in the receiver 10 can be reduced.

  In the present embodiment, the display format detection unit 18 compares the detected description rule for each technical item with the description rules for all technical items described in the display format table 70. As a modification, the description rule for each technical item detected may be compared with a part of the description rule for each technical item described in the display format table 70 according to user settings.

  In the present embodiment, the display format of the received signal of the AV signal depends on whether or not the detected description rule for each technical item matches the description rule for each technical item in the display format described in the display format table 70. It was determined whether or not the receiving apparatus 10 has a corresponding display format. As a modification, even if a predetermined tolerance is provided and the description rule for each technical item does not match, the display format of the received AV signal is a display format supported by the receiving device 10 within the tolerance. May be determined. Thereby, the flexibility of the operation of the receiving device 10 with respect to the received signal can be ensured.

It is a block diagram which shows the structure of the electronic device which concerns on embodiment. It is a block diagram which shows the structure of a video signal description rule detection part. It is a block diagram which shows the structure of a horizontal signal description rule detection part. It is a figure which shows the detailed structure of a video timing counter and a video timing register. It is a timing chart which shows the production | generation of the signal in a hazard removal circuit, an edge detection circuit, and a polarity detection circuit. It is a timing chart which shows the process of acquiring a horizontal pixel count value. It is a timing chart which shows the process in which a front porch count value, a back porch count value, and a horizontal synchronization count value are acquired. It is a figure which shows the example of the display format table which a description rule holding part hold | maintains. It is a flowchart which shows operation | movement of a receiver.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 receiving apparatus, 12 receiving part, 16 video signal description rule detection part, 18 display format detection part, 20 description rule holding part, 22 operation mode control part, 24 speaker, 26 image display part, 28 horizontal signal description rule detection part, 30 vertical signal description rule detection unit, 32 parallel serial conversion unit, 36 hazard removal circuit, 38 edge detection circuit, 40 video timing counter, 42 video timing register, 44 polarity detection circuit, 50 HSYNC counter, 52 HPIX counter, 54 HFP counter 56 HBP counter, 60 HSYNC register, 62 HPIX register, 64 HFP register, 66 HBP register, 70 display format table, 100 image display device.

Claims (7)

A receiver for receiving a display signal including digital video data transmitted by a small amplitude differential method;
A description rule detection unit that detects a description rule for each technical item for the display signal received in the reception unit;
A description rule storage unit for storing in advance a description rule for each technical item in a predetermined display format;
The display format of the display signal is detected by comparing the description rule for each technical item detected by the description rule detection unit with the description rule for each technical item held in the description rule holding unit for each technical item. A display format detector to
An operation mode control unit that controls an operation mode according to a detection result in the display format detection unit;
A receiving apparatus comprising:   The receiving apparatus according to claim 1, wherein the operation mode control unit restricts a receiving operation of the receiving unit when the display format detecting unit detects a non-compatible display format.   The receiving apparatus according to claim 1, wherein the operation mode control unit stops an operation of a circuit not used for processing the display signal whose display format is detected by the display format detection unit.   The receiving apparatus according to any one of claims 1 to 3, wherein the display signal conforms to a high definition multimedia interface (HDMI) standard or a digital visual interface (DVI) standard.   The receiving apparatus according to claim 1, wherein at least the receiving unit and the description rule detecting unit are integrated on a single semiconductor substrate. A receiving device according to any one of claims 1 to 5;
An image display unit for displaying an image using a signal output from the receiving device;
An electronic device comprising: A receiving step of receiving a display signal including digital video data transmitted by a small amplitude differential method;
A description rule detection step for detecting a description rule for each technical item of the display signal received in the reception step;
A display format detection step of detecting the display format of the display signal by comparing the description rule for each technical item detected in the description rule detection step with the description rule for each technical item of a predetermined display format for each technical item; ,
An operation mode control step for controlling an operation mode of a receiving device that receives the display signal according to a detection result in the display format detection step;
A receiving method comprising:

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