JP2011130319A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a hazard from being included in a signal to be output to the outside of a semiconductor device. <P>SOLUTION: In the semiconductor device, an IO cell 23_1 includes a timing adjustment circuit 50 and an output buffer 70. The output buffer 70 receives a data signal DOc, with a timing adjusted by the timing adjustment circuit 50 and an output permission signal OEc. The timing adjustment circuit 50 adjusts the timing of at least one of a data signal DO and an output permission signal OE received from an IO port logic circuit 18 so that the output permission signal OEc is changed-over, from an inactive state to an active state, after the data signal DOc changes to a logical level to be output, when the data signal DOc and the output permission signal OEc are input to the output buffer 70, and the output permission signal OEc is changed over from an active state to an inactive state, while the data signal DOc holds the logical level to be output. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a hazard can occur.

  Hazard means that when a plurality of input signals change with a minute time difference in a logic circuit that operates in synchronization with an operation clock of a predetermined frequency, the original is output transiently due to the delay of the signal arrival time. A signal having a logic level different from the logic level. Hazards are observed as very short pulses (so-called “beards”). For example, the following circuits are known as circuits for removing hazards.

  The hazard removal circuit described in Japanese Patent Laid-Open No. 11-214965 (Patent Document 1) includes first and second delay circuits, a negative exclusive OR circuit, and a D flip-flop circuit. The first delay circuit delays an input signal including a hazard. The negative exclusive OR circuit receives an input signal including a hazard and an output signal of the first delay circuit. The second delay circuit further delays the output signal of the negative exclusive OR circuit. The D flip-flop circuit receives an input signal including a hazard as a data signal, and receives an output signal of the second delay circuit as a clock signal.

  Japanese Patent Laying-Open No. 2009-116047 (Patent Document 2) discloses a display device in which a hazard is suppressed. The display device of this document includes a decoding circuit, a hazard signal removing circuit that removes a hazard signal generated in an output signal from the decoding circuit using an output signal from the decoding circuit, and an output signal from the hazard signal removing circuit. A driven pixel.

Japanese Patent Laid-Open No. 11-214965 JP 2009-116047 A

  In recent years, an automatic place-and-route tool is used for designing an LSI (Large-Scale Integration). With the automatic placement and routing tool, each macro cell (functional block) is optimally placed so that the circuit area is minimized, and the macro cells are routed. Therefore, it is difficult for the designer to specify the wiring route between the macro cells in detail. It is. For this reason, depending on the wiring path between the macro cells, a signal arrival time may be shifted (skew) due to wiring delay, and as a result, a hazard may occur. In addition, since the device sensitivity of the semiconductor circuit has increased due to advances in the semiconductor process, the hazard once generated propagates without disappearing.

  A main object of the present invention is to prevent a hazard from being included in a signal output to the outside of an LSI chip (semiconductor device) via an external connection terminal (pad).

  A semiconductor device according to an embodiment of the present invention includes an internal circuit, a plurality of pads, and a plurality of interface units provided corresponding to the plurality of pads, respectively. Each interface unit receives a data signal and an output permission signal from an internal circuit. Each interface unit includes a timing adjustment circuit and an output buffer. In each interface unit, the timing adjustment circuit adjusts the timing of at least one of the data signal and the output permission signal received from the internal circuit. The output buffer receives the data signal and the output permission signal after the timing adjustment by the timing adjustment circuit, and outputs the data signal to the outside through the corresponding pad when the output permission signal is in the active state. When the data signal and the output enable signal are input to the output buffer, the timing adjustment circuit changes the output enable signal from the inactive state after the data signal changes to the logic level to be output while the output enable signal is in the active state. The data signal is switched so that the output permission signal switches from the active state to the inactive state while the data signal holds the logic level to be output while the output permission signal is in the active state. And the timing of at least one of the output permission signals is adjusted.

  According to the semiconductor device of this embodiment, since the timing adjustment circuit of each interface unit adjusts the timing of at least one of the data signal and the output permission signal, the signal output to the outside via the corresponding pad Hazard can be excluded.

1 is a functional block diagram showing an overall configuration of a microcomputer 100 according to Embodiment 1 of the present invention. FIG. 2 is a functional block diagram illustrating a configuration related to an IO port logic circuit 18 in the microcomputer 100 of FIG. 1. It is a circuit diagram which shows the structure of the part relevant to a data output among IO cells 23_1. FIG. 4 is a circuit diagram showing an example of a configuration of a delay circuit 53A in FIG. FIG. 10 is a timing diagram for explaining a hazard that occurs when the output permission signal OE rises. FIG. 10 is a timing diagram for explaining a hazard that occurs when the output permission signal OE falls. FIG. 5 is a timing diagram for explaining the operation of first and second signal delay units 51 and 52. FIG. 3 is a plan view showing an example of a layout of IO cells 23 and pads 24 in FIG. 2. FIG. 5 is a circuit diagram showing a configuration of a delay circuit 55 as a first modification of the delay circuit 53 of FIG. 4. FIG. 6 is a circuit diagram showing a configuration of a delay circuit 56 as a second modification of the delay circuit 53 in FIG. 4. FIG. 6 is a circuit diagram showing a configuration of a delay circuit 57 as a third modification of the delay circuit 53 in FIG. 4. FIG. 4 is a circuit diagram showing a modification of the timing adjustment circuit 50 of FIG. 3. It is a circuit diagram which shows the structure of the part relevant to a data output among IO cells 23A_1 used for the semiconductor device by Embodiment 2 of this invention. FIG. 14 is a timing chart for explaining the operation of the hazard removal circuit 91A of FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. Hereinafter, a microcomputer will be described as an example of a semiconductor device, but the present invention is not limited to application to a microcomputer.

<Embodiment 1>
[Overall Configuration of Microcomputer 100]
FIG. 1 is a functional block diagram showing the overall configuration of a microcomputer 100 according to Embodiment 1 of the present invention.

  Referring to FIG. 1, a microcomputer 100 includes a CPU (Central Processing Unit) 2, an interrupt controller (INT) 3, a ROM (Read-Only Memory) 4, a RAM (Random Access Memory) 5, a timer [A] 6, Timer [B] 7, serial communication interface (SCI) 8, A / D (Analog-to-Digital) converter 9, first to ninth IO (Input-Output) port logic circuits (IOP [1] to IOP [9]) Functional blocks (modules) of 11 to 19, a clock pulse generator (CPG) 20, and a system controller (SYSC) 21 are included. The CPU 2 governs overall control. The ROM 4 is a memory that stores a processing program of the CPU 2 and the like. The RAM 5 is a memory used for temporary storage of the work area and data of the CPU 2. The system controller 21 is provided with a control register (CPUCR) 22. The microcomputer 100 is formed on a single semiconductor substrate 1 such as single crystal silicon by a known semiconductor manufacturing technique.

  The microcomputer 100 further has input terminals for ground voltage (Vss), external power supply voltage (Vcc), analog ground voltage (AVss), analog power supply voltage (AVcc), and analog reference voltage (Vref) as power supply terminals. The microcomputer 100 has terminals such as reset (RES), standby (STBY), mode control (MD0, MD1, MD2), clock input (EXTAL, XTAL), etc. as dedicated control terminals.

  The microcomputer 100 operates in synchronization with a reference clock (system clock) generated based on a crystal oscillator connected to the XTAL terminal of the CPG 20 or an external clock input to the EXTAL terminal.

  The functional blocks of the microcomputer 100 are connected to each other by an internal bus 30. The microcomputer 100 includes a bus controller (not shown) that controls the bus. The internal bus 30 includes a control bus for transmitting commands such as a read signal and a write signal in addition to an address bus and a data bus.

  Microcomputer 100 further includes a plurality of IO cells 23 (also referred to as interface units (IF)) and a plurality of pads 24 respectively corresponding to the plurality of IO cells 23. A predetermined number of pads 24 are connected to each of the IO port logic circuits 11 to 19 via corresponding IO cells 23. The pad 24 is used as a general-purpose input / output terminal of the microcomputer 100 and also as an input / output terminal of a built-in module. Specifically, IO port logic circuits 15 to 17 are connected to timers 6 to 8 in addition to internal bus 30. A part of the pad 24 connected to the IO port logic circuits 15 to 17 also serves as input / output terminals for the timers 6 and 7. Similarly, a part of the pad 24 connected to the IO port logic circuit 18 also serves as an input / output terminal of the SCI 8, and a part of the pad 24 connected to the IO port logic circuit 19 is an input terminal of the A / D converter 9. Also doubles.

  The timers 6 and 7, the SCI 8, the A / D converter 9, and the IO port logic circuits 11 to 19 output an interrupt signal 32 to the interrupt controller 3 based on a signal input from the outside of the microcomputer 100. In response to the interrupt signal 32, the interrupt controller 3 issues an interrupt request 31 to the CPU 2.

  In this specification, among the components of the microcomputer 100, the functional block portion excluding the IO cell 23 and the pad 24 is referred to as an internal circuit 25. Each functional block constituting the internal circuit 25 is arranged so that the circuit area becomes as small as possible by an automatic wiring arrangement tool at the time of design.

[Configuration of IO port logic circuit and IO cell]
Next, the configuration of the IO port logic circuits 11 to 19 and each IO cell 23 will be described in detail. Since the configuration of each IO cell 23 is the same and the configuration of the IO port logic circuits 11 to 19 is also substantially the same, the IO port logic circuit 18 and the IO cell 23 connected to the IO port logic circuit 18 will be described below as representatives.

  FIG. 2 is a functional block diagram showing a configuration related to the IO port logic circuit 18 in the microcomputer 100 of FIG. As shown in FIG. 2, predetermined n IO cells 23_1 to 23_n (IF [1] to IF [n]) are connected to the IO port logic circuit 18, and the IO cells 23_1 to 23_n are respectively associated with corresponding pads. 24_1 to 24_n are connected. The IO cells 23_1 to 23_n and the pads 24_1 to 24_n are simply referred to as the IO cells 23 and the pads 24 when collectively referred to or unspecified.

  Each IO cell 23_i (i is an integer of 1 to n) receives the output data signal DO_i and the output permission signal OE_i from the IO port logic circuit 18. When the output permission signal OE_i is in the active state, the IO cell 23_i outputs the output data signal DO_i through the corresponding pad 24_i. Conversely, the IO cell 23_i outputs the input data signal DI_i received via the corresponding pad 24_i to the IO port logic circuit 18 when the output permission signal OE_i is inactive. In this embodiment, the logic level of the output permission signal OE is positive logic (H level when in the active state and L level when in the inactive state), but it is not necessarily required to be positive logic. .

  The IO port logic circuit 18 includes a selector 43, a direction register 41, and a port latch 42 provided for controlling input / output of data signals to / from the outside.

  The selector 43 has a function of switching whether the pad 24 is used as a general-purpose input / output terminal or a serial signal input / output terminal by the SCI 8 in accordance with a command from the SCI 8.

  The direction register 41 is provided to specify whether the pad 24 is used as an input terminal or an output terminal when the pad 24 is used as a general-purpose input / output terminal. Data for instructing the input function or the output function is input to the direction register 41 via the internal bus 30, and the input / output function of the IO cell 23 is switched according to the data held in the direction register 41.

  The port latch 42 is a flip-flop that temporarily stores output data signals DO_1 to DO_n and input data signals DI_1 to DI_n when the pad 24 is used as a general-purpose input / output terminal.

  Hereinafter, the configuration of the portion related to the data output related to the present invention will be described in more detail. Hereinafter, the configuration of the IO cell 23_1 will be described as a representative.

  FIG. 3 is a circuit diagram showing a configuration of a portion related to data output in the IO cell 23_1. The configuration of the IO port logic circuit 18 related to data output is also shown in FIG.

  As shown in FIG. 3, the IO port logic circuit 18 includes selectors 43A and 43B provided to switch the output function of the IO cell 23_1. Selector 43A is connected to direction register 41 and receives SCI output permission signal 37A from SCI8. Selector 43B is connected to port latch 42 and receives SCI output permission signal 37A and SCI output data signal 37B from SCI8.

  When the SCI output permission signal 37A is in the active state (H level), the selector 43A sets the output permission signal OE_1 (hereinafter simply referred to as OE) output to the IO cell 23_1 to the active state (H level). Further, selector 43B outputs SCI output data signal 37B received from SCI 8 to IO cell 23_1 as output data signal DO_1 (hereinafter abbreviated as DO).

  When the SCI output enable signal 37A is in an inactive state (L level), the selector 43A outputs an H level or L level output enable signal OE to the IO cell 23_1 according to the corresponding bit data of the direction register 41. Further, the selector 43B outputs the data held in the corresponding flip-flop of the port latch 42 to the IO cell 23_1. When the corresponding bit data of the direction register 41 is “1” (H level), the output permission signal OE is in the active state (H level), and when the corresponding bit data of the direction register 41 is “0” (L level). The output permission signal OE becomes inactive (L level).

  The IO cell 23_1 in FIG. 3 includes a timing adjustment circuit 50, inverters 61 to 65, a NAND circuit 66, an output buffer 70, and a protection circuit 80.

  The timing adjustment circuit 50 includes a first signal delay unit 51 that receives the output data signal DO, and a second signal delay unit 52 that receives the output permission signal OE. The first signal delay unit 51 includes a delay circuit 53A.

  FIG. 4 is a circuit diagram showing an example of the configuration of the delay circuit 53A of FIG. In the example shown in FIG. 4, the delay circuit 53A includes a plurality of (four in the case of FIG. 4) inverters 83A to 83D connected in cascade between the input node IN and the output node OUT. The number of cascaded inverters is determined according to the delay time.

  Referring to FIG. 3 again, second signal delay unit 52 includes delay circuits 53B and 53C and AND circuit 54. The output permission signal OE received from the IO port logic circuit 18 is input to the first input terminal of the AND circuit 54. The output permission signal OE is input to the second input terminal of the AND circuit 54 through the delay circuits 53B and 53C connected in cascade. The configuration of the delay circuits 53B and 53C is the same as that of the delay circuit 53A shown in FIG. The delay circuits 53 </ b> A to 53 </ b> C are also referred to as a delay circuit 53 when they are generically referred to or when an unspecified one is indicated. The operation of the first and second signal delay units 51 and 52 configured as described above will be described later with reference to FIG.

  The output data signal DOa output from the first signal delay unit 51 is input to the level shifter 67 via the inverter 61. Level shifter 67 converts the voltage level of output data signal DOa to external power supply voltage Vcc (3 to 5 V) higher than internal power supply voltage Vdd (for example, 1 to 1.5 V). Thereby, the voltage level of the output data signal DOa can be matched with the drive voltage of the circuit connected to the pad 24.

  Similarly, the output permission signal OEa delayed by the second signal delay unit 52 is input to the level shifter 68 via the inverter 61, and the voltage level is converted from Vdd to Vcc by the level shifter 68.

  The output data signal DOb whose level has been converted by the level shifter 67 is input to the output buffer 70 via the NAND circuit 66. The output permission signal OEb whose level has been converted by the level shifter 68 is input to the output buffer 70 through cascaded inverters 63 to 65. Connection node ND 2 of inverters 63 and 64 is connected to one input terminal of NAND circuit 66. NAND circuit 66 and inverters 63 to 65 are provided for shaping output data signal DOb and output permission signal OEb.

  Output buffer 70 includes an inverter 71, a NAND circuit 72, a NOR circuit 73, a P-channel MOS (Metal-Oxide Semiconductor) transistor 74, and an N-channel MOS transistor 75. MOS transistors 74 and 75 are connected in this order between a power supply node (external power supply voltage Vcc) and a ground node (ground voltage Vss). The output terminal of the NAND circuit 72 is connected to the gate electrode of the MOS transistor 74, and the output terminal of the NOR circuit 73 is connected to the gate electrode of the MOS transistor 75. The output data signal DOc is input to each first input terminal of the NAND circuit 72 and the NOR circuit 73. The output permission signal OEc is input to the second input terminal of the NAND circuit 72 and input to the second input terminal of the NOR circuit 73 via the inverter 71.

  According to the configuration of the output buffer 70 described above, when the output permission signal OEc is at the H level, the output data signal DOc is output to the connection node ND3 of the MOS transistors 74 and 75. When the output permission signal OE is at L level, both the MOS transistors 74 and 75 are turned off, so that the connection node ND3 is in a high impedance state.

  The protection circuit 80 is provided to protect the IO cell 23_1 from static electricity and includes diodes 81 and 82. Diode 81 is connected in the reverse bias direction between connection node ND3 and the power supply node (external power supply voltage Vcc). The diode 82 is connected in the reverse bias direction between the ground node (ground voltage Vss) and the connection node ND3.

[Operation of Timing Adjustment Circuit 50]
As described above, the layout of each functional block (module) of the microcomputer 100 shown in FIG. 1 is usually designed using an automatic wiring placement tool. Therefore, the IO port logic circuit 18 and the IO cell 23_1 are not necessarily arranged close to each other, and the wiring distance of the output data signal DO and the wiring distance of the output permission signal OE are not necessarily equal. Therefore, in the case of FIG. 3, there is a possibility that a deviation (skew) occurs in the timing between the output data signal DO and the output permission signal OE due to a wiring delay from the IO port logic circuit 18 to the IO cell 23_1. In an IO cell circuit in which the timing adjustment circuit 50 is not provided, if such a timing shift occurs, a hazard may occur in the external output signal PO output from the output buffer 70. Hereinafter, unlike the case of FIG. 3, the cause of the hazard included in the external output signal PO output from the output buffer 70 via the pad 24_1 will be described in the case where the timing adjustment circuit 50 is not provided.

  FIG. 5 is a timing chart for explaining a hazard that occurs when the output permission signal OE rises. FIG. 5 shows, in order from the top, the waveforms of the output data signal DOc and the output permission signal OEc input to the output buffer 70 and the waveform of the external output signal PO. The horizontal axis in FIG. 5 indicates time.

  3 and 5, the corresponding bit data of direction register 41 is always at L level. In this state, when the SCI output permission signal 37A output from the SCI 8 is switched from the L level to the H level, the output permission signal OE output from the selector 43A is also switched from the L level to the H level. Along with this, an output data signal DO corresponding to the SCI output data signal 37B is output from the selector 43B. Hereinafter, it is assumed that when the output permission signal OE is activated, the logic level of the output data signal DO to be output first is “1” (H level).

  At time t1, the output permission signal OEc input to the output buffer 70 is switched from the L level to the H level. However, in the case of FIG. 5, the output data signal DOc input to the output buffer 70 is switched from the L level to the H level that should be output at time t2, which is later than the time t1. As a result, an L-level external output signal PO different from the H-level signal that should be output from time t1 to time t2 is output from the output buffer 70. That is, the output permission signal OEc is activated from the inactive state (L level) before the output data signal DOc changes to the logic level (H level in FIG. 5) to be output while the output permission signal OEc is in the active state. When switching to the state (H level), a hazard is output from the output buffer. Note that the pad 24_1 is in the high impedance state (high-Z) before the time t1 when the output permission signal OEc is switched to the H level.

  FIG. 6 is a timing chart for explaining a hazard that occurs when the output permission signal OE falls. FIG. 6 shows, in order from the top, the waveforms of the output data signal DOc and the output permission signal OEc inputted to the output buffer 70 and the waveform of the external output signal PO. The horizontal axis in FIG. 6 indicates time.

  Referring to FIGS. 3 and 6, the corresponding bit data of direction register 41 is always at L level. In this state, when the SCI output permission signal 37A output from the SCI 8 is switched from the H level to the L level, the output permission signal OE output from the selector 43A is also switched from the H level to the L level. Hereinafter, it is assumed that the logic level of the output data signal DO to be output last before the output permission signal OE is deactivated is “1” (H level).

  At time t4, the output permission signal OEc input to the output buffer 70 is switched from the H level to the L level. However, in the case of FIG. 6, at time t3 earlier than time t4, the output data signal DOc input to the output buffer 70 switches from the H level to be output to the L level. As a result, an L-level external output signal PO different from the H-level signal that should be output from time t3 to time t4 is output from the output buffer 70. That is, after the output data signal DOc changes to a logic level different from the logic level (H level in FIG. 6) to be output while the output enable signal OEc is in the active state, the output enable signal OEc is in the active state (H level). A hazard is output from the output buffer 70 when switching from the inactive state to the inactive state (L level). After time t4 when the output permission signal OEc is switched to the L level, the pad 24_1 is in the high impedance state (high-Z).

  Each IO cell 23 of the first embodiment is provided with a timing adjustment circuit 50 in order to prevent the occurrence of a hazard due to the cause described with reference to FIGS. When the output data signal DOc and the output permission signal OEc are input to the output buffer 70, the timing adjustment circuit 50 outputs after the data signal DOc has changed to a logic level to be output while the output permission signal OEc is active. While the enable signal OEc is switched from the inactive state to the active state, and the data signal DOc holds the logic level to be output while the output enable signal OEc is in the active state, the output enable signal OEc changes from the active state. The timing of at least one of the output data signal DO and the output permission signal OE is adjusted so as to switch to the inactive state. Since signal delay is also caused by the level shifters 67 and 68 provided in each IO cell 23, the timing adjustment by the timing adjustment circuit 50 also takes into account the delay time by such a circuit in the IO cell.

  FIG. 3 shows first and second signal delay units 51 and 52 as an example of a specific circuit of the timing adjustment circuit 50. This circuit is effective in preventing the occurrence of a hazard when the output data signal DO and the output permission signal OE change almost simultaneously.

  FIG. 7 is a timing chart for explaining the operation of the first and second signal delay units 51 and 52. In FIG. 7, the output data signal DO input to the first signal delay unit 51, the output permission signal OE input to the second signal delay unit 52, and the first signal delay unit 51 are output in order from the top. The voltage waveforms of the output data signal DOa and the output permission signal OEa output from the second signal delay unit 52 are shown. The horizontal axis indicates time. In FIG. 7, each delay time of the delay circuits 53A to 53C in FIG. Since the delay time of the NAND circuit 54 is smaller than the delay time Td1, it is ignored.

  Referring to FIGS. 3 and 7, at time t1 in FIG. 7, both output data signal DO and output enable signal OE input to first and second signal delay units 51 and 52 are changed from L level to H level, respectively. Suppose you switch to a level. Then, at time t2 when the delay time Td1 by the delay circuit 53A has elapsed, the output data signal DOa output from the first signal delay unit 51 is switched from the L level to the H level. Further, at time t3 when the delay time Td1 × 2 due to the delay circuits 53B and 53C has elapsed, the signals input to the input terminals of the AND circuit 54 of the second signal delay unit 52 are both at the H level. The output permission signal OEa output from 54 is switched to the H level.

  At the next time t4, both the output data signal DO input to the first signal delay unit 51 and the output permission signal OE input to the second signal delay unit 52 are switched from the H level to the L level. At this time, the output permission signal OEa output from the AND circuit 54 is also switched to the L level. Thereafter, at time t5 when the delay time Td1 by the delay circuit 53A has elapsed, the output data signal DOa output from the first signal delay unit 51 is switched from H level to L level.

  As described above, the first signal delay unit 51 delays the input output data signal DO by the first delay time (Td1). The second signal delay unit 52 delays the rising timing (timing of switching from the inactive state to the active state) of the input output permission signal OE by the second delay time (Td1 × 2), and the falling edge Do not delay the timing. As a result, while the logic level of the output data signal OEa is at the H level (time t2 to t5), the output permission signal OEa is switched from the inactive state (L level) to the active state (H level) and activated (H Level) to an inactive state (L level).

  Although FIG. 7 shows a case where single output data “1” is output, a data string including a plurality of data may be output. In this case, after the data signal DO changes to the logic level of the first data output while the output enable signal OE is in the active state, the output enable signal OE is changed from the inactive state (L level) to the active state (H level). ), While the data signal DO holds the logic level of the last data output while the output permission signal OE is in the active state, the output permission signal OE is changed from the active state (H level) to the inactive state ( L level).

  The delay time Td1 is determined according to the timing difference between the output permission signal OE and the output data signal DO. At this time, it is preferable to set the same delay time Td1 for the IO cells 23 corresponding to the same functional block such as the SCI 8 and the timers 6 and 7.

  Note that the delay times of the delay circuits 53A to 53C are not necessarily the same, and the delay of the falling timing of the output permission signal OE is not necessarily zero. More generally, the delay time of the timing at which the output permission signal OE is switched from the inactive state to the active state is made longer than the delay time by the first signal delay unit 51 to switch from the active state to the inactive state. This delay time may be shorter than the delay time by the first signal delay unit 51.

[Example of layout of IO cell 23]
FIG. 8 is a plan view showing an example of the layout of the IO cells 23 and the pads 24 shown in FIG. FIG. 8 shows an example of the layout of the IO cells 23_1 and 23_2 and the pads 24_1 and 24_2. Since the layout of each IO cell 23 and each pad 24 is the same, hereinafter, the layout of the IO cell 23_1 and the pad 24_1 will be described as a representative.

  As shown in FIG. 8, regions R <b> 1 to R <b> 5 are provided on the semiconductor substrate 1 in order from the side close to the substrate end 1 </ b> A. A pad 24_1 is provided in the region R1. In the region R2, the protection circuit 80 and the output buffer 70 shown in FIG. 3 are provided. In the region R3, level shifters 67 and 68 in FIG. 3, a level shifter for the input data signal DI_1, an input buffer, and the like are provided. In the region R4, circuits such as the buffer inverters 61 and 62 in FIG. 3 are provided. The region R5 is provided with the timing adjustment circuit 50 shown in FIG.

  A circuit provided in the region R2 on the side close to the substrate end 1A (the −Y direction side) across the region R3 in which the level shifter is provided operates with the external power supply voltage Vcc, and the regions R4 and R5 on the opposite + Y direction side. The circuit provided in the circuit operates with the internal power supply voltage Vdd. By operating the timing adjustment circuit 50 with the internal power supply voltage Vdd, the circuit area required for the timing adjustment circuit 50 can be reduced as compared with operating with the external power supply voltage Vcc. Further, the timing adjustment is facilitated by operating with the internal power supply voltage Vdd whose voltage fluctuation is smaller than that of the external power supply voltage Vcc.

[Modification]
9 to 11 are circuit diagrams showing modifications of the delay circuit 53 of FIG.

  Referring to FIG. 9, delay circuit 55 includes a resistance element 84 provided between input node IN and output node OUT, and a capacitor provided between output node OUT and a ground node (ground voltage Vss). 85. The delay time of the delay circuit 55 is determined by the product of the resistance value of the resistance element 84 and the capacitance value of the capacitor 85.

  Referring to FIG. 10, delay circuit 56 includes gate circuits 86A and 86B such as inverters, a negative exclusive OR circuit 87, and a D flip-flop 88. The first input terminal of the negative exclusive OR circuit 87 is directly connected to the input node IN of the delay circuit 56, and the second input terminal is connected to the input node IN via the gate circuits 86A and 86B. The clock terminal CLK of the D flip-flop 88 is connected to the output terminal of the negative exclusive OR circuit 87, and the input terminal D is connected to the input node IN of the delay circuit 56. The output terminal Q of the D flip-flop 88 is connected to the output node OUT of the delay circuit 56.

  According to the circuit configuration described above, when the input signal of the input node IN changes, the input of the clock terminal CLK of the D flip-flop 88 becomes L level during the delay time corresponding to the gate circuits 86A and 86B. Accordingly, since the value before the input signal is changed is held by the D flip-flop 88 during this period, the output signal of the output node OUT can be delayed.

  Referring to FIG. 11, delay circuit 57 includes cascaded gate circuits 89 </ b> A to 89 </ b> D and a selection circuit 90. The input terminal of the first-stage gate circuit 89A is connected to the input node IN of the delay circuit 57, and the output terminal of the final-stage gate circuit 89D is connected to the selection circuit 90. Further, the connection nodes ND4 to ND6 of the gate circuits 89A to 89D are also connected to the selection circuit 90. The selection circuit outputs any one output signal of the gate circuits 89A to 89D to the output node OUT of the delay circuit 57 in accordance with the 2-bit selection signal SL. Thereby, the delay time of the delay circuit 57 can be adjusted.

  FIG. 12 is a circuit diagram showing a modification of the timing adjustment circuit 50 of FIG. In the modification of FIG. 12, a plurality of cascaded timing adjustment circuits 50A and 50B are provided in place of the timing adjustment circuit 50 of FIG. In the case of FIG. 12, two cases are illustrated. Therefore, in the case of FIG. 12, the delay time of the output permission signal OE and the output data signal DO can be doubled compared to the case where one timing adjustment circuit is provided. When designing the layout of an LSI, the timing adjustment circuit is registered as a macro cell, and the timing adjustment can be easily performed by adjusting the number of cascaded timing adjustment circuits.

<Embodiment 2>
Since the device sensitivity of the semiconductor circuit has been increased by the recent progress of the semiconductor process, the hazard once generated propagates without disappearing. For this reason, the generated hazard may be included in the output data signal DO and the output permission signal OE input to the IO cell 23 in some cases. In the second embodiment, means for preventing a hazard output to the outside of the semiconductor device in such a case will be described.

  FIG. 13 is a circuit diagram showing a configuration of a portion related to data output in IO cell 23A_1 used in the semiconductor device according to the second embodiment of the present invention. The IO cell 23A_1 in FIG. 13 is different from the IO cell 23_1 in FIG. 3 in that it further includes hazard removal circuits 91A and 91B provided in the previous stage of the timing adjustment circuit 50. The hazard removal circuit 91A removes a hazard that can be included in the output data signal DO, and the hazard removal circuit 91B removes a hazard that can be included in the output permission signal OE. 13 is the same as that of IO cell 23_1 in FIG. 3, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated. Since the hazard removal circuits 91A and 91B have the same configuration, the hazard removal circuit 91A will be described below as a representative.

  The hazard removal circuit 91A includes a delay circuit 92, an AND circuit 93, and NOR circuits 94-96. Here, as the delay circuit 92, any of the delay circuits described in FIGS. 4 and 9 to 11 may be used.

  As shown in FIG. 13, the output data signal DO output from the IO port logic circuit 18 is input to the first input terminals of the AND circuit 93 and the NOR circuit 94. The output data signal DO is input to the second input terminals of the AND circuit 93 and the NOR circuit 94 via the delay circuit 92. The output terminal of the AND circuit 93 is connected to the first input terminal of the NOR circuit 95, and the output terminal of the NOR circuit 94 is connected to the first input terminal of the NOR circuit 96. The NOR circuits 95 and 96 constitute an RS flip-flop 97 by connecting one output terminal to the other second input terminal. The output signal of the AND circuit 93 input to the RS flip-flop 97 is a set signal, and the output signal of the NOR circuit 94 is a reset signal.

  FIG. 14 is a timing chart for explaining the operation of the hazard removal circuit 91A of FIG. FIG. 14 shows, in order from the top, the input node ND10 of the hazard removal circuit 91A, the output node ND11 of the delay circuit 92, the output node ND12 of the AND circuit 93, the output node ND13 of the NOR circuit 94, and the output node ND14 of the hazard removal circuit 91A. Each voltage waveform is shown. The horizontal axis of FIG. 14 is time.

  Referring to FIGS. 13 and 14, output data signal DO input to input node ND10 switches from the L level to the H level at time t3, and switches from the H level to the L level at time t7. The output data signal DO includes a hazard with a pulse width Td2 at times t1 and t2.

  The voltage waveform at the output node ND11 of the delay circuit 92 is obtained by delaying the voltage waveform at the input node ND10 by the delay time Td3 of the delay circuit 92. That is, the voltage of the output node ND11 is switched from the L level to the H level at time t4, and is switched from the H level to the L level at time t8. Hazards are included at times t2 and t6. Here, the delay time Td3 of the delay circuit 92 needs to be set larger than the hazard pulse width Td2.

  The voltage waveform at the node ND12 is obtained by ANDing the voltage waveforms at the nodes ND10 and ND11. The voltage waveform at the node ND13 is obtained by performing a NOR operation on the voltage waveforms at the nodes ND10 and ND11. The voltage waveform at the node ND14 is an output waveform of the RS flip-flop when the voltage waveform at the node ND12 is a set signal and the voltage waveform at the node ND13 is a reset signal. As a result, the hazard is removed from the voltage waveform at the node ND14 as shown in FIG.

  As described above, the IO cell 23A according to the second embodiment is included in the external output signal PO output from the IO cell 23A to the outside of the semiconductor device by providing the hazard removal circuits 91A and 91B before the timing adjustment circuit 50. Obtaining hazards can be completely prevented. Therefore, the circuit configuration of the IO cell 23A of FIG. 13 can be suitably used when using the automatic placement and routing tool.

  The hazard removal circuits 91A and 91B are arranged in the same region R5 as the timing adjustment circuit 50 in the layout diagram shown in FIG. By operating the hazard removal circuits 91A and 91B with the internal power supply voltage Vdd, the circuit area can be reduced as compared with the case of operating with the external power supply voltage Vcc.

  It is not preferable to provide the hazard removal circuits 91A and 91B in the subsequent stage of the timing adjustment circuit 50. When the hazard is included in the output permission signal OE itself, when the hazard removal circuits 91A and 91B are provided in the subsequent stage of the timing adjustment circuit 50, the delay circuit 92 of the delay circuit 92 depends on the pulse width spread by the second signal delay unit 52. Determine the delay time.

  The embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  11-19 IO port logic circuit, 23, 23A IO cell (interface unit), 24 pads, 25 internal circuit, 30 internal bus, 50, 50A, 50B timing adjustment circuit, 51 first signal delay unit, 52 second Signal delay unit, 67, 68 level shifter, 70 output buffer, 91A, 91B hazard removal circuit, 100 microcomputer, DI input data signal, DO output data signal, OE output enable signal, PO external output signal.

Claims (6)

Internal circuitry,
Multiple pads,
A plurality of interface units each provided corresponding to the plurality of pads, each receiving a data signal and an output permission signal from the internal circuit;
Each of the plurality of interface units is
A timing adjustment circuit that adjusts the timing of at least one of the data signal and the output permission signal received from the internal circuit;
An output buffer that receives the data signal after timing adjustment by the timing adjustment circuit and the output permission signal, and outputs the data signal to the outside via a corresponding pad when the output permission signal is in an active state;
In each of the plurality of interface units, the timing adjustment circuit has a logic level that should be output while the output permission signal is in an active state when the data signal and the output permission signal are input to the output buffer. The output permission signal is switched from the inactive state to the active state after the data signal is changed, and the data signal holds the logic level to be output while the output permission signal is in the active state. A semiconductor device that adjusts timing of at least one of the data signal and the output permission signal so that the output permission signal is switched from an active state to an inactive state.   Each of the plurality of interface units includes a first hazard removal circuit and a second hazard removal circuit that are provided between the internal circuit and the timing adjustment circuit and respectively remove hazards included in the data signal and the output permission signal. The semiconductor device according to claim 1, further comprising: The timing adjustment circuit includes:
A first signal delay unit for delaying the data signal by a first delay time;
The timing at which the output permission signal is switched from the inactive state to the active state is delayed by a second delay time longer than the first delay time, and the timing at which the output permission signal is switched from the active state to the inactive state is not delayed, or The semiconductor device according to claim 1, further comprising: a second signal delay unit that delays a third delay time shorter than the first delay time. The timing adjustment circuit includes:
A plurality of first signal delay units connected in cascade to receive the data signal in the first stage;
Receiving the output permission signal in the first stage, and having the same number of cascaded second signal delay units as the plurality of first signal delay units,
Each of the plurality of first signal delay units delays an input signal by a first delay time,
Each of the plurality of second signal delay units delays the timing at which the input signal is switched from the inactive state to the active state by a second delay time longer than the first delay time, 2. The semiconductor device according to claim 1, wherein the timing of switching to the inactive state is not delayed or is delayed by a third delay time shorter than the first delay time. The plurality of interface units are divided into a plurality of groups,
4. The semiconductor device according to claim 3, wherein the first to third delay times that are equal to each other are set in each interface unit belonging to the same group. The drive voltage of the output buffer is higher than the drive voltage of the timing adjustment circuit,
Each of the plurality of interface units further includes first and second level shifters that are provided between the output buffer and the timing adjustment circuit and increase the signal levels of the data signal and the output permission signal, respectively. The semiconductor device according to claim 1.

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