JP2006338723A - Data transfer circuit and semiconductor memory apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To transfer correctly data in a data transfer circuit of a clock synchronous type using two kinds of clock signals having different phases. <P>SOLUTION: The apparatus is provided with a transfer gate 11 controlled by clock signals CK2/bCK2 and transferring input data IN, a latch circuit 13 latching data transferred from the transfer gate 11, a transfer gate 12 controlled by clock signals CK1/bCK1 of which the phases are different from the clock signals CK2/bCK2 and transferring data latched by the latch circuit 13, and a latch circuit 14 latching data transferred from the transfer gate 12 and outputting it. Phases of the clock signals CK2/bCK2, CK1/bCK1 are controlled so that data transfer periods in the transfer gate 11, 12 are not overlapped each other and off-periods of the transfer gate 11, 12 are overlapped. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a clock-synchronous data transfer circuit that transfers 1-bit data in synchronization with a clock signal and a semiconductor memory device using the data transfer circuit.

  Most of current semiconductor memory products are controlled in synchronization with a clock signal input from the outside. For example, when a write operation is performed, a command for requesting a “Write operation” is input in synchronization with a clock signal input from the outside. At this time, in the semiconductor chip, the write operation is started by using the clock signal to which the “Write operation” request is input as a trigger. Similarly, when a read operation is performed, the read operation is started using a clock signal to which a “Read operation” request is input as a trigger. Also, the operation of the shift register that converts parallel data to serial data (paraserial conversion) inside the semiconductor chip and converts serial data to parallel data (serial-parallel conversion) can also be applied to an externally input clock signal or It is controlled in synchronization with a clock signal generated inside the chip.

  FIG. 20 shows an example of a conventional data transfer circuit used for a shift register for converting parallel data into serial data or converting serial data into parallel data. This data transfer circuit is disclosed in, for example, FIG. 13 and FIG. 14 of Patent Document 1, and 1-bit data is synchronized with clock signals CK and bCK (bCK represents an inverted signal of CK). Forward.

  This data transfer circuit includes two transfer gates 61 and 62 whose on / off operations are controlled by clock signals CK and bCK, and two latch circuits 63 and 64 that latch the outputs of the two transfer gates 61 and 62. ing.

  The transfer gate 61 takes in the input data IN into the data transfer circuit, and the latch circuit 63 latches the data taken in by the transfer gate 61. The transfer gate 62 transfers the data latched by the latch circuit 63, and the latch circuit 64 latches the data transferred by the transfer gate 62 and outputs it to the next data transfer circuit.

  In the above conventional data transfer circuit, generally, input data IN is supplied to the data transfer circuit in synchronization with an external reference clock signal. The clock signals CK and bCK supplied to the data transfer circuit are generated by a control clock signal generation circuit inside the semiconductor chip in synchronization with an external reference clock signal.

  If the control clock signal generation circuit is arranged in the vicinity of the data transfer circuit and the clock signals CK and bCK have almost no wiring delay, no problem occurs. However, when the control clock signal generation circuit cannot be arranged in the vicinity of the data transfer circuit, the clock signals CK and bCK are caused by the resistance component existing in the wiring between the control clock signal generation circuit and the data transfer circuit. The wiring delay increases, the rise from the “L” level to the “H” level, or the fall from the “H” level to the “L” level is delayed, and the signal waveform becomes dull. As a result, there arises a problem that the data transfer circuit malfunctions.

  For example, the clock signal CK changes from “L” level to “H” level (bCK changes from “H” level to “L” level), the transfer gate 62 turns on, and the data latched by one latch circuit 63 Is transferred to the other latch circuit 64. At this time, it is assumed that the transfer gate 61 is still on because the rising and falling waveforms of the clock signals CK and bCK are dull. If the input data IN synchronized with the external reference clock signal is switched before the clock signal CK changes from “L” level to “H” level and bCK changes from “H” level to “L” level, The switched input data IN is transmitted to the latch circuit 64 via the transfer gate 61, the latch circuit 63, and the transfer gate 62, and is output as it is to the next stage. That is, data slipping occurs.

From the above, the conventional data transfer circuit has a restriction that the control clock signal generation circuit must always be arranged in the vicinity of the data transfer circuit in order to prevent data from slipping out due to the phase difference between the data and the clock signal. I have it.
JP 2000-67577 A

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a clock synchronous data transfer circuit and a semiconductor memory device capable of preventing malfunction due to the influence of delay of a clock signal. .

  The data transfer circuit of the present invention is controlled by a first clock signal, and includes a first transfer gate that transfers input data, a first latch circuit that latches data transferred by the first transfer gate, The second clock signal is controlled by a second clock signal having a phase different from that of the first clock signal, and is transferred by the second transfer gate for transferring the data latched by the first latch circuit, and the second transfer gate. And a second latch circuit for latching and outputting data, wherein the first and second clock signals have a data transfer period in the first and second transfer gates that do not overlap each other, and The phase is controlled so that the off periods of the first and second transfer gates overlap.

  A data input transfer circuit according to the present invention includes a data transfer circuit that transfers data, a data input control circuit that unambiguously sets the level of input data based on a reset signal while supplying the input data to the data transfer circuit, And the data transfer circuit is controlled by a first clock signal to transfer a first transfer gate for transferring input data, and a first latch circuit for latching the data transferred by the first transfer gate. And a second transfer gate for transferring data latched by the first latch circuit, controlled by a second clock signal having a phase different from that of the first clock signal, and the second transfer gate. A second latch circuit that latches and outputs the transferred data, and the first and second clock signals are supplied to the first and second transfer gates. Kicking data transfer period do not overlap each other and said first and second phase as the OFF period of the transfer gate overlaps is characterized in that it is controlled.

  A semiconductor memory device according to the present invention includes a plurality of memory cell array blocks each having a plurality of memory cell arrays each composed of a plurality of memory cells, and word lines in the memory cell arrays. A row decoder and column decoder for selectively driving lines and column select lines, and a redundancy redundancy block for outputting redundancy replacement data for replacing the word lines and column select lines with spare word lines and spare column select lines in parallel And a column redundancy fuse block, a clock signal generation circuit for generating first and second clock signals, and redundancy replacement data output in parallel from both fuse blocks as the first and second clock signals. Synchronize, A row redundancy parallel serial conversion circuit and a column redundancy parallel serial conversion circuit for converting to real data, and redundancy replacement data serially output from both parallel serial conversion circuits are synchronized with the first and second clock signals. And a row redundancy serial / parallel conversion circuit and a column redundancy serial / parallel conversion circuit for converting into parallel data, and between the two parallel serial conversion circuits and the two serial parallel conversion circuits, and output based on a reset signal. Based on the output data from the row redundancy data input control circuit and the column redundancy data input control circuit and the serial / parallel conversion circuit for uniquely setting the data level, the spare word line and the spare column selection are selected. A row replacement control circuit and a column replacement control circuit for controlling replacement to a line, wherein both the parallel-serial conversion circuit and both the serial-parallel conversion circuits are connected in series to transfer 1-bit data. Each of the plurality of data transfer circuits is controlled by the first clock signal, and each of the plurality of data transfer circuits includes a first transfer gate for transferring input data, and the first transfer gate. A first latch circuit that latches the transferred data and a second clock signal that is controlled by a second clock signal having a phase different from that of the first clock signal, and that transfers the data latched by the first latch circuit. And a second latch circuit for latching and outputting the data transferred by the second transfer gate, the first and second The phase of the clock signal is controlled so that the data transfer periods in the first and second transfer gates do not overlap each other and the off periods of the first and second transfer gates overlap. To do.

  According to the present invention, it is possible to provide a clock-synchronous data transfer circuit and a semiconductor memory device that can prevent malfunction due to the influence of delay of a clock signal.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a clock synchronous data transfer circuit according to a first embodiment of the present invention, together with a control clock signal generation circuit that generates a clock signal used for controlling the operation of the data transfer circuit. . The data transfer circuit 10 shown in FIG. 1 transfers 1-bit data in synchronization with a clock signal, and includes two transfer gates 11 and 12 and latch circuits 13 and 14, respectively.

  The transfer gate 11 is a CMOS-type transfer gate composed of P-channel and N-channel MOS transistors whose source and drain are connected in parallel, and is turned on by clock signals CK2 and bCK2 (bCK2 represents a reverse phase signal of CK2). / Off operation is controlled.

  A latch circuit 13 is connected to the output node A of the transfer gate 11. The latch circuit 13 includes a first inverter circuit (inverting circuit) 15 whose input terminal is connected to the output node A of the transfer gate 11 and a first inverter whose input terminal is connected to the output terminal of the first inverter circuit 15. And a second inverter circuit 16 having an output terminal connected to the input terminal of the circuit 15.

  A transfer gate 12 is connected to the output node B of the latch circuit 13. Similarly to one transfer gate 11, the transfer gate 12 is a CMOS type transfer gate composed of P-channel and N-channel MOS transistors in which the source and drain are connected in parallel, and is different from the clock signals CK2 and bCK2. ON / OFF operations are controlled by clock signals CK1 and bCK1 (bCK1 represents a reverse phase signal of CK1).

  A latch circuit 14 is connected to the output node C of the transfer gate 12. The latch circuit 14 includes a first inverter circuit 17 having an input terminal connected to the output node C of the transfer gate 12, and an input terminal connected to the output terminal of the first inverter circuit 17. And a second inverter circuit 18 having an output terminal connected to the terminal.

  The control clock signal generation circuit 20 receives, for example, a reference clock signal CLK supplied from the outside of the semiconductor chip. From the reference clock signal CLK, two-phase clock signals CK1 and CK2 as shown in FIG. Signals bCK1 and bCK2 are generated.

  When the clock signal CK1 is at “H” level and bCK1 is at “L” level, the transfer gate 12 is turned on and the latch data of the latch circuit 13 is transferred to the latch circuit. At this time, since the clock signal CK2 is at "L" level and bCK2 is at "H" level, the transfer gate 11 is turned off.

  On the contrary, when the clock signal CK2 is at “H” level and bCK2 is at “L” level, the transfer gate 11 is turned on, and the input data IN is transferred to the latch circuit 13. At this time, since the clock signal CK1 is at "L" level and bCK1 is at "H" level, the transfer gate 12 is turned off.

  That is, the phases of the clock signals CK1 and CK2 and the opposite phase signals bCK1 and bCK2 are such that the data transfer periods in the two transfer gates 11 and 12 do not overlap each other and the off periods of the transfer gates 11 and 12 overlap. It is controlled.

  FIG. 3 shows an example of a specific circuit configuration of the control clock signal generation circuit 20 shown in FIG. The two-phase clock signal generation circuit 21 generates two-phase clock signals CLK1 and CLK2 having different phases from the reference clock signal CLK.

  Two inverter circuits 22 connected in series generate a clock signal CK1 from one of the two-phase clock signals CLK1.

  The three inverter circuits 23 connected in series generate the clock signal bCK1 from the clock signal CLK1.

  Two inverter circuits 24 connected in series generate a clock signal CK2 from the other clock signal CLK2 of the two-phase clock signals.

  Three inverter circuits 25 connected in series generate a clock signal bCK2 from the clock signal CLK2.

  When a plurality of data transfer circuits 10 configured as shown in FIG. 1 are integrated on a semiconductor chip, the plurality of data transfer circuits 10 are arranged in the vicinity of the control clock signal generation circuit 20 and others are not. Occurs.

  FIG. 4A shows a circuit connection state when the data transfer circuit 10 is arranged in the vicinity of the control clock signal generation circuit 20. Since the data transfer circuit 10 is disposed in the vicinity of the control clock signal generation circuit 20, the clock signals CK1, bCK1, and CK2, bCK2 hardly cause a signal delay due to the wiring path. In this case, as shown in the timing chart of FIG. 4B, the rising and falling waveforms of the clock signals CK1, bCK1, and CK2 and bCK2 supplied to the data transfer circuit 10 are not dull and are almost the same as the reference clock signal CLK. Have rising and falling characteristics. The timing tD at which the input data IN changes is later than the timing tC at which the clock signal CK1 changes.

  Next, the operation of the circuit of FIG.

  In a period in which the reference clock signal CLK is at the “L” level, the clock signal CK1 is at the “L” level, the bCK1 is at the “H” level, the clock signal CK2 is at the “H” level, and the bCK2 is at the “L” level. Since the gate 11 is on and the transfer gate 12 is off, the input data IN is transferred to the latch circuit 13 via the transfer gate 11.

  From this state, the reference clock signal CLK is “L” level, the clock signal CK1 is “L” level, the bCK1 is “H” level, the clock signal CK2 is “L” level, and the bCK2 is “H” level. In the period, both the transfer gates 11 and 12 are turned off, so that the data transferred to the latch circuit 13 is latched by the latch circuit 13.

  From this state, next, the reference clock signal CLK is “H” level, the clock signal CK1 is “H” level, the bCK1 is “L” level, the clock signal CK2 is “L” level, and the bCK2 is “H”. During the level period, the transfer gate 11 is in the off state and the transfer gate 12 is in the on state, so that the data latched by the latch circuit 13 is transferred to the latch circuit 14 via the transfer gate 12.

  From this state, the reference clock signal CLK is “H” level, the clock signal CK1 is “L” level, bCK1 is “H” level, the clock signal CK2 is “L” level, and bCK2 is “H” level. In the period, both the transfer gates 11 and 12 are turned off, so that the data transferred to the latch circuit 14 is latched by the latch circuit 14.

  That is, in the data transfer circuit 10 in FIG. 1, after the transfer gate 11 or 12 is turned on, there is always a period in which both the transfer gates 11 and 12 are in the off state, and two transfers are performed with the off period interposed therebetween. Data is transferred in synchronism with the clock signal while the gates alternately repeat on / off operations.

  Next, the operation of the circuit shown in FIG. 4A will be described in detail with reference to the timing chart of FIG.

  In the period from time T0 to time T1, the clock signal CK1 is at the “L” level, the bCK1 is at the “H” level, the clock signal CK2 is at the “H” level, and the bCK2 is at the “L” level. Reference numeral 12 denotes an off state. Accordingly, the “L” level of the input data IN is transferred to the latch circuit 13.

  In the period from time T1 to T2, since the clock signal CK1 is “L” level, bCK1 is “H” level, the clock signal CK2 is “L” level, and bCK2 is “H” level, the transfer gate 12 remains off. On the other hand, the transfer gate 11 changes from the on state to the off state. In other words, during the period from time T1 to time T2, “L” level data transferred to the latch circuit 13 is latched by the latch circuit 13.

  At time T2, when the input data IN changes from “L” level to “H” level in synchronization with the reference clock signal CLK, the clock signal CK1 becomes “H” level, and bCK1 becomes “L” level, the transfer gate 12 However, since the clock signal CK2 remains at “L” level and bCK2 remains at “H” level, the transfer gate 11 remains off. Further, after the time T2, the input data IN transits from the “L” level to the “H” level, but the transfer gate 11 that functions to take data into the data transfer circuit 10 is in the OFF state. The transition of the input data IN is not transmitted to the data transfer circuit 10 regardless of the phase difference between the clock signal CK1 and the difference between the timings tC and tD. Further, when the transfer gate 12 changes from the off state to the on state, the “L” level data latched by the latch circuit 13 during the period of time T1 to T2 is transferred to the latch circuit 14 and is output as the output data OUT. Is output.

  When the clock signal CK1 becomes “L” level and bCK1 becomes “H” level at time T3, the transfer gate 12 changes from the on state to the off state, but the clock signal CK2 becomes “L” level and bCK2 becomes “H” level. As a result, the transfer gate 11 remains off. When the transfer gate 12 is turned off, the “L” level data output as the output data OUT from the data transfer circuit 10 at time T2 is latched by the latch circuit 14. Accordingly, during the period from time T2 to T4, “L” level data is output as the output data OUT of the data transfer circuit 10.

  When the clock signal CK2 becomes “H” level and bCK2 becomes “L” level at time T4, the transfer gate 11 changes from the off state to the on state. However, since the clock signal CK1 remains at “L” level and bCK1 remains at “H” level, the transfer gate 12 remains off. When the transfer gate 11 is turned on, “H” level data of the input data IN is transferred to the latch circuit 13. That is, node A in FIG. 1 changes from “L” level to “H” level, and node B changes from “H” level to “L” level. At this time, since the transfer gate 12 is in the OFF state, the “H” level data transferred to the latch circuit 13 is not transferred to the latch circuit 14. Accordingly, the output data OUT of the data transfer circuit 10 remains at the “L” level as in the previous period.

  When the clock signal CK2 becomes “L” level and bCK2 becomes “H” level at time T5, the transfer gate 11 changes from the on state to the off state, but the clock signal CK1 is “L” level and bCK1 is “H” level. As a result, the transfer gate 12 remains off. When the transfer gate 11 is turned off, the “H” level data transmitted to the latch circuit 13 is latched by the latch circuit 13. Therefore, the output data OUT of the data transfer circuit 10 remains at the “L” level in the period from the time T4 to the time T6 as in the previous period from the time T2 to the time T4.

  At time T6, when the input data IN changes from the “H” level to the “L” level, the clock signal CK1 becomes the “H” level, and the bCK1 becomes the “L” level, the transfer gate 12 changes from the off state to the on state. However, since the clock signal CK2 remains at “L” level and bCK2 remains at “H” level, the transfer gate 11 remains off. After the time T6, the input data IN changes from the “H” level to the “L” level, but the transfer gate 11 that functions to take in the data into the data transfer circuit 10 is in the OFF state. Regardless of the phase difference of the signal CK1 (difference between timings tC and tD), the transition of the input data IN is not transmitted to the data transfer circuit 10. In addition, when the transfer gate 12 is turned from the off state to the on state, the “H” level data latched by the latch circuit 13 during the period of time T5 to T6 is transferred to the latch circuit 14, and the node C becomes “ The H level is changed to the “L” level, the node D is changed from the “L” level to the “H” level, and “H” level data is output as the output data OUT.

  When the clock signal CK1 becomes “L” level and bCK1 becomes “H” level at time T7, the transfer gate 12 changes from the on state to the off state, but the clock signal CK2 becomes “L” level and bCK2 becomes “H” level. As a result, the transfer gate 11 remains off. When the transfer gate 12 is turned off, the “H” level data output as the output data OUT from the data transfer circuit 10 at time T6 is latched by the latch circuit 14. That is, node C is at “L” level and node D is at “H” level. Therefore, the output data OUT from the data transfer circuit 10 is at the “H” level during the period of time T6 to T8.

  When the clock signal CK2 becomes “H” level and bCK2 becomes “L” level at time T8, the transfer gate 11 changes from the off state to the on state, but the clock signal CK1 is “L” level and the bCK1 is “H” level. As a result, the transfer gate 12 remains off. When the transfer gate 11 changes from the OFF state to the ON state, the “L” level data of the input data IN is transmitted to the latch circuit 13 in the data transfer circuit 10, and the node A changes from the “H” level to the “L” level. The node B transits from the “L” level to the “H” level, and the “L” level data of the input data IN is not transmitted to the latch circuit 14 because the transfer gate 12 is in the off state. Accordingly, the output data OUT remains at the “H” level as in the previous period.

  When the clock signal CK2 becomes “L” level and bCK2 becomes “H” level at time T9, the transfer gate 11 changes from the ON state to the OFF state, but the clock signal CK1 becomes “L” level and the bCK1 becomes “H” level. As a result, the transfer gate 12 remains off. When the transfer gate 11 is turned off, the “L” level data transmitted to the latch circuit 13 in the data transfer circuit 10 is latched by the latch circuit 13, the node A becomes “L” level, and the node B becomes It is held at “H” level. Therefore, the output data OUT from the data transfer circuit 10 remains at the “H” level in the period from the time T8 to T10 as in the previous period from the time T6 to T8.

  When the clock signal CK1 becomes “H” level and bCK1 becomes “L” level at time T10, the transfer gate 12 changes from the OFF state to the ON state, but the clock signal CK2 becomes “L” level and bCK2 becomes “H” level. As a result, the transfer gate 11 remains off. When the transfer gate 12 is turned from the off state to the on state, the “L” level data latched by the latch circuit 13 during the period from time T9 to T10 is transmitted to the latch circuit 14, and the node C changes from the “L” level. The node D transitions from the “H” level to the “L” level to the “H” level. Therefore, the output data OUT changes from the “H” level to the “L” level.

  When the clock signal CK1 becomes “L” level and bCK1 becomes “H” level at time T11, the transfer gate 12 changes from the ON state to the OFF state, but the clock signal CK2 becomes “L” level and bCK2 becomes “H” level. As a result, the transfer gate 11 remains off. Then, when the transfer gate 12 is changed from the on state to the off state, the “L” level data output as the output data OUT from the data transfer circuit 10 at time T10 is latched by the latch circuit 14, and the node C is The node D is held at the “H” level and the “L” level. Accordingly, the “L” level is output as the output data OUT during the period of time T10 to T12.

  Regarding the period after time T12, since the state of the internal node in the data transfer circuit 10 is the same as the period from time T10 to T12, the data transfer circuit 10 continues to output "L" level data.

  That is, as shown in FIG. 4A, when the data transfer circuit 10 is arranged in the vicinity of the control clock signal generation circuit 20, the data transfer circuit 10 normally transfers data.

  FIG. 6A shows a circuit connection state when the data transfer circuit 10 cannot be arranged in the vicinity of the control clock signal generation circuit 20. Since the data transfer circuit 10 is not disposed in the vicinity of the control clock signal generation circuit 20, the clock signals CK1, bCK1, and CK2, bCK2 are delayed by a resistance component existing in the wiring path. In this case, as shown in the timing diagram of FIG. 6B, the clock signals CK1, bCK1, and CK2 and bCK2 supplied to the data transfer circuit 10 have dull rising and falling waveforms and are gentler than the reference clock signal CLK. It has a rising and falling characteristic that changes to. Further, the timing tD when the input data IN changes precedes the timing tC when the clock signal CK1 changes.

  FIG. 7 is a timing chart showing an example of the operation of the circuit shown in FIG. The operations in the period before time T2 and in the period after T6 are the same as those in the case of the circuit in FIG. 4A described with reference to FIG. The operation during the period will be described below.

  At time T2, the input data IN transitions from the “L” level to the “H” level. Unlike the case of FIG. 5, the data transition is earlier than the switching of the clock signals CK1 and bCK1. 10 is transmitted. However, since the transfer gate 11 that functions to take the input data IN transmitted to the data transfer circuit 10 into the data transfer circuit 10 is in an off state, the data transition is transmitted to the data transfer circuit 10 as in the conventional case. There is nothing.

  At time T6, the input data IN changes from the “H” level to the “L” level, and the data transition is transmitted to the data transfer circuit 10 earlier than the switching of the clock signals CK1 and bCK1. Since 11 is in the OFF state, it is not transmitted to the data transfer circuit 10.

  In other words, even if a delay occurs in the clock signal and a phase difference occurs between the input data and the clock signal, it is possible to prevent a malfunction that the data slips through, and the input data is transferred correctly in synchronization with the reference clock signal. be able to. As a result, the restriction that the control clock signal generation circuit must always be arranged in the vicinity of the data transfer circuit can be solved.

  In the conventional data transfer circuit, as described above, when data is switched before the clock signal, data slips out in the data transfer circuit, and the input data is correctly transferred in synchronization with the reference clock signal. Therefore, there is a problem that the control clock signal generation circuit must always be arranged near the data transfer circuit.

  In addition, a delay circuit block is provided between the data transfer circuits for delaying the data input to the data transfer circuit relative to the clock signal if the circuit configuration inevitably causes a wiring delay in the clock signal. This has resulted in an increase in layout area.

  However, since the data transfer circuit according to the present embodiment can always correctly transfer input data in synchronization with the reference clock signal regardless of the phase difference between the clock signal and the data, the location of the control clock signal generation circuit can be reduced. You can decide freely.

  Further, in the data transfer circuit according to the present embodiment, even if a wiring delay occurs in the clock signal due to the circuit configuration, the data input to the data transfer circuit is transferred between the data transfer circuits. There is no need to provide a delay circuit block for delaying. For this reason, an effect of reducing the layout area, that is, reducing the chip size can be obtained.

  FIG. 8 shows a configuration of a data transfer circuit according to the second embodiment of the present invention.

  The data transfer circuit 10 according to the second embodiment is different from the data transfer circuit according to the first embodiment shown in FIG. 1 in that instead of the second inverter circuits 16 and 18 constituting the latch circuits 13 and 14. The clocked inverter circuits 16A and 18A are provided.

  The clocked inverter circuit 16A in the latch circuit 13 is controlled by the clock signals CK2 and bCK2, and the clocked inverter circuit 18A in the latch circuit 14 is controlled by the clock signals CK1 and bCK1.

  When the clock signal CK1 becomes “H” level and bCK1 becomes “L” level and the transfer gate 12 is turned on, the clocked inverter circuit 18A in the latch circuit 14 is turned off. Contrary to the above case, when the clock signal CK1 becomes “L” level, bCK1 becomes “H” level, and the transfer gate 12 is turned off, the clocked inverter circuit 18A in the latch circuit 14 is turned on. Thus, the latch circuit 14 latches the data.

  Similarly, when the clock signal CK2 becomes “H” level and bCK2 becomes “L” level and the transfer gate 11 is turned on, the clocked inverter circuit 16A in the latch circuit 13 is turned off. Contrary to the above case, when the clock signal CK2 becomes “L” level, bCK2 becomes “H” level, and the transfer gate 11 is turned off, the clocked inverter circuit 16A in the latch circuit 13 is turned on. Thus, the data is latched by the latch circuit 13.

  As in this embodiment, when the transfer gates 11 and 12 are turned on and data is transferred to the latch circuits 13 and 14, the clocked inverter circuits 16A and 18A constituting the latch circuits 13 and 14 are turned off. Thus, data can be transferred to the latch circuit more easily than in the case where the latch circuit is configured by two inverter circuits as in the first embodiment.

  As shown in FIG. 1, when a latch circuit is composed of two inverter circuits, the capacity of the inverter circuit for latching (inverter circuits 16 and 18 in FIG. 1) is set to the inverter circuit for transfer (inverter in FIG. 1). It must be weaker than the circuits 15, 17). For this reason, the layout area of the latch circuit portion increases.

  However, as in this embodiment, by using a latched element as a clocked inverter circuit, a data transfer circuit can be configured without increasing the layout area of the latch circuit portion.

  Also in this embodiment, as in the first embodiment, the input data can always be correctly transferred in synchronization with the reference clock signal regardless of the phase difference between the clock signal and the data. The circuit location can be determined freely.

  Further, as in the first embodiment, even if a wiring delay occurs in the clock signal due to the circuit configuration, data input to the data transfer circuit is transferred between the data transfer circuits by the clock signal. There is no need to provide a delay circuit block for delaying. As a result, an effect of reducing the layout area, that is, reducing the chip size can be obtained.

  FIG. 9 shows a configuration of a data transfer circuit according to the third embodiment of the present invention.

  The data transfer circuit 10 according to the third embodiment is different from the data transfer circuit according to the second embodiment shown in FIG. 8 in that P channels and N channels are used as transfer gates for transferring data to the latch circuits 13 and 14. Instead of the CMOS type transfer gates 11 and 12 configured using MOS transistors, transfer gates 11A and 12A configured using a clocked inverter circuit are provided.

  The transfer gate 11A is controlled by clock signals CK2 and bCK2, and the transfer gate 12A is controlled by clock signals CK1 and bCK1.

  As in the present embodiment, as a transfer gate for transferring data to the latch circuits 13 and 14, a transfer gate formed by a clocked inverter circuit is used in place of a simple CMOS type transfer gate so that the transfer gate is turned on. Unlike the case of the first and second embodiments, the capacity of the latch circuits 13 and 14 becomes invisible via the transfer gate, so that the data is faster than the case of the first and second embodiments. Can be transferred.

  Also in this embodiment, as in the first and second embodiments, the input data can always be correctly transferred in synchronization with the reference clock signal regardless of the phase difference between the clock signal and the data. The location of the clock signal generation circuit can be freely determined.

  Further, as in the first and second embodiments, even when a wiring delay occurs in the transfer control clock signal due to the circuit configuration, the data is input to the data transfer circuit between the data transfer circuits. Since there is no need to provide a delay circuit block for delaying data from the clock signal, an effect of reducing the layout area, that is, reducing the chip size can be obtained.

  In the first embodiment, transfer gates 11A and 12A configured using a clocked inverter circuit may be provided instead of the CMOS type transfer gates 11 and 12, respectively.

  FIG. 10 shows a data input transfer circuit showing a data transfer circuit according to the fourth embodiment of the present invention together with a control clock signal generation circuit for generating a clock signal used for controlling the operation of the data transfer circuit. It is. The data transfer circuit 10 transfers 1-bit data in synchronization with clock signals CK1, bCK1, CK2, and bCK2 having different phases. The data transfer circuit 10 may be configured as shown in FIG. 1, FIG. 8, and FIG.

  The control clock signal generation circuit 20A has a function of generating clock signals CK1, bCK1, and CK2, bCK2 in synchronization with a reference clock signal CLK supplied from the outside, and the clock signals CK1, bCK1, and the like based on the reset signal bRST. It has a function to uniquely set the levels of CK2 and bCK2.

  The data (Data) input control circuit 30 has a function of supplying the input data (Data) to the data transfer circuit 10 as input data IN and uniquely setting the level of the input data IN based on the reset signal bRST.

  FIG. 11 shows an example of a specific circuit configuration of the data input control circuit 30 in FIG. The input data (Data) and the reset signal bRST are supplied to the NAND gate 31. The output of the NAND gate 31 is supplied to the inverter circuit 32, and the data D_IN output from the inverter circuit 32 is supplied to the data transfer circuit 10 as input data IN.

  FIG. 12 shows an example of a specific circuit configuration of the control clock signal generation circuit 20A in FIG. The two-phase clock signal generation circuit 21 generates two-phase clock signals CLK1 and CLK2 having different phases from the reference clock signal CLK in the same manner as shown in FIG.

  The inverter circuits 33 to 36 and the NAND gate 37 generate clock signals CK1 and bCK1 from one of the two-phase clock signals CLK1 and the reset signal bRST.

  The inverter circuits 38 to 41 and the NAND gate 42 generate clock signals CK2 and bCK2 from the other clock signal CLK2 of the two-phase clock signals and the reset signal bRST.

  As shown in the timing diagram of FIG. 13, the reset signal bRST changes from the “L” level to the “H” level state when the power is turned on and the power supply potential VCC in the semiconductor chip rises to a desired potential. When the power supply potential inside the chip rises, that is, when bRST is in the “L” level state, the output D_IN (IN) from the data input control circuit 30 is in the “L” level state. When bRST is in the “L” level state, the clock signal CK1 generated by the control clock signal generation circuit 20A is in the “H” level, bCK1 is in the “L” level state, and the clock signal CK2 is in the “H” level. , BK2 are in the “L” level state.

  Next, the operation of the data input transfer circuit of this embodiment will be described with reference to FIG.

  It is assumed that the power is turned on at time T0, the power supply voltage VCC rises sequentially from the ground potential (VSS), and the power supply potential inside the chip reaches a desired potential at time T1.

  The chip ready signal CHRDY transitions from the “L” level to the “H” level when the power supply potential inside the chip reaches a desired potential. Since the reset signal bRST is generated in response to the chip ready signal CHRDY, it transitions from the “L” level to the “H” level at the time T1 similarly to the CHRDY.

  In the initialization period from time T0 to time T1, the reset signal bRST is in the “L” level state, so that the output data D_IN (IN) from the data input control circuit 30 is in the “L” level state, and the control clock The clock signal CK1, which is an output from the signal generation circuit 20A, is at "H" level, bCK1 is at "L" level, the clock signal CK2 is at "H" level, and bCK2 is at "L" level.

  Since the clock signal CK1 is at "H" level, bCK1 is at "L" level, the clock signal CK2 is at "H" level, and bCK2 is at "L" level, the transfer gates 11 and 12 in the data transfer circuit 10 are both turned on. It has become. Accordingly, the “L” level data of the data IN that is output from the data input control circuit 30 is transmitted into the data transfer circuit 10, and “L” level data is output as the output data OUT of the data transfer circuit 10. At this time, the output node B of the latch circuit 13 is at “H” level, the output node C of the transfer gate 12 is at “H” level, and the output data OUT of the data transfer circuit 10 is at “L” level.

  When the reset signal bRST transitions from “L” level to “H” level at time T1, the clock signal CK1 is “L” level, the bCK1 is “H” level, the clock signal CK2 is “L” level, and the bCK2 is “H”. Therefore, both of the transfer gates 11 and 12 in the data transfer circuit 10 are turned off, and the previous state is latched by the latch circuits 13 and 14. Accordingly, the output data OUT from the data transfer circuit 10 maintains the “L” level as in the period from time T0 to time T1.

  Here, what is important is that both the transfer gates 11 and 12 in the data transfer circuit 10 are turned on during the period until the power supply potential inside the chip is determined after the power is turned on, and the data input node of the data transfer circuit 10 is turned on. The data transfer circuit 10 can be initialized to arbitrary data by inputting arbitrary data from.

  In order to initialize the conventional data transfer circuit shown in FIG. 20, a reset transistor for setting the input node of the latch circuit (reference numeral 64 in FIG. 20) in the subsequent stage to the “H” level is used as the data transfer circuit. Therefore, it is necessary to take measures such as providing it inside, and the layout area increases.

  On the other hand, in the data input transfer circuit of this embodiment, the data transfer circuit can be initialized without providing a reset transistor. Accordingly, there is no increase in layout area, which is particularly effective in a circuit in which a plurality of data transfer circuits are provided and connected in multiple stages, such as a shift register.

  FIG. 14 is a block diagram showing a configuration of a semiconductor memory device according to the fifth embodiment of the present invention. The semiconductor memory device according to the present embodiment is configured using the data transfer circuit according to the first to third embodiments.

  At present, with the progress of high integration due to the miniaturization of the semiconductor manufacturing process, a redundant memory cell array is provided in addition to the regular memory cell array from the viewpoint of improving the yield of the semiconductor memory device. For some reason, the word line (WL) In addition, when a column selection line (CSL) fails, the importance of a redundancy circuit replaced with a spare word line or a spare column selection line is increasing. The redundancy circuit normally compares the fuse block that selects the failed row or column address by fuse blow, the redundancy replacement data from the fuse block and the external input address, and replaces the spare word line / spare column selection line. And a replacement control circuit for controlling. The redundancy circuit having such a configuration is a row decoder for selecting and driving a normal word line and a spare word line in order to increase the access speed as a redundancy circuit for a row and a column. And the normal column selection line and the spare column selection line are preferably arranged in the vicinity of the column decoder for selecting and driving.

  However, the redundancy circuit may not be arranged in the vicinity of the row decoder and the column decoder due to restrictions on the chip area of the semiconductor chip. In such a case, the access speed cannot be increased.

  Therefore, the semiconductor memory device according to the present embodiment converts the redundancy replacement data output from the redundancy fuse block into serial data by parallel serial data conversion, synchronizes this serial data with the clock signal, and the vicinity of the row decoder and the column decoder. By sequentially transferring the data to the replacement control circuit arranged in FIG. 1, the arrangement location of the redundancy fuse block can be freely determined without sacrificing the access speed.

  As shown in FIG. 14, the semiconductor memory device of this embodiment is composed of a plurality of memory cells selected by a matrix address signal, a memory cell array 100 including a normal cell array 101, redundant cell arrays 102 and 103, and a memory cell array. 100, a row decoder 104 and a column decoder 105 for selecting a word line and a column selection line, respectively, and a row fuse block 106 for outputting redundancy replacement data for the word line and the column selection line, respectively. And column fuse block 107, row replacement control circuit 108 and column replacement control circuit for controlling spare replacement of word lines and column selection lines based on redundancy replacement data of word lines and column selection lines, respectively. 109, a reference clock signal generation circuit 110 that generates a reference clock signal CLK, and two-phase clock signals CK1, bCK1, and CK2, bCK2, and clock signals CK3, bCK3 that are different in phase from the reference clock signal CLK and the reset signal bRST. The control clock signal generation circuit 111 for generating the signal and the redundancy replacement data of the word line output in parallel from the row fuse block 106 are serially converted in synchronization with the clock signals CK1, bCK1, CK2, bCK2, CK3, bCK3. A data input control circuit 113 having a function similar to that of the data input control circuit 30 in FIG. 10 is inputted with the output FR_OUT and the reset signal bRST from the parallel-serial (parallel serial) conversion circuit 112 and the row parallel-serial conversion circuit 112. The serial output FR_IN from the data input control circuit 113 is parallel-converted in synchronization with the clock signals CK1, bCK1, CK2, and bCK2 and supplied to the row replacement control circuit 108. A column parallel-serial conversion circuit 115 that serially converts the redundancy replacement data of the column selection line output from the column fuse block 107 in synchronization with the clock signals CK1, bCK1, CK2, bCK2, CK3, and bCK3; , The data input control circuit 116 having the same function as the data input control circuit 30 in FIG. 10 and the serial input from the data input control circuit 116 are inputted with the output FC_OUT and the reset signal bRST from the column parallel-serial conversion circuit 115. The output FC_IN, and a clock signal CK1, BCK1 and CK2, column supplies the parallel conversion is synchronized to the replacement control circuit 109 for column bCK2 serial-parallel (serial-parallel) conversion circuit 117.

  According to the semiconductor memory device of the present embodiment, the redundancy replacement data output from the redundancy fuse block is converted into serial data by parallel serial data conversion, and the serial data is synchronized with the clock signal to be near the row decoder and the column decoder. By sequentially transferring to the arranged replacement control circuits, it is possible to freely determine the placement location of the redundancy fuse block without sacrificing the access speed.

  In the semiconductor memory device of this embodiment, the row replacement control circuit 108 controls the replacement of the row decoder 104 with m spare word lines WL <m>, and the column replacement control circuit 109 controls the column decoder. The replacement of m with 105 spare column selection lines CSL <m> is controlled.

  The low fuse block 106 is divided into a total number m of fuse sets, and each of the divided fuse sets is composed of a total number n + 1 fuses. Similarly, the column fuse block 107 is divided into a total number m of fuse sets, and each divided fuse set is composed of a total number n + 1 fuses.

  The output FR_OUT from the row parallel-serial conversion circuit 112 is a serial data line obtained by serially converting parallel data of (m × n) fuse data lines output from the row fuse block 106, and is output from the column parallel-serial conversion circuit 115. The output FC_OUT is a serial data line obtained by serially converting parallel data of (m × n) fuse data lines output from the column fuse block 107.

  The data FR_IN and FC_IN input from the data input control circuits 113 and 116 to the row and column replacement control circuits 108 and 109 are (m × n) pieces of row and column fuse data, respectively. is there.

  FIG. 15 shows an example of a detailed circuit configuration of the row-to-parallel conversion circuit 112 or the column-to-column conversion circuit 115 in FIG.

  In this parallel-serial conversion circuit, (m × n) clock-synchronous data transfer circuits 10 described in any of the first to third embodiments are provided. The data transfer circuit 10 is connected serially. Two-phase clock signals CK1, bCK1, and CK2, bCK2 generated by the control signal clock signal generation circuit 111 are used for data transfer control in each of the (m × n) data transfer circuits 10. The two-phase clock signals CK1, bCK1 and CK2, bCK2 are used for the data transfer periods in the two transfer gates 11, 12 or 11A, 12A in each data transfer circuit 10 as described above with reference to FIG. The phases are controlled so that they do not overlap each other.

  The parallel-serial conversion circuit receives (m × n) redundancy replacement data (fuse data) FDi (1) to FDi (m × n) output from the row fuse block 106 or the column fuse block 107 as clock signals. There are (m × n) fuse data transfer circuits 50 that perform transfer control in synchronization with CK3 and bCK3. The clock signals CK3 and bCK3 are used as fuse data fetch clock signals in the (m × n) fuse data transfer circuits 50. Redundancy replacement data FDo (1) to FDo (m × n) output from (m × n) fuse data transfer circuits 50 are data input nodes (IN) of (m × n) data transfer circuits 10. Is input.

  As shown in FIG. 16, the fuse data transfer circuit 50 in FIG. 15 may be configured using a CMOS type transfer gate TrsG controlled by clock signals CK3 and bCK3 which are fuse data fetch clock signals. The transfer gate TrsG is turned on when the clock signal CK3 is at “H” level and bCK3 is at “L” level, and the fuse data FDi from the fuse block 106 or 107 is transferred to (m × n) data transfer circuits. Transfer as FDo to the corresponding one of 10.

  FIG. 17 is a timing chart showing an example of the operation of the parallel-serial conversion circuit shown in FIG. The operation of the parallel-serial conversion circuit of FIG. 15 will be described below with reference to FIG.

  The period from time T0 to T1 is a period until the power supply potential inside the chip is determined. During this period, the control clock signal generation circuit 111 has the clock signal CK1 at “L” level, bCK1 at “H” level, Each clock signal is generated so that the signal CK2 is at “H” level, bCK2 is at “L” level, the clock signal CK3 is at “H” level, and bCK3 is at “L” level. As a result, the transfer gate 11 in each data transfer circuit 10 and the transfer gate TrsG in the fuse data transfer circuit 50 are turned on, and the fuse data from the fuse block is latched in the corresponding data transfer circuit 10. It is transmitted to the circuit 13.

  At time T1, when the power supply potential VCC inside the chip is determined and the chip ready signal CHRDY transitions from the “L” level to the “H” level, the clock signal CK1 remains at the “L” level and the bCK1 remains at the “H” level. However, the clock signal CK2 changes from "H" level to "L" level, bCK2 changes from "L" level to "H" level, the clock signal CK3 changes from "H" level to "L" level, bCK3 Changes from “L” level to “H” level. As a result, the transfer gate 11 in each data transfer circuit 10 and the transfer gate TrsG in the fuse data transfer circuit 50 are turned off, and the fuse data FDo from the fuse block is latched by the latch circuit 13 in each data transfer circuit 10. The

  After time T2, serially converted fuse data F_OUT is obtained by sequentially transferring fuse data in (m × n) data transfer circuits 10 in synchronization with clock signals CK1, bCK1, CK2, and bCK2. (FR_OUT or FC_OUT) is output from the data transfer circuit 10 at the last stage.

  FIG. 18 shows an example of a detailed circuit configuration of the row serial-parallel conversion circuit 114 or the column serial-parallel conversion circuit 117 in FIG.

  In this serial-parallel conversion circuit, (m × n) clock-synchronous data transfer circuits 10 described in any of the first to third embodiments are provided. The data transfer circuit 10 is connected serially. Two-phase clock signals CK1, bCK1, and CK2, bCK2 generated by the control signal clock signal generation circuit 111 are used for data transfer control in each of the (m × n) data transfer circuits 10. The two-phase clock signals CK1, bCK1 and CK2, bCK2 are used for the data transfer periods in the two transfer gates 11, 12 or 11A, 12A in each data transfer circuit 10 as described above with reference to FIG. The phases are controlled so that they do not overlap each other.

  FIG. 19 is a timing chart showing an example of the operation of the serial-parallel converter circuit shown in FIG. Hereinafter, the operation of the serial-parallel conversion circuit of FIG. 18 will be described with reference to FIG.

  The period from time T0 to T1 is a period until the power supply potential inside the chip is determined. During this period, the control clock signal generation circuit 111 has the clock signal CK1 at the “H” level, bCK1 at the “L” level, Each clock signal is generated so that the clock signal CK2 is at “H” level and bCK2 is at “L” level. As a result, both the transfer gates 11 and 12 in all the data transfer circuits 10 are turned on, and the (m × n) data transfer circuits 10 have the “L” level from the data input control circuit 113 or 116. Data is transmitted. That is, the outputs FD (N) (N = 1 to m × n) of all the data transfer circuits 10 are at the “L” level.

  At time T1, the power supply potential inside the chip is determined, and when the signal CHRDY transitions from the “L” level to the “H” level, the clock signal CK1 changes from the “H” level to the “L” level, and the bCK1 changes to the “L” level. To “H” level, the clock signal CK2 changes from “H” level to “L” level, and bCK2 changes from “L” level to “H” level. As a result, both the transfer gates 11 and 12 in each data transfer circuit 10 are turned off, and the “L” level data from the data input control circuit is latched by the latch circuits 13 and 14 in each data transfer circuit 10. As a result, all the data transfer circuits 10 are initialized to “L” level data.

  After the time T2, the fuse data is sequentially transferred in the (m × n) data transfer circuits 10 in synchronization with the clock signals CK1, bCK1 and CK2, bCK2, and finally converted into parallel. The fuse data FD (N) (N = 1 to m × n) is output in parallel from the (m × n) data transfer circuits 10.

  In the semiconductor memory device of this embodiment, the fuse data output from the fuse blocks 106 and 107 is converted into one serial data by parallel conversion, and the serial data is synchronized with a clock signal. By sequentially transferring the data to the replacement control circuits 108 and 109 arranged in the vicinity, the location of the redundancy fuse block can be freely determined without sacrificing the access speed.

  At that time, the serial-parallel conversion circuit and the parallel-serial conversion circuit are configured using the data transfer circuits according to the first to third embodiments, so that the fuse data is always synchronized with the reference clock signal without increasing the chip area. Can be transferred correctly.

1 is a circuit diagram of a data transfer circuit according to a first embodiment of the present invention. FIG. 2 is a timing diagram of a clock signal generated by a control clock signal generation circuit in FIG. 1. FIG. 2 is a circuit diagram showing an example of a specific circuit configuration of a control clock signal generation circuit in FIG. 1. FIG. 2 is a circuit diagram showing a circuit connection state between a data transfer circuit and a control clock signal generation circuit in FIG. 1 and a timing diagram of a clock signal supplied to the data transfer circuit. FIG. 5 is a timing chart showing an example of the operation of the circuit shown in FIG. 4. FIG. 2 is a circuit diagram showing a circuit connection state between a data transfer circuit and a control clock signal generation circuit in FIG. 1 and a timing diagram of a clock signal supplied to the data transfer circuit. FIG. 7 is a timing chart showing an example of the operation of the circuit shown in FIG. 6. The circuit diagram of the data transfer circuit concerning the 2nd Embodiment of this invention. The circuit diagram of the data transfer circuit concerning the 3rd Embodiment of this invention. The circuit diagram of the data input transfer circuit concerning the 4th Embodiment of this invention. FIG. 11 is a circuit diagram showing an example of a specific circuit configuration of the data input control circuit in FIG. 10. FIG. 11 is a circuit diagram showing an example of a specific circuit configuration of a control clock signal generation circuit in FIG. 10. FIG. 11 is a timing chart showing an example of the operation of the data input transfer circuit shown in FIG. 10. FIG. 9 is a block diagram showing a configuration of a semiconductor memory device according to a fifth embodiment of the present invention. FIG. 15 is a circuit diagram showing an example of a detailed circuit configuration of the parallel-serial conversion circuit in FIG. 14. FIG. 16 is a detailed circuit diagram of the fuse data transfer circuit in FIG. 15. FIG. 16 is a timing chart illustrating an example of the operation of the parallel-serial conversion circuit illustrated in FIG. 15. The circuit diagram which shows an example of the detailed circuit structure of the serial-parallel conversion circuit in FIG. FIG. 19 is a timing chart illustrating an example of the operation of the serial-parallel conversion circuit illustrated in FIG. 18. The circuit diagram which shows an example of the conventional data transfer circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11, 12, 11A, 12A ... Transfer gate, 13, 14 ... Latch circuit, 20, 20A ... Control clock signal generation circuit, 30 ... Data input control circuit, 100 ... Memory cell array, 1010 ... Normal cell array, 102, 103 ... Redundancy Cell array 104 ... Row decoder 105 ... Column decoder 106 ... Row fuse block 107 ... Column fuse block 108 ... Row replacement control circuit 109 ... Column replacement control circuit 110 ... Reference clock signal generation circuit DESCRIPTION OF SYMBOLS 111 ... Control clock signal generation circuit, 112 ... Row parallel-serial conversion circuit, 113 ... Data input control circuit, 114 ... Row serial-parallel conversion circuit, 115 ... Column parallel-serial conversion circuit, 116 ... Data input control circuit, 117 ... Column use Serial converter circuit.

Claims (6)

A first transfer gate controlled by a first clock signal to transfer input data;
A first latch circuit for latching data transferred by the first transfer gate;
A second transfer gate that is controlled by a second clock signal having a phase different from that of the first clock signal and transfers data latched by the first latch circuit;
A second latch circuit for latching and outputting the data transferred by the second transfer gate;
The phases of the first and second clock signals are controlled such that the data transfer periods in the first and second transfer gates do not overlap each other and the off periods of the first and second transfer gates overlap. A data transfer circuit which is characterized by the above. Each of the first and second transfer gates includes a transfer gate,
The first and second latch circuits each have an input terminal connected to an output terminal of the first inverter circuit and the first inverter circuit, and an output terminal connected to an input terminal of the first inverter circuit. 2. The data transfer circuit according to claim 1, comprising a second inverter circuit. Each of the first and second transfer gates includes a transfer gate,
Each of the first and second latch circuits includes an inverter circuit and a clocked inverter circuit having an input terminal connected to the output terminal of the inverter circuit and an output terminal connected to the input terminal of the inverter circuit. The data transfer circuit according to claim 1. Each of the first and second transfer gates includes a first clocked inverter circuit controlled by the first clock signal or the second clock signal,
The first and second latch circuits have an inverter circuit and an input terminal connected to an output terminal of the inverter circuit, an output terminal connected to the input terminal of the inverter circuit, and the first clock signal or the second latch circuit, respectively. 2. The data transfer circuit according to claim 1, comprising a second clocked inverter circuit controlled by two clock signals. A data transfer circuit for transferring data; and
A data input control circuit for supplying input data to the data transfer circuit and uniquely setting a level of the input data based on a reset signal;
The data transfer circuit includes:
A first transfer gate controlled by a first clock signal to transfer input data;
A first latch circuit for latching data transferred by the first transfer gate;
A second transfer gate that is controlled by a second clock signal having a phase different from that of the first clock signal and transfers data latched by the first latch circuit;
A second latch circuit that latches and outputs the data transferred by the second transfer gate, and the first and second clock signals transfer data in the first and second transfer gates. A data input transfer circuit characterized in that the phase is controlled so that the periods do not overlap each other and the off periods of the first and second transfer gates overlap. A plurality of memory cell array blocks each having a plurality of memory cell arrays each composed of a plurality of memory cells;
A row decoder and a column decoder, each provided corresponding to the plurality of memory cell array blocks, for selectively driving word lines and column selection lines in the memory cell array;
A row redundancy fuse block and a column redundancy fuse block for outputting redundancy replacement data for replacing the word line and the column selection line with a spare word line and a spare column selection line in parallel;
A clock signal generation circuit for generating first and second clock signals;
A redundancy replacement data output in parallel from both fuse blocks in synchronization with the first and second clock signals and converted into serial data; a parallel serial conversion circuit for row redundancy and a parallel serial conversion circuit for column redundancy;
Row redundancy serial parallel conversion circuit and column redundancy serial parallel conversion circuit for converting redundancy replacement data serially output from both parallel serial conversion circuits into parallel data in synchronization with the first and second clock signals When,
A row redundancy data input control circuit and a column redundancy data input control circuit which are provided between the two parallel serial conversion circuits and the two serial parallel conversion circuits and which uniquely set the level of output data based on a reset signal. When,
A row replacement control circuit and a column replacement control circuit for controlling replacement to a spare word line and a spare column selection line based on output data from the serial-parallel conversion circuits;
Each of the parallel-serial conversion circuits and the serial-parallel conversion circuits has a plurality of data transfer circuits connected in series for transferring 1-bit data,
Each of the plurality of data transfer circuits includes:
A first transfer gate controlled by the first clock signal to transfer input data;
A first latch circuit for latching data transferred by the first transfer gate;
A second transfer gate that is controlled by a second clock signal having a phase different from that of the first clock signal and transfers data latched by the first latch circuit;
A second latch circuit that latches and outputs the data transferred by the second transfer gate;
The phases of the first and second clock signals are controlled so that the data transfer periods in the first and second transfer gates do not overlap each other and the off periods of the first and second transfer gates overlap. A semiconductor memory device.

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