JP2003143499A - Digital television receiver, video data transmission circuit and video data reception circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable serial data transmission of video data at a low transmission speed of 20 Mbps or less. SOLUTION: A video data output means 10 outputs a video image clock and video image data. If a serial data transmission speed is lower than prescribed, a first select means 14 outputs a video clock multiplied by a clock multiplier circuit 13 to a serial data transmission means 15 by a selection signal of a selection means 11. Also, the video clock is outputted as a reproduction clock from a reproduction clock means 12 by the selection signal of the means 11. The means 15 transmits video data, a reproduction clock, the selection signal, and a synchronous clock to a serial data receiving means 16. The means 16 outputs the video data, the regenerated clock, the selection signal and the synchronous clock from the received serial data. A second select means 17 outputs the regenerated clock by the selection signal, and a video data receiving means 18 receives the video data synchronously with the regenerated clock. In this way, serial data transmission with a low transmission speed can be enabled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital television receiver, and more particularly to a digital television receiver for serially transmitting video data.

[0002]

2. Description of the Related Art At present, the image data of a digital television receiver is subjected to digital signal processing so as to be transmitted between boards and L
Some are transmitted to a digital drive display such as a CD. As a result, there is no need to perform conventional digital-to-analog, further analog-to-digital data conversion, and deterioration of video data due to conversion,
The complexity of the circuit can be suppressed.

As a method of transmitting digitized video data, LVDS (Low) which is a serial data transmission system is used.
Voltage Differential Signaling) and DVI (Digital V
video interactive). In the method based on LVDS or DVI, since video data is serialized from parallel and transmitted, the number of interfaces can be reduced, which is advantageous in design. Further, since it is transmitted as a differential signal, it is a highly effective transmission means with strong noise resistance.

The LVDS and DVI systems are currently one I
It is realized by C and serial data transmission is performed. When transmitting video data serially with this IC, the IC
It must be transmitted within the guaranteed operation range of the PLL (Phase Locked Loop) included therein. Therefore, the current 20
Only data transmission rates in the range of Mbps to 80 Mbps are guaranteed.

[0005]

However, the video data has a broadcast wave data format (SD: Standard Definit
ion, HD: High Definition, etc.) 13.5 Mbps
To 74.25 Mbps, the serial data transmission rate varies. When the video data is serially transmitted at 20 Mbps or less, there is a problem in that the video data cannot be transmitted because it falls below the guaranteed operation range of the PLL inside the IC.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a digital television receiver capable of serial data transmission of video data even at a low transmission speed.

[0007]

According to the present invention, in a digital television receiver in which video processing is digitized, a video clock, a video data output means for outputting video data synchronized with the video clock, and a broadcast wave. Selection means for outputting a selection signal according to the data format of the above, reproduction clock output means for outputting the video clock as a reproduction clock according to the selection signal, and clock multiplication means for multiplying the video clock and outputting a multiplication clock. When,
First select means for outputting one of the video clock or the multiplied clock as a synchronization clock in accordance with the selection signal; and the video data, the reproduction clock, the selection signal and the synchronization in synchronization with the synchronization clock. Serial data transmitting means for converting a clock into serial data for transmission, and serial data for receiving the serial data in synchronization with the synchronous clock and outputting the video data, the reproduction clock, the synchronous clock and the selection signal Receiving means, second selecting means for outputting one of the synchronous clock or the reproduced clock according to the selection signal, and the synchronous clock or the reproduced clock output from the second select means. Video data receiving means for receiving the video data. Digital television receiver is provided.

According to the above construction, serial data transmission of the video data is performed by the multiplied clock obtained by multiplying the video clock according to the selection signal, and the video data receiving means receives the video data in synchronization with the reproduction clock. Therefore, low-speed serial data transmission is possible.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a principle diagram showing the principle configuration of a digital television receiver of the present invention.

The digital television receiver shown in FIG. 1 includes a video data output means 10, a selection means 11, a reproduction clock means 12, a clock multiplication means 13, a first selection means 14, and a serial data transmission means 15. , Serial data receiving means 16, second selecting means 17, and video data receiving means 18.

The video data output means 10 outputs parallel video data to be displayed on the display screen of the digital television receiver. At this time, the video data is output in synchronization with the video clock. The video clock is also output from the video data output means 10 together with the video data.

The selection means 11 outputs a selection signal according to the data format of the broadcast wave received from the antenna. The reproduction clock means 12 is the video data output means 10.
The video clock output from the output unit is output as a reproduction clock according to the selection signal output from the selection unit 11.

The clock multiplication means 13 multiplies the video clock output from the video data output means 10 and outputs it. The first selecting unit 14 outputs the multiplied clock output from the clock multiplying unit 13 or the video data output unit 1 according to the selection signal output from the selecting unit 11.
Either one of the video clocks output from 0 is output as the synchronization clock.

The serial data transmission means 15 includes the video data output from the video data output means 10, the reproduction clock output from the reproduction clock means 12, and the selection means 11.
The selection signal output from the first selection unit 14 and the synchronization clock output from the first selection unit 14 are converted into serial data in synchronization with the synchronization clock and output. The serial data transmission means 15 also serially transmits transmission speed data in the range of 20 Mbps to 80 Mbps.

The serial data receiving means 16 receives the serial data transmitted from the serial data transmitting means 15,
Received via cable, video data, playback clock,
Synchronous clock and selection signal are converted into parallel and output.
The serial data receiving means 16 also receives data in the range of 20 Mbps to 80 Mbps.

The second selecting means 17 is a reproduction clock output from the serial data receiving means 16, or
Either one of the synchronous clocks is output according to the selection signal. The video data receiving means 18 is the second selecting means 1
The video data is received in synchronization with the reproduction clock or the synchronization clock output from 7.

The operation of the principle diagram of FIG. 1 will be described below. First, the operations of the video data output means 10 and the serial data transmission means 15 will be described. The video data output means 10 outputs a video clock and video data synchronized with the video clock. Serial data transmission means 15
Receives a video clock (when the video clock is output as a synchronous clock by the first selecting means 14 in FIG. 1), and serially transmits the video data at a transmission rate obtained by multiplying the video clock. In particular,
The video data is N-bit data, and the video clock is a clock having a frequency of fHz. Serial data transmission means 1
Reference numeral 5 serially transmits video data based on a transmission rate obtained by multiplying the frequency fHz of the video clock by N.

Here, it is assumed that the frequency of the video clock output from the video data output means 10 is lower than the transmission rate of 20 Mbps. The video data output from the video data output means 10 cannot be correctly converted into serial data by the serial data transmission means 15 and cannot be transmitted.

Therefore, when the frequency of the video clock output from the video data output means 10 is within the operation guarantee range of the serial data transmission means 15 (the transmission speed is 20 Mbps or more and 80 Mbps or less) and below the operation guarantee range. (Transmission speed is 20 Mbps or less) will be described separately.

The case where the frequency of the video clock output from the video data output means 10 is within the operation guarantee range of the serial data transmission means 15 will be described. The selection means 11 detects from the broadcast wave data format that the frequency of the video clock output from the video data output means 10 is within the guaranteed operation range of the serial data transmission means 15, and outputs a selection signal to that effect. Output.

The reproduction clock means 12 receives the selection signal from the selection means 11 and does not output the reproduction clock. The first selecting means 14 receives the selection signal from the selecting means 11 and outputs the video clock as a synchronous clock.

That is, when the frequency of the video clock output from the video data output means 10 is within the guaranteed operation range of the serial data transmission means 15, the video clock output from the video data output means 10 remains synchronized. It is output to the serial data transmission means 15 as a clock.

The serial data transmission means 15 includes the video data output from the video data output means 10 and the selection means 1.
The selection signal output from 1 and the synchronous clock selected by the first selection unit 14 are serially transmitted.

The serial data transmitted by the serial data transmitting means 15 is received by the serial data receiving means 16 via the cable. The serial data receiving unit 16 converts the received serial data into video data, a reproduction clock, a synchronization clock, and a selection signal in synchronization with the received synchronization clock, and outputs the video data.

The second selecting means 17 outputs a synchronous clock according to the selection signal. That is, the video clock is output from the second selecting means 17. The video data receiving means 18 inputs the video data output from the serial data receiving means 16 in synchronization with this synchronous clock.

Therefore, when the frequency of the video clock output from the video data output means 10 is within the operation guarantee range of the serial data transmission means 15, the serial data transmission means 15 is output from the video data output means 10. The video data is converted into serial data based on the video clock. The serial data receiving means 16 receives the serial data and outputs the video data, the synchronous clock and the selection signal based on the video clock. The second selecting means 17 uses the selection signal to output a synchronous clock, that is,
The video data is output by the video data receiving means 18 in synchronization with the video clock which is a synchronization clock. That is, the video data output from the video data output means 10 in synchronization with the video clock is received by the video data receiving means 18 in synchronization with the video clock.

Next, the case where the frequency of the video clock output from the video data output means 10 falls below the guaranteed operation range of the serial data transmission means 15 will be described. The selection means 11 determines that the frequency of the video clock output from the video data output means 10 is the serial data transmission means 15.
It is detected from the data format of the broadcast wave that the value falls below the operation guarantee range, and a selection signal to that effect is output.

The reproduction clock means 12 receives the selection signal from the selection means 11 and outputs the video clock output from the video data output means 10 as a reproduction clock.
The first selecting means 14 receives the selection signal from the selecting means 11 and outputs the video clock multiplied by the clock multiplying means 13.

That is, when the frequency of the video clock output from the video data output means 10 is lower than the guaranteed operation range of the serial data transmission means 15, the video clock output from the video data output means 10 is the clock multiplication means 13. Thus, the serial data transmission means 15 is multiplied so as to fall within the guaranteed operation range. The multiplied video clock is output to the serial data transmission means 15 as a synchronization clock by the first selection means 14. Therefore, the serial data transmission means 15 can serially transmit the video data.

The serial data transmission means 15 includes the video data output from the video data output means 10 and the selection means 1.
The selection signal output from 1 and the synchronous clock selected by the first selecting means 14 are synchronized with the synchronous clock for serial data transmission.

The serial data transmitted by the serial data transmitting means 15 is the serial data receiving means 16
Received by. The serial data receiving means 16 is
The received serial data is converted into video data, a selection signal, and a synchronization clock in synchronization with the received synchronization clock and output. That is, the video data is output in synchronization with the multiplied clock obtained by multiplying the video clock output from the video data output means 10.

The second selecting means 17 outputs a reproduction clock according to the selection signal output from the serial data receiving means 16. The video data receiving means 18 receives the video data in synchronization with the reproduction clock output from the second selecting means 17.

Therefore, when the frequency of the video clock output from the video data output means 10 falls below the operation guarantee range of the serial data transmission means 15, the serial data transmission means 15 outputs the video output from the video data output means 10. The video data is converted into serial data in synchronization with the multiplied clock obtained by multiplying the clock. The serial data receiving means 16 receives the serial data and outputs the video data, the reproduction clock, the synchronization clock and the selection signal in synchronization with the multiplication clock. The second selecting means 17 outputs the reproduction clock, that is, the video clock to the video data receiving means 18 according to the selection signal. The video data receiving unit 18 receives the video data in synchronization with the video clock which is the reproduction clock, and thereby the video data output unit 1
The same data as the video data output from 0 can be received.

Thus, the serial data transmission means 1
5. The video data can be transmitted even at a serial transmission speed below the guaranteed operating range of the serial data receiving means 16.

Next, an example of the embodiment of the present invention will be described. FIG. 2 is a schematic configuration diagram of the digital television receiver of the present invention. As shown in FIG. 2, the digital television receiver includes an antenna 20, a tuner 21, and a decoder 22.
, CPU (Central Processing Unit) 23, and RO
M (Read Only Memory) 24 and RAM (Random Acces
s Memory) 25, a video data transmission circuit 26, a video data reception circuit 27, and an LCD (Liquid Crystal Displa).
y) 28.

The antenna 20 receives the digital broadcast wave and sends it to the tuner 21. The tuner 21 is the antenna 2
The digital broadcast wave received by 0 is subjected to high frequency processing and demodulated.

The decoder 22 separates high-frequency processed and demodulated digital broadcast wave image data from audio data. The CPU 23 processes the video data separated by the decoder 22 into video data that can be displayed on the LCD 28 according to a program stored in the ROM 24.

The ROM 24 stores a program for operating the CPU 23, and the RAM 25 stores the program in the CPU 23.
Is the work area for executing the program. The video data transmission circuit 26 is a circuit capable of serial data transmission of video data at a low transmission rate of 20 Mbps or less.

The video data receiving circuit 27 is a circuit capable of receiving serial data transmitted by the video data transmitting circuit 26 at a low transmission rate of 20 Mbps or less. LC
D28 displays the video data received by the video data receiving circuit 27.

The digital broadcast wave is received by the antenna 20 and passed through the tuner 21 and the decoder 22 to the CPU.
Sent to 23. The CPU 23 processes the digital broadcast wave into parallel video data that can be displayed on the LCD 28 according to the program in the ROM 24, and sends the video data to the video data transmission circuit 26. The video data transmission circuit 26 converts the video data into serial data and sends it to the video data reception circuit 27. The video data receiving circuit 27 converts the serial data into parallel video data and sends it to the LCD 28.

FIG. 3 is a diagram showing a circuit for transmitting video data of the digital television receiver of the present invention, and FIG. 4 is a diagram showing a circuit for receiving video data. The circuit for transmitting the video data of the digital television receiver shown in FIG. 3 includes a video device 30, a CPU 31, a PLL 32, and a selector 33.
And a flip-flop (hereinafter referred to as FF) circuit 34
, An LVDS circuit 35, an inverter circuit Z1, and an AND circuit Z2.

The video device 30 has an 8-bit luminance signal Y [7: 0] and an 8-bit chroma signal C [7: 0].
, A horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync
c and the video clock CLK are output. Video device 3
0 is an 8-bit luminance signal Y [7: 0], an 8-bit chroma signal C [7: 0], and a horizontal synchronization signal Hsync.
And the video data of the vertical synchronization signal Vsync is output in synchronization with the video clock CLK. Also, the video device 30 sends video data to 74.25 MHz and 13.5 MH.
It is assumed that the image can be output with two types of video clocks of z.

The CPU 31 processes digital broadcast waves received by an antenna (not shown) and demodulated by a tuner or the like into video data that can be displayed on a display screen or the like. The processed video data is sent to the video device 30.
Further, the CPU 31 outputs the selection signal CLKSEL according to the data format of the broadcast wave received from the antenna. According to the data format of the broadcast wave, when the video data is output from the video device 30 at 13.5 Mbps, the selection signal CLKSEL outputs the state of "H", and when it is output at 74.25 Mbps, the selection signal CLKSEL is output. As for CLKSEL, the state of “L” is output.

The PLL 32 multiplies the video clock CLK output from the video device 30 and outputs it to the selector 33. Here, the video clock CLK is doubled and output.

The selector 33 multiplies the video clock CLK output from the PLL 32 in accordance with the selection signal CLKSEL output from the CPU 31 and the video device 30.
Either one of the video clocks CLK output from is output as the synchronization clock LVDSCLK. Selector 3
3 outputs the video clock CLK output from the video device 30 as the synchronous clock LVDSCLK when the selection signal CLKSEL is in the “L” state, and outputs the selection signal CLK.
When the SEL is in the “H” state, the multiplied video clock CLK output from the PLL 32 is used as the synchronous clock LVDS.
Output as CLK.

The inverter circuit Z1 is used in the video device 30.
The video clock CLK output from is inverted and output to the AND circuit Z2. The AND circuit Z2, when the selection signal CLKSEL output from the CPU 31 is in the “H” state,
Video clock CLK output from the inverter circuit Z1
Is output as a reproduction clock DATCLK. The AND circuit Z2 outputs the selection signal CLKS output from the CPU 31.
When EL is in the "L" state, it outputs the "L" state.

The FF circuit 34 outputs the video data output from the video device 30, the selection signal CLKSEL output from the CPU 31, the reproduction clock DATCLK output from the AND circuit Z2, and the synchronization clock LVDSCLK output from the selector 33. Output at the rising edge or the falling edge. The FF circuit 34 synchronously outputs the video data and the video clock CLK output as the reproduction clock DATCLK via the inverter circuit Z1 and the AND circuit Z2 to the LVDS circuit 35.

The LVDS circuit 35 internally multiplies the synchronous clock LVDSCLK output from the selector 33,
Video data, a selection signal CLKSEL, and a reproduction clock DAT are synchronized with the multiplied synchronization clock LVDSCLK.
CLK is converted to serial data and output.

Specifically, the synchronous clock LVDSCLK
Is multiplied by 7 by a PLL having
Bits 0 to 6 of [7: 0] are signal lines TXOUT0 + and signal lines TXOU as differential serial data.
Output to T0-. Similarly, the luminance signal Y [7: 0] of 7
5th bit and 0th bit of chroma signal C [7: 0]
Signal line TX with differential serial data up to the bit
Output to OUT1 + and signal line TXOUT1-. Further, 6 bits and 7 bits of the chroma signal C [7: 0],
The horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, the selection signal CLKSEL, and the reproduction clock DATCLK are output to the signal line TXOUT2 + and the signal line TXOUT2- as differential serial data. Furthermore, the synchronization clock LV
Signal line TXCL with the 7th multiplication of DSCLK as differential data
It outputs to K_OUT + and signal line TXCLK_OUT-. Thereby, for example, when the video data is output from the video device 30 at 74.25 Mbps, 519.
It is transmitted as 75 Mbps serial data.

The LVDS circuit 35 has a range of transmission speed for transmitting serial data. Specifically, 20
Only data in the range of MHz to 80 MHz can be serially transmitted.

The digital television receiver shown in FIG.
It is composed of a circuit 40, a selector 41, and a video device 42. The LVDS circuit 40 includes signal lines TXOUT0 + to TXOUT2 + of the LVDS circuit 35 and a signal line TXO.
UT0- to TXOUT2- and the signal line TXCLK_OU
The differential serial data output from T + and the signal line TXCLK_OUT- is transferred to the signal lines RTIN0 + to RTIN.
2+, the signal lines RTIN0- to RTIN2-, the signal line RXCLK_IN +, and the signal line RXCLK_IN-. The LVDS circuit 40 uses the signal line RXCLK_IN
+, 8-bit luminance signal Y in synchronization with the synchronization clock LVDSCLK received on the signal line RXCLK_IN-
[7: 0], 8-bit chroma signal C [7: 0], horizontal sync signal Hsync, vertical sync signal Vsync, video data, selection signal CLKSEL, and reproduction clock DAT.
Output CLK.

The inverter circuit Z3 is the LVDS circuit 40.
Inverts the synchronous clock LVDSCLK received at.
The selector 41 receives the reproduction clock DATCLK or the synchronization clock L received by the LVDS circuit 40 according to the selection signal CLKSEL received by the LVDS circuit 40.
Either one of VDSCLK is output. Selector 41
Outputs the synchronization clock LVDSCLK when the selection signal CLKSEL is in the “L” state, and the selection signal CLKSEL
Is in the "H" state, the reproduction clock DATCLK is output.

The video device 42 receives the video data in synchronization with the reproduction clock DATCLK or the synchronous clock LVDSCLK output from the selector 41.
The operation of the circuit for transmitting video data of the digital television receiver shown in FIG. 3 and the operation of the circuit for receiving video data shown in FIG. 4 will be described below with reference to the signal state diagram of the circuit shown in FIG. FIG. 5A shows a signal state when the video clock is within the operation guarantee range of the LVDS circuit, and FIG. 5B shows a signal state when the video clock is outside the operation guarantee range of the LVDS circuit.

First, the case where the video data is output at 74.25 Mbps will be described with reference to FIG. In this case, the LVDS circuit 35 transmits the 719-multiplied serial data of 519.75 Mbps. 74.25 Mbps is the LVDS circuit 35
Is within the operation guarantee range of the CPU 31, and the CPU 31 sets “L”.
The selection signal CLKSEL in the state of is output.

Since the selection signal CLKSEL is in the "L" state, the AND circuit Z2 outputs the reproduction clock DATCLK in the "L" state. Further, the selector 33 outputs the video clock CLK output from the video device 30 as the synchronous clock LVDSCLK.

The FF circuit 34 uses the synchronous clock LVDSC.
In synchronization with LK, video data, selection signal CLKSEL,
The reproduction clock DATCLK is output. As a result, the reproduction clock DATCLK delayed via the inverter circuit Z1 and the AND circuit Z2 is synchronized with the video data.

Video data output from the FF circuit 34,
The selection signal CLKSEL and the reproduction clock DATCLK are
It is sent to the LVDS circuit 35 and output as serial data. At this time, the synchronization clock LVDSCLK is multiplied by 7, that is, the video clock CLK of 74.25 MHz.
Is transmitted at a transmission rate of 519.75 Mbps, which is a multiple of 7.

The serial data is received by the LVDS circuit 40, and has an 8-bit luminance signal Y [7: 0], an 8-bit chroma signal C [7: 0], and a horizontal synchronizing signal Hsyn.
c, the video data of the vertical synchronization signal Vsync, the selection signal CLKSEL, and the reproduction clock DATCLK are output in synchronization with the synchronization clock LVDSCLK. Since the synchronous clock LVDSCLK is the video clock CLK, the video data is output at 74.25 MHz, which is the same as the cycle output from the video device 30.

Since the selection signal CLKSEL is in the "L" state, the selector 41 outputs the synchronous clock LVDSCLK. That is, the video device 42 receives the video data in synchronization with the video clock CLK output from the video device 30.

Next, a case where the video data is output at a cycle of 13.5 Mbps will be described with reference to FIG. When output in this cycle, LVDS
It is multiplied by 7 by the circuit 35 and transmitted as serial data of 94.5 Mbps. 13.5Mbp
s is below the operation guarantee range of the LVDS circuit 35, and CP
U31 outputs the selection signal CLKSEL in the "H" state.

When the selection signal CLKSEL is "H", the video clock CLK is output as the reproduction clock DATCLK from the AND circuit Z2. Further, the selector 33 outputs the video clock doubled by the PLL 32 as the synchronous clock LVDSCLK.

The FF circuit 34 uses the synchronous clock LVDSC.
In synchronization with LK, video data, selection signal CLKSEL,
The reproduction clock DATCLK is output. As a result, the reproduction clock DATCLK delayed via the inverter circuit Z1 and the AND circuit Z2 is synchronized with the video data.

The synchronized video data output from the FF circuit 34, the selection signal CLKSEL, and the reproduction clock DATC.
The LK is sent to the LVDS circuit 35 and output as serial data. At this time, the synchronization clock LVDSCL
7 times K, that is, 27 MHz by PLL32.
It is transmitted at a transmission rate of 189 Mbps, which is a 7-fold multiplication of the video clock CLK used as the clock. The transmission rate of 27 MHz is within the operation guarantee range of the LVDS circuit 35, and serial data transmission can be effectively performed.

The serial data is received by the LVDS circuit 40, and has an 8-bit luminance signal Y [7: 0], an 8-bit chroma signal C [7: 0], and a horizontal synchronizing signal Hsyn.
c, the video data of the vertical synchronization signal Vsync, the selection signal CLKSEL, and the reproduction clock DATCLK are output in synchronization with the synchronization clock LVDSCLK. Since the synchronous clock LVDSCLK is the video clock CLK doubled by the PLL 32, the video data is 27 MH.
It is output in the z cycle.

Since the selection signal CLKSEL is in the "H" state, the selector 41 selects and outputs the reproduction clock DATCLK. That is, the video device 42
Will receive the video data in synchronization with the video clock output from the video device 30.

As described above, even when serial transmission is performed within the operation guarantee range of the LVDS circuit 35, the LVD
A synchronous clock LVDSCLK that enables serial data transmission within the operation guarantee range of the S circuit 35 is generated from the PLL 32, and serial transmission is performed in synchronization with this synchronous clock LVDSCLK. LVDS to receive serial data
The circuit 40 outputs the video data in synchronization with the synchronization clock LVDSCLK, and the video device 42 receives the data in synchronization with the reproduction clock DATCLK. This enables effective data transmission even at a low transmission rate.

In the above explanation, the video clock CLK is explained as being multiplied by 2 by the PLL 32.
The video clock CLK may be multiplied so as to fall within the operation guarantee range of the DS circuits 35 and 40, but is not limited to this.

Further, since the inverter circuit Z1 shifts the edges of the reproduction clock DATCLK and the synchronization clock LVDSCLK (to prevent the FF circuit 34 from becoming indefinite),
In the inverter circuit Z3, the video device 42 uses the synchronous clock LVDSCLK or the reproduction clock DATCL.
It is provided to receive video data at the rising and falling edges of K, and is attached as necessary.

Further, only the video data transmission circuit for transmitting the video data shown in FIG. 3 may be mounted on the digital television receiver, and only the video data receiving circuit for receiving the video data shown in FIG. 4 may be mounted. . For example, from a digital television receiver that has only a circuit that transmits video data, transmit the video data to a digital television receiver that has only a circuit that receives the video data via a cable that transmits the serial data. It is possible to display the transmitted video data.

Next, a timing chart when the video clock of FIG. 6 is within the operation guarantee range of the LVDS circuit will be described. FIG. 6A shows the video data output from the video device 30 and the video clock CLK.

FIG. 6B shows the video data at the input stage of the FF circuit 34, the reproduction clock DATCLK, and the synchronization clock LVDSCLK. Video clock CLK
Is synchronized with the synchronous clock LVDSCLK via the selector 33.
Is output as. Therefore, the synchronization clock LVDSC
LK is delayed from the video clock CLK of FIG.
It is input to the F circuit 34. Also, the reproduction clock DATC
LK is the selection signal CLKSEL from the “L” state,
The "L" state is output.

FIG. 6C shows the video data at the output stage of the FF circuit 34, the reproduction clock DATCLK, and the synchronization clock LVDSCLK. The video data is shown in Figure 6.
When the synchronous clock LVDSCLK of (b) rises, F
It is output from the F circuit 34. Video clock CLK, reproduction clock DATCLK, synchronous clock LVDSCLK
Are transmitted to the LVDS circuit 40 by the LVDS circuit 35.

FIG. 6D shows the video data on the receiving side, the reproduction clock DATCLK, and the synchronization clock LVDSCL.
K is shown. The LVDS circuit 40 outputs the video data in synchronization with the synchronization clock LVDSCLK shown in FIG.

The selector 41 outputs the synchronous clock LVDSCLK in response to the selection signal CLKSEL, and the video device 42 receives the video data in synchronization with the rising of the synchronous clock LVDSCLK.

FIG. 7 shows a timing chart when the video clock falls below the operation guarantee range of the LVDS circuit.
(A) is video data output from a video device,
The video clock CLK is shown.

FIG. 7B shows the video data in the input stage of the FF circuit 34, the reproduction clock DATCLK, and the video clock CLK. When the selection signal CLKSEL is in the “H” state, the video clock C is output from the selector 33.
The video clock CLK, which is LK multiplied by 2, is the synchronous clock L.
VDSCLK is output, and the video clock CLK is output from the AND circuit Z2 as the reproduction clock DATCLK.
Is output as. Also, the reproduction clock DATCLK,
The synchronous clock LVDSCLK is the inverter circuit Z1,
Since it goes through the logical product circuit Z2 and the selector 33, FIG.
Is input to the FF circuit 34 later than the video clock CLK.

FIG. 7C shows the video data at the output stage of the FF circuit 34, the reproduction clock DATCLK, and the synchronization clock LVDSCLK. The video data is shown in Figure 7.
When the synchronous clock LVDSCLK of (b) rises, F
It is output from the F circuit 34. That is, the same video data is output twice. The video clock CLK, the reproduction clock DATCLK, and the synchronous clock LVDSCLK are LVD
It is transmitted to the LVDS circuit 40 by the S circuit 35.

FIG. 7D shows the video data on the receiving side, the reproduction clock DATCLK, and the synchronization clock LVDSCL.
K is shown. The LVDS circuit 40 outputs the video data in synchronization with the synchronous clock LVDSCLK as shown in FIG. The selector 33 outputs the reproduction clock DATCLK in response to the selection signal CLKSEL, and the video device 30 receives the video data in synchronization with the rising of the reproduction clock DATCLK. That is, the video device 30 outputs the same video data that is continuously output twice.
Only one of them will be received by the reproduction clock DATCLK.

In this way, it becomes possible to perform serial data transmission at a low transmission rate.

[0080]

As described above, according to the present invention, serial data transmission of video data is performed by a multiplied clock obtained by multiplying the video clock according to the selection signal, and the video data receiving means synchronizes with the reproduction clock. It is configured to receive video data. As a result, it becomes possible to transmit serial data at a low transmission rate.

[Brief description of drawings]

FIG. 1 is a principle diagram of a digital television receiver of the present invention.

FIG. 2 is a schematic configuration diagram of a digital television receiver of the present invention.

FIG. 3 is a circuit diagram of a transmission circuit that transmits video data.

FIG. 4 is a circuit diagram of a receiving circuit that receives video data.

FIG. 5 is a diagram showing a signal state of the circuit, in which (a) shows a case where the video clock is within the operation guarantee range of the LVDS circuit.
(B) shows the signal state when the video clock is out of the operation guarantee range of the LVDS circuit.

FIG. 6 shows a timing chart when the video clock is within the operation guarantee range of the LVDS circuit, (a) shows video data output from the video device, and the video clock C.
LK, (b) shows the FF circuit input stage, (c) shows the FF circuit output stage, and (d) shows the video data, the reproduction clock DATCLK, and the synchronous clock LVDSCLK at the receiving side.

FIG. 7 shows a timing chart when the video clock falls below the operation guarantee range of the LVDS circuit, (a) shows video data output from the video device, and the video clock C.
LK, (b) shows the FF circuit input stage, (c) shows the FF circuit output stage, and (d) shows the video data at the receiving side, the reproduction clock DATCLK, and the synchronization clock LVDSCLK.

[Explanation of symbols]

10 ... Video data output means, 11 ... Selection means, 12
...... Reproduction clock means, 13 ...... Clock multiplication means, 1
4 ... First selecting means, 15 ... Serial data transmitting means, 16 ... Serial data receiving means, 17 ... Second selecting means, 18 ... Video data receiving means, 20
... antenna, 21 ... tuner, 22 ... decoder,
23 ... CPU, 24 ... ROM, 25 ... RAM, 2
6 ... video data transmission circuit, 27 ... video data reception circuit, 28 ... LCD, 30, 42 ... video device, 3
1 ... CPU, 32 ... PLL, 33, 41 ... Selector, 34 ... FF circuit, 35, 40 ... LVDS circuit.

Claims (5)

[Claims] 1. A digital television receiver in which video processing is digitized, a video clock, a video data output means for outputting video data synchronized with the video clock, and a selection signal according to a data format of a broadcast wave. Selection means, a reproduction clock output means for outputting the video clock as a reproduction clock according to the selection signal, a clock multiplication means for multiplying the video clock and outputting a multiplication clock, and the video according to the selection signal First select means for outputting one of a clock and the multiplied clock as a synchronous clock; and converting the video data, the reproduction clock, the selection signal and the synchronous clock into serial data in synchronization with the synchronous clock. Serial data transmission means for transmitting the serial data, A serial data receiving unit that receives in synchronization with a clock and outputs the video data, the reproduction clock, the synchronization clock, and the selection signal, and outputs one of the synchronization clock or the reproduction clock according to the selection signal. Digital television reception, comprising: a second selecting unit; and a video data receiving unit that receives the video data in synchronization with the synchronous clock or the reproduction clock output from the second selecting unit. Machine. 2. When the serial data transmission means and the serial data reception means perform serial data transmission at 20 Mbps or less, the selection means outputs a selection signal for performing a transmission speed of 20 Mbps or less, and the selection signal The reproduction clock output means outputs the reproduction clock, the first selection means outputs the multiplied clock as a synchronous clock, and the second selection means outputs the reproduction clock. Item 1. A digital television receiver according to item 1. 3. When the serial data transmission means and the serial data reception means perform serial data transmission of 20 Mbps or more, the selection means outputs a selection signal for performing a transmission speed of 20 Mbps or more, and the selection signal 2. The digital television receiver according to claim 1, wherein the first selecting means outputs the video clock as a synchronous clock, and the second selecting means outputs the synchronous clock. 4. A video data transmission circuit in which video processing is digitized, a video clock, a video data output means for outputting video data in synchronization with the video clock, and a selection signal according to a data format of a broadcast wave. Selection means, a reproduction clock output means for outputting the video clock as a reproduction clock according to the selection signal, a clock multiplication means for multiplying the video clock and outputting a multiplication clock, and the video according to the selection signal Select means for outputting one of a clock and the multiplied clock as a synchronous clock; and a serial for converting the video data, the reproduction clock, the selection signal and the synchronous clock into serial data in synchronization with the synchronous clock and transmitting the serial data. Video data comprising: a data transmission means Transmission circuit. 5. A video data receiving circuit in which video processing is digitized, serial data receiving means for receiving serial data in synchronization with a synchronous clock and outputting video data, a reproduction clock, a selection signal and a synchronous clock, Select means for outputting one of the synchronous clock or the reproduced clock according to a selection signal; and video data receiving means for receiving the video data in synchronization with the synchronous clock or the reproduced clock output from the select means. A video data receiving circuit comprising: