JP2002169770A - Picture data transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a picture data transfer system which can correct the dispersion of the delay time of signal transmission, which occurs between two sets of LVDS devices. SOLUTION: In a picture reading part 10, the same LSYNC signals included are transmitted into respective LVDS transmission lines. A picture processing part 20 calculates signal delay time caused in the transmission lines by the LSYNC signal and generates a writing timing signal controlling writing timing to a plurality of FIFO memories for writing picture data based on calculated signal delay time. Thus, the phases of RGB picture data written into the FIFO memories can securely be adjusted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image data transfer system for transferring one image data by dividing it into a plurality of LVDS devices.

[0002]

2. Description of the Related Art An image reading section (scanner) and a printer engine section are physically separated from each other because of different devices. In such a system configuration, LVDS is used to perform high-speed transmission of a large amount of data such as a read image.
(Low voltage differential signal) interface is provided.

FIG. 2 shows a configuration of a conventional image reading section 10 and an I / F section of an image processing section 20 of a printer engine.

The LDVS device uses an LVDS transmitter 15 of parallel input and serial output, and an LVDS receiver 21 of serial input and parallel output (so-called FPD link), so that the image reading unit 10 and the image processing unit 20 of the printer engine can be used. , The number of I / F cables can be reduced, and EMI can be suppressed.

When the resolution of the A / D converter 13 is 6 bits, the digital image signal has a total of 18 bits (6 bits for each of RGB), and if a general 6-bit color FPD link device is used, the control can be performed. Signal transmission of 21 bits including signals is performed by three pairs of differential data signals and one differential clock signal.
It can be composed of a total of eight cables in pairs.

[0006] The LVDS transmitter 15 transmits a 6-bit RGB digital image signal sent from the A / D converter 13 and a main scanning direction synchronization signal (LSYNC signal) which is a timing signal output from the controller 14. Total 1
Nine CMOS S / TTL signals are sampled at every falling cycle of the clock, and are converted into three-channel LVDS serial signals by a built-in PLL circuit. The output per channel is 7 bits per cycle. When the clock is 40 MHz, the data transmission rate per channel becomes 280 Mbps.
In total, 840 Mbps (105 Mbps)
Bytes / s).

[0007] The LVDS receiver 21 performs serial-parallel conversion on the LVDS serial data and clock of three channels sent from the LVDS transceiver 15. The LVDS receiver 21 also has a built-in PLL circuit, and automatically generates a strobe signal for detecting the input 7-bit signal at the falling edge of the clock, and outputs parallel data, that is, a digital image signal of 6 bits each for RGB. And a total of 19 CMOSs of the LSYNC signal
/ TTL signal.

[0008] LVDS transmitter 1 for FPD link
5 and the LVDS receiver 21, the AC characteristics and the skew satisfy a certain standard value, and the individual data (6 bit digital image signal and LSYNC signal for each of RGB) and the clock are transmitted to the LVDS receiver 21 by the LVDS receiver 21. The setup time and hold time of the strobe signal are guaranteed.

By the way, the resolution of the image reading section 10 has recently been increased, and the resolution of the A / D conversion section 13 requires 10 bits. FIG. 3 shows a block diagram of the image reading unit (scanner) 10 and the I / F unit of the image processing unit 20 of the printer engine in this case.

[0010] The LVDS device of the FPD link was originally developed for a liquid crystal panel display (LCD), and for a 6-bit RGB signal (18 bits),
For 8-bit RGB signals (24 bits) is common. For a digital image signal of 10 bits (30 bits) for each of RGB transmitted from the A / D converter 13, two LVDS devices for 6-bit RGB signals (18 bits) are used.
20 bits of digital image signals of R and G
The B digital image signal and L
By transmitting the SYNC signal to the LVDS transmitter 18, a total of 31 signals of the RGB 10-bit digital image signal and the LSYNC signal are converted into eight pairs of LVD signals.
Image processing unit 20 of printer engine unit by S serial output
Transfer to

The image processing unit 20 performs serial / parallel conversion of the four pairs of LVDS serial output signals including the R and G image data by the LVDS receiver 22, and outputs one R, G, and B signal.
Obtain a 0-bit digital image signal. Similarly, four pairs of LVDS serial output signals including the B image signal and the LSYNC signal are subjected to serial / parallel conversion by the LVDS receiver 23, and finally a digital image signal of 10 bits (30 bits) of RGB and an LSYNC signal are obtained. At this time,
LVDS transmitter 17 and LVDS receiver 22,
And LVDS transmitter 18 and LVDS receiver 2
No. 3 satisfies a certain standard value in AC characteristics and skew by FPD link transmission.
Guaranteed for the transfer clock.

However, the LVDS transmitter 1
7 from the LVDS receiver 22
In the digital image signal of 10 bits each of RG generated by serial-parallel conversion in, the transfer clock is guaranteed, but the RG is compared with the reference clock.
It is inevitable that a phase shift between the image signal and the B image signal may occur.

Therefore, as shown in FIG. 3, the digital image signal of each color of RGB generated by the LVDS receivers 22 and 23 is temporarily stored in a FIFO memory prepared for each color to absorb the phase shift.

The R digital image signal bus of the LVDS receiver 22 is input to the FIFO memory 25. F
The write clock of the IFO memory 25 is the LVDS transfer clock from the LVDS transmitter 17,
Data is guaranteed by using the clock output of the VDS receiver 22.

Similarly, the FIFO memory 26 has an LVD
The G digital image signal bus of the S receiver 22 is input,
The write clock uses the clock output of the LVDS receiver 22, the FIFO memory 27 receives the B digital image signal bus of the LVDS receiver 23, and the write clock uses the clock output of the LVDS receiver 23, thereby using the FIFO memories 25 to 27. Each store a 10-bit digital image signal.

The read timing of the FIFO memories 25 to 27 can be asynchronously performed without depending on the write timing of each FIFO memory, so that the phase of the digital image signal of each color of RGB can be surely matched.

In writing data into the FIFO memories 25 to 27, it is necessary to detect one line of valid data. Therefore, the LSYNC signal (main scanning direction synchronization signal) from the control unit 14 of the image reading apparatus 10 is input to the timing generation unit 24 via the LVDS transmitter 18 and the LVDS receiver 23, and the write timing signals (for the FIFO memories 25 to 27) A Write Enable signal (hereinafter, referred to as a WE signal) is generated, and writing of the FIFO memories 25 to 27 is controlled. This allows the FIF
Only valid data can be written into the O memories 25 to 27.

[0018]

However, the FIF
The phase difference between the RG image signal and the B image signal that can be absorbed by the O memory is within the range of one reference clock, and if a further deviation occurs, the FIFO memory absorbs the phase difference. You will not be able to do that. For example, L
The longer the distance between the VDS transmitter and the LVDS receiver, the more the delay time varies,
It cannot be absorbed by the O memory.

Therefore, it is necessary to manage the dispersion of the delay time between the two LDVS devices (between the transmitter and the receiver), but this becomes very difficult for the following reasons. For example, even if the LVDS transmitter and the LVDS receiver are arranged close to each other on the same substrate, there is a variation of about 1 ns (the data book is described with a width of several ns). Also, different systems (boards)
Are connected by cable wiring, the variation cannot be ignored due to the board wiring capacity and the cable wiring capacity. Although not shown in FIGS. 2 and 3, the LVDS transceiver and the LVDS receiver are connected by a cable via a connector. This cable is composed of eight pairs of three pairs of differential data signals and one pair of differential clocks. The wiring pattern of the cable between the LVDS device and the connector must be all equal in length. Also, it is necessary to minimize the difference between the lengths of the wires included in the cable.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide an image data transfer system capable of surely adjusting the phases of digital image signals of RGB colors.

[0021]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention is an image data transfer system for splitting and transferring one image data to a plurality of LVDS devices. In the LVDS transmission line,
The same image data synchronization signal is included and transmitted to the receiving side,
On the receiving side, a signal delay time generated in each transmission path is calculated by the same image data synchronization signal, and a write timing signal for controlling a write timing to a plurality of memories for writing image data is calculated. It is characterized by being created based on

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the image data transfer system of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of an image data transfer system according to the present invention. Note that the same devices as those in the above-described conventional technology will be described with the same reference numerals.

The embodiment according to the present invention includes an image reading unit 10 and an image processing unit 20 as shown in FIG. 1, and an LVDS interface is provided as an interface between these devices. The image reading unit 10 is applied to a scanner or the like, and the image processing unit 20 is mounted on a printer engine or the like.

The image reading section 10 includes a CCD 11, an analog processing section 12, an A / D conversion section 13, and a control section 14.
And LVDS transmitters 17 and 18.

The image processing unit 20 includes an LVDS receiver 22, 23, a timing generation unit 24, and a FIFO (F
IRST IN FIRST OUT) memories 25, 26, 27.

R, G, photoelectrically converted by the CCD 11,
The B image signal is input to the analog processing unit 12, subjected to signal amplification, signal synthesis, variable amplification, and other processing, and converted to a digital image signal by the A / D conversion unit 13. CCD1
1. The analog processing unit 12 and the A / D conversion unit 13 are controlled by a timing signal from the control unit 14 and a read clock.

The resolution of the A / D converter 13 is 10 bits, and the A / D converter 13 outputs a digital image signal of 10 bits (30 bits) for each of RGB.

Image reading unit 1 applied to a scanner or the like
0, an image processing unit 20 mounted on a printer engine or the like
Are physically separated because the devices are different. To perform such high-speed transmission of large amounts of data, LVDS
(Low voltage differential signal) interface is provided.

The LVDS transmitters 17 and 18 have a parallel input and a serial output, respectively.
Reference numerals 2 and 23 are a serial input and a parallel output. A /
RGB 10 bits (30 bits) transmitted from the D conversion unit 13
6 bit RG for a digital image signal of
Two sets of B signal (18 bit) LVDS devices are used.
20 bits of the R and G digital image signals, the LSYNC signal which is a timing signal output from the control unit 14, and the transfer clock are transmitted to the LVDS transmitter 17 to perform LVDS serial transmission. The LVDS transmitter 17 samples these signals at each falling cycle of the transfer clock, and converts them into LVDS serial signals by a built-in PLL circuit. Also, it transmits the B image data, the LSYNC signal, and the transfer clock to the LVDS transmitter 18 and performs LVDS serial transmission. Similarly, the LVDS transmitter 18 samples these signals at every falling cycle of the transfer clock, and converts them into LVDS serial signals by a built-in PLL circuit. At this time, the LVDS transmitter 17 and the LVDS
Since the DS characteristics of the DS receiver 22, the LVDS transmitter 18, and the LVDS receiver 23 satisfy certain standard values by the FPD link transmission, all data is guaranteed with respect to the transfer clock.

The LV provided on the image processing unit 20 side
The DS receivers 22 and 23 are the LVDS transmitter 1
The LVDS serial data transferred from 7 and 18 is converted into parallel data. LVDS receivers 22, 23
Has a built-in PLL circuit, automatically generates a strobe signal for detecting an input 7-bit signal at the falling edge of a transfer clock, and converts it into parallel data. That is, the LVDS receiver 22 converts the R and G image data and the LSYNC signal into
To the image data and the LSYNC signal.

The timing generator 24 receives the LSYNC signal from the LVDS receiver 22 and the LSYNC signal and the transfer clock from the LVDS receiver 23. Then, between the LVDS devices (LVDS transmitter 1
7 and between the LVDS receiver 22 and between the LVDS transmitter 18 and the LVDS receiver 23) are determined from the respective LSYNC signals, and WE signals corresponding to those delay times are generated. Note that LV
WE indicates the write timing number corresponding to the delay time generated between the DS transmitter 17 and the LVDS receiver 22.
1. LVDS transmitter 18 and LVDS receiver 2
Let WE2 be a write timing signal corresponding to the delay time occurring between the three.

The FIFO memory 25 receives the R digital image signal and the transfer clock from the LVDS receiver 22, and receives the write timing signal WE1 from the timing generator 24. Then, the write timing signal W
According to the write timing controlled by E1,
Write the R image data.

The FIFO memory 26 receives the G digital image signal and the transfer clock from the LVDS receiver 22, and receives the write timing signal WE1 from the timing generator 24. Then, the write timing signal W
According to the write timing controlled by E1,
Write G image data.

The FIFO memory 27 receives the R digital image signal and the transfer clock from the LVDS receiver 23, and receives the write timing signal WE2 from the timing generator 24. Then, the write timing signal W
According to the write timing controlled by E2, R
Write image data.

The write clock for the FIFO memories 25 and 26 uses the transfer clock from the LVDS transmitter 17, that is, the clock output of the LVDS receiver 22. The write clock of the FIFO memory 27 uses the transfer clock from the LVDS transmitter 18, that is, the clock output of the LVDS receiver 23. As a result, the FIFO memories 25 to 27 have
Each stores a 10-bit digital image signal.

The read timing of the FIFO memories 25 to 27 can be asynchronously performed without depending on the write timing of each FIFO memory.
The phase of the digital image signal of each color B can be surely matched.

In the present embodiment having the above-described configuration, in the LVDS transmission of image data, when two sets of LVDS devices are used to transmit one read image, two sets of LVDS are used.
It is characterized in that the dispersion of the delay time of signal transmission occurring between DS devices is corrected.

In order to achieve this object, the present embodiment provides
Include the same image data synchronization signal in each LVDS transmission line, calculate the delay time from the image data synchronization signal for each LVDS device, and generate a WE signal for controlling the write timing to the FIFO memory It is characterized by.

That is, in the image reading unit 10,
For a system I / F width of 21 bits of the LVDS transmitter 17, a digital image signal of 10 bits (20 bits) for each of RG and an LSYNC signal are input, and the LVDS
Perform serial transmission. Also, LVDS transmitter 1
8 also receives a B digital image signal and an LSYNC signal, and performs LVDS serial transmission.

The image processing unit 20 sends the LSYNC signal extracted by the LVDS receivers 22 and 23 to the timing generation unit 24. The timing generator 24 generates LSYN
A signal delay time generated between the transmission paths is calculated from the C signal, and a write timing signal WE of the FIFO memory corresponding to the delay time is generated. That is, LVDS
A delay time generated between the transmitter 17 and the LVDS receiver 22 is calculated from the LSYNC signal included in the transmission path, and a write timing signal WE1 corresponding to the calculated delay time is created. Also, the delay time generated between the LVDS transmitter 18 and the LVDS receiver 23 is
A write timing signal WE2 calculated from the LSYNC signal included in this transmission path and corresponding to the calculated delay time
Create

The WE1 write timing signal generated by the timing generator 24 is input to FIFO memories 25 and 26, and the WE1 write timing signal is input to the FIFO memories 25 and 26 according to the WE1 write timing.
The IFO memories 25 and 26 take in image data. The WE2 write timing signal is input to the FIFO memory 27, and the FIFO memory 27 captures image data according to the WE2 write timing.

As described above, in the present embodiment, two sets of LVDS
Even if the delay in the signal transmission time between devices varies, by controlling the writing of the FIFO memory with the WE signal generated based on the LSYNC signal included in each transmission path, the digital image signal of each RGB color can be controlled. The phases can be surely matched.

The above-described embodiment is a preferred embodiment of the present invention. However, the present invention is not limited to this, and various modifications can be made without departing from the scope of the present invention. For example, in the above embodiment, the LS generated by the control unit 14 of the image reading unit 10 is used.
Although the YNC signal is included in two sets of LVDS transmission lines,
The transfer clocks of the two sets of LVDS devices may be sent to the timing generation unit 24, and the writing of the FIFO memory may be controlled based on the difference between the delay times of the transfer clocks.

Although the transfer clock generated by the control unit 14 of the image reading unit 10 is used as the write clock to the FIFO memory, a clock generated by the image processing unit 20 may be used. In this case, a clock having a speed equal to or higher than the transfer clock of the LVDS is used.

[0045]

As is clear from the above description, according to the present invention, on the transmitting side, each LVDS transmission line has:
The same image data synchronization signal is included and transmitted to the receiving side,
On the receiving side, a signal delay time generated in each transmission path is calculated by the same image data synchronization signal, and a write timing signal for controlling write timing to a plurality of memories for writing image data is calculated. , The phase of the image data written to the memory can be surely matched.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment according to the present invention.

FIG. 2 is a block diagram illustrating a conventional device configuration.

FIG. 3 is a block diagram illustrating a conventional device configuration.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Image reading device 11 CCD 12 Analog processing part 13 A / D conversion part 14 Control part 17, 18 LVDS transmitter 20 Image processing part 22, 23 LVDS receiver 24 Timing generation part 25, 26, 27 FIFO memory

Claims (1)

[Claims] 1. An image data transfer system for dividing one image data to a plurality of LVDS devices and transferring the divided image data, wherein the transmission side includes the same image data synchronization signal in each LVDS transmission line. Write timing for calculating the signal delay time generated in each transmission path by the same image data synchronization signal on the reception side, and controlling the write timing to a plurality of memories for writing the image data. An image data transfer system, wherein a signal is created based on the calculated signal delay time.