JP2011056883A - Data transfer device, data transfer control method, data transfer control program and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transfer device that appropriately prevents data shift on a reception side by appropriately adjusting skew in terms of synchronous data transmission between a plurality of transmission sides and reception sides and then performing data transmission, and to provide a data transfer control method, a data transfer control program and a recording medium. <P>SOLUTION: In multifunction equipment 1, when transmitting image data which must be transmitted synchronously from a plurality of transfer controllers 7a and 7b to a printing processing part 8, reference signals Ks received by the transfer controllers 7a and 7b is input in the transfer controllers 7b and 7a each other, and transmitted/received as a comparison reference signal Ksh through transfer circuits 30a and 30b and a reference signal transfer path 11, a time difference between the reference signal Ks and the comparison reference signal Ksh is detected, and data transmission timing to the printing processing part 8 is adjusted based on a skew value being the time difference. Even if there is the skew between the printing processing part 8 and the transfer controllers 7a and 7b, transfer of the image data considering the skew is performed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a data transfer device, a data transfer control method, a data transfer control program, and a recording medium, and more particularly, to a composite device, a printer device, and the like that synchronously transfer image data from a plurality of data transfer control units to a printing unit. The present invention relates to a data transfer device, a data transfer control method, a data transfer control program, and a recording medium.

  In image processing apparatuses such as copying apparatuses, printer apparatuses, composite apparatuses, scanner apparatuses, and facsimile apparatuses, it is important to transfer data (image data, etc.) at high speed and appropriately. Image data read from an external storage unit (for example, hard disk, CD-ROM (Compact Disc Read Only Memory), DVD (Digital Video Disk), SD (Secure Digital) card, etc.), input from an external device such as a computer Input image data such as image data is subjected to various image processing, temporarily stored in a RAM (Random Access Memory), a hard disk or other temporary storage memory, and the image data stored in the temporary storage memory is again required for image processing. (Scanner γ correction, filter processing, background removal, color correction, printer γ correction, halftone processing, etc.) Send or subjected to recording output to, or transferred to a computer or the like via the network, it performs various output processing such as subjecting the facsimile transmission.

  In recent years, image processing apparatuses such as composite devices and printers have been required to realize high-speed data communication in data communication between an image processing chip such as an ASIC (Application Specific Integrated Circuit) and a memory. And PCI (Peripheral Component Interconnect) Express (hereinafter referred to as PCIe), which is a split transaction bus that performs high-speed transfer that can issue the next request without waiting for the response. Yes. In a high-speed serial bus such as PCIe, a packet transfer error due to bit corruption occurs with a specific probability. In the case of PCIe, according to the PCIe standard, when a packet transfer error due to bit corruption occurs, retransmission (retry) is performed to guarantee data.

  On the other hand, in copy processing, transfer processing, and the like, it is necessary to complete transfer processing of input image data within a predetermined processing time. If this processing time is exceeded, data communication cannot be performed properly. For example, when reading of an image of a document is started by the scanner unit, read data is input from the scanner unit at a preset speed. Therefore, the input image data is shortened by a predetermined length so as to be in time for reading by the scanner unit. You need to send data at time intervals. That is, there is a restriction of synchronous transfer that a certain amount of data must be transferred in a predetermined short cycle.

  Conventionally, a common reference signal is distributed to each chip on the data transmission side and data reception side, and a synchronization signal is output as a training pattern for each predetermined cycle of the reference signal, so that logical synchronization between the transmission side and the reception side is performed. The technique which takes is proposed (refer patent document 1).

  Conventionally, a technique has been proposed in which a test pattern is transmitted to the receiving side, the slowest delay time in each bit of the bus is detected and confirmed, and output data is transmitted in accordance with the slowest delay time (Patent Document) 2).

  Further, when print data is transmitted from a plurality of data transfer sides to one print unit (data reception side), for example, CMYK is transmitted from one transmission side to one print unit, and other color signals P1, When P2 or the like is transmitted from the other transmission side to the same printing unit, since it is print data for printing one image, it is necessary for the two transmission sides to transmit print data to the printing unit in synchronization.

  However, in the above-described prior art, the timing shift in the case of transmitting related data from a plurality of transmitting sides to one receiving side in synchronization cannot be properly eliminated and needs to be improved. .

  That is, when data that needs to be synchronized from a plurality of transmission sides is transmitted to the reception side, a delay difference (skew) is caused by a wiring length, variation, etc. in a data communication path for transmitting data from the plurality of transmission sides to the reception side. Arise.

  However, in the conventional technique described in Patent Document 1, since the synchronization signal is output as a training pattern to the transmission side and the reception side for synchronization, the synchronization signal is transmitted to a plurality of transmission sides using this conventional technique. When there is a skew in the distributed synchronization signal itself, the synchronization signal includes a shift, and the skew of the data itself output from the transmission side cannot be corrected. There was a need.

  In the prior art described in Patent Document 2, a test pattern is transmitted to the receiving side, the latest delay time in each bit of the bus is detected and confirmed, and output data is transmitted in accordance with the latest delay time. For this reason, if the test pattern itself includes a skew, the skew correction cannot be performed properly, and improvement is required.

  Therefore, the present invention performs data transmission by appropriately adjusting a skew in simultaneous data transmission between a plurality of transmission sides and a reception side, and data transfer capable of appropriately preventing data deviation on the reception side An object is to provide an apparatus, a data transfer control method, a data transfer control program, and a recording medium.

  In order to achieve the above-mentioned object, the present invention enables each transmission side to transmit data that needs to be transmitted synchronously from a plurality of transmission sides to a reception side that transmits the synchronization signal for synchronization. The received synchronization signals are mutually transmitted and received as a comparison synchronization signal, a time difference between the synchronization signal and the comparison synchronization signal is detected, and a data transmission timing to the receiving side is adjusted based on the time difference.

  According to the present invention, data transmission can be performed by appropriately adjusting a skew in data transmission in synchronization between a plurality of transmission sides and reception sides, and a data shift on the reception side can be appropriately performed. Can be prevented.

The principal part block block diagram of the compound apparatus to which one Example of this invention is applied. FIG. 3 is a configuration diagram of a print processing unit and a transfer control unit when the number of processing data of the print processing unit is the same as the output channel of the transfer control unit. The principal part block block diagram of a compound apparatus. The figure which shows the relationship of the reference signal about the image data between a printing process part and a transfer control part. The figure which shows transfer of the reference signal between transfer control parts. The figure which shows transfer of the reference signal between transfer control parts. The circuit diagram of a skew measurement circuit. The figure which shows the reference signal input / transfer circuit of a transfer control part. The circuit diagram of the transfer control part containing a delay circuit. The circuit diagram of a delay circuit. The figure which shows the clock in each part of a transfer control part, a reference signal, and a comparison reference signal. The figure which shows the clock in each part of the transfer control part in case a skew difference is small, a reference signal, and a comparison reference signal. The circuit diagram of the skew measurement circuit of 2nd Example. The circuit diagram of the delay circuit of the 2nd example. The figure which shows the clock in each part of the transfer control part of 2nd Example, a reference signal, and a comparison reference signal. The circuit diagram of the skew measurement circuit of 3rd Example. The figure which shows the clock in each part of the transfer control part in case a comparison reference signal is large, a reference signal, and a comparison reference signal. The figure which shows the clock in each part of the transfer control part of 3rd Example, a reference signal, and a comparison reference signal. The block diagram of the transfer control part of 4th Example. The block diagram of a skew determination circuit. The principal part block diagram of the transfer control part of 5th Example. The principal part block diagram of the transfer control part of 6th Example. The block diagram of a skew measurement circuit.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, since the Example described below is a suitable Example of this invention, various technically preferable restrictions are attached | subjected, However, The range of this invention is unduly limited by the following description. However, not all the configurations described in the present embodiment are essential constituent elements of the present invention.

  1 to 12 are diagrams showing a first embodiment of a data transfer device, a data transfer control method, a data transfer control program, and a recording medium according to the present invention. FIG. 1 shows the data transfer device, data transfer according to the present invention. It is a principal block block diagram of the composite apparatus 1 to which the first embodiment of the control method, the data transfer control program, and the recording medium is applied.

  In FIG. 1, the composite apparatus 1 includes an image input unit 2, an image processing unit 3, a memory control / controller unit 4, a memory 5, a CPU (Central Processing Unit) 6, a transfer control unit 7, a printing unit 8, and the like. The above units are connected by a general-purpose bus 9. The composite apparatus 1 includes a so-called copy function such as image reading, recording output, and transmission / reception, a fax function, a printer function, a scanner function, and the like.

  The image input unit 2 is a scanner unit that reads an image of a document and outputs digital image data, a network interface that receives image data from a computer or the like via a network, and the like. Output to.

  The image processing unit 3 includes, for example, an image processing ASIC (Application Specific Integrated Circuit) and the like, and includes an interface that receives digital image data from the image input unit 2. The image processing unit 3 performs various types of image processing on the digital image data from the image input unit 2, for example, correction processing or shading of signal degradation when reading document image data when the image input unit 2 is a scanner. Correction, scanner γ correction, MTF correction, and the like are performed.

  A memory 5 is connected to the memory control / controller unit 4. The memory control / controller unit 4 controls the flow of image data under the control of the CPU 6, and writes image data into the memory 5 and the memory. The reading of image data from 5 is controlled.

  Further, the memory control / controller unit 4 converts the image data such as RGB input from the image input unit 2 into print data such as CMYK data for printing, and stores the converted image data in the memory 5. .

  The memory 5 includes a hard disk, an SSD (Solid State Drive), a backed up RAM (Random Access Memory), and the like, and image data and the like are written and read under the control of the memory control / controller unit 4. The memory 5 may store a program of the composite apparatus 1 and the like.

  The CPU 6 functions as the composite device 1 by controlling each part of the composite device 1 while using the memory 5 or the RAM (not shown) as a work memory based on a program stored in the memory 5 or a ROM (not shown). And the image data transfer control process of the present invention is executed.

  A print processing unit 8 is connected to the transfer control unit 7, and each of the transfer control unit 7 and the print processing unit 8 is configured by a semiconductor chip, for example, an ASIC.

  The print processing unit (reception unit) 8 is mounted on a printing unit (not shown) that forms an image on a sheet in line units or page units, and controls the printing unit based on image data transferred from the transfer control unit 7. Print the image. The print processing unit 8 outputs the reference signal Sk to the transfer control unit 7 in order to appropriately receive the image data transfer from the transfer control unit 7.

  The transfer control unit 7 adjusts the transfer timing based on the reference signal Sk from the print processing unit 8 and transfers the image data for printing in the memory 5 to the print processing unit 8.

  Normally, the transfer control unit 7 and the print processing unit 8 transfer control when four DMACs are mounted and the number of output channels is four and the print processing capability of the print processing unit 8 is four-color printing. As shown in FIG. 2, the unit 7 has a one-to-one ASIC count. In this case, the transfer control unit 7 determines the CMYK format based on the reference signal Sk from the print processing unit 8. The four colors of image data can be appropriately transferred to the print processing unit 8.

  However, in the composite apparatus 1 of this embodiment, the print processing capability of the print processing unit 8 exceeds the number of colors that is the number of output channels of one transfer control unit 7, for example, as shown in FIG. In addition, it has a print processing capability for six-color printing with P1 and P2 colors added.

  Therefore, as shown in FIG. 3, the transfer control unit 7 of the present embodiment is equipped with two transfer control units (transmission means) 7a and 7b. The transfer control unit 7a and the transfer control unit 7b are provided by an ASIC. It is configured. In FIG. 3, the transfer control units 7 a and 7 b split the PCI (Peripheral Component Interconnect) Express (hereinafter referred to as PCIe) that can issue the next request without waiting for the response. A case is shown in which the transaction bus chip set 10 is connected to the memory control / controller 4, the memory 5, and the CPU 6.

  Then, the transfer of the image data from the transfer control units 7a and 7b to the print processing unit 8 is performed by transferring the reference signal (synchronization signal) Ks from the print processing unit 8 to each of the transfer control unit 7a and the transfer control as shown in FIG. The transfer control unit 7a and the transfer control unit 7b transfer the image data for printing in synchronization with the reference signal Ks.

  The reference signal Ks is transmitted from the print processing unit 8 to the two transfer control units 7a and 7b, but the print data output by the transfer control unit 7a and the transfer control unit 7b due to the delay difference (skew) in the transmission path of the reference signal Ks. There is a risk that the print quality will deteriorate.

  Therefore, as shown in FIGS. 5 and 6, the composite apparatus 1 according to the present embodiment transfers the reference signal Ks input to the transfer control units 7a and 7b to the other transfer control units 7a and 7b. 11 is transferred between the transfer control units 7a and 7b and the reference signal Ks input to the other. In FIG. 5 and FIG. 6, the internal connection lines are omitted for easy understanding. That is, when the reference signal Ks is input from the print processing unit 8 to the transfer control unit 7a and the transfer control unit 7b, the reference signal Ks input to the transfer control unit 7b is used as the reference signal transfer path 11 as shown in FIG. Is transferred to the transfer control unit 7a and input as a comparison reference signal (comparison synchronization signal) Ksh. As shown in FIG. 6, the reference signal Ks input to the transfer control unit 7b is used as a reference signal transfer path. 11 to the transfer control unit 7a and input as a comparison reference signal Ksh.

  Each of the transfer control unit 7a and the transfer control unit 7b includes skew measurement circuits (time difference detection means) 20a and 20b for measuring a delay difference (skew) between the reference signal Ks and the comparison reference signal Ksh, and measures skew. As shown in FIG. 7, the circuits 20a and 20b include OR circuits 21a and 21b and counters 22a and 22b. The OR circuit 21a, 21b receives the reference signal Ks sent directly from the print processing unit 8 and the comparison reference signal Ksh transferred from the other transfer control unit 7a, 7b, and receives the reference signal Ks and the comparison reference. The OR output of the signal Ksh is output to the counters 22a and 22b. That is, when either the reference signal Ks or the comparison reference signal Ksh is input, the OR circuits 21a and 21b output the detection signal to the counters 22a and 22b.

  In addition to the detection signals from the OR circuits 21a and 21b, a clock (internal clock) CLK is input to the counters 22a and 22b. When the detection signals are input to the counters 22a and 22b from the OR circuits 21a and 21b, Counting of the clock CLK is started as a skew, and when a detection signal is next input from the OR circuits 21a and 21b, the counting is terminated and the count value is held as a skew value.

  As shown in FIG. 8, the transfer control unit 7a and the transfer control unit 7b include reference signal input / transfer circuits 30a and 30b, and the reference signal input / transfer circuits 30a and 30b include a reference signal input buffer 31a. 31b, reference signal buffers 32a and 32b, internal buffers 33a and 33b, comparison signal buffers 34a and 34b, input / output buffers 35a and 35b, and the like. The reference signal input buffers 31a and 31b are connected to a reference signal signal line from the print processing unit 8, and their outputs are connected to the reference signal buffers 32a and 32b. The outputs of the reference signal buffers 32a and 32b are connected to one side input terminals of the OR circuits 21a and 21b of the skew measurement circuits 20a and 20b, and are connected to the internal buffers 33a and 33b. The output of 33b is connected to comparison signal buffers 34a and 34b and input / output buffers 35a and 35b. The comparison signal buffers 34a and 34b are connected to the internal buffers 33a and 33b at the inputs thereof, and are connected to input / output buffers 35a and 35b. The outputs of the comparison signal buffers 34a and 34b are skew measurement circuits. The other side input terminals of the OR circuits 21a and 21b of 20a and 20b are connected. The input / output buffers 35a and 35b are mutually connected by the reference signal transfer path 11, and the reference signal Ks from the internal buffers 33a and 33b is mutually transmitted to the counterpart input / output buffers 35a and 35b through the reference signal transfer path 11. The comparison reference signal Ksh is transmitted, and the comparison reference signal Ksh sent from the counterpart input / output buffers 35a and 35b is output to the comparison signal buffers 34a and 34b.

  That is, when the reference signal Ks is directly input from the print processing unit 8 to the reference signal input buffers 31a and 31b, the reference signal input / transfer circuits 30a and 30b receive the skew measurement circuit 20a via the reference signal buffers 32a and 32b. 20b, the reference signal Ks is input to one input terminal of the OR circuits 21a and 21b and sent to the input / output buffers 35a and 35b via the internal buffers 33a and 33b. The comparison reference signal is output from the input / output buffers 35a and 35b. The data is transferred as Ksh to the input / output buffers 35a and 35b of the other transfer control units 7a and 7b via the reference signal transfer path 11. When the reference signal Ksh is input to the input / output buffers 35a and 35b, the reference signal input / transfer circuits 30a and 30b are input to the other input terminals of the OR circuits 21a and 21b via the comparison signal buffers 34a and 34b. Let The reference signal input / transfer circuits 30a and 30b and the reference signal transfer path 11 function as signal receiving means, transfer means, and transfer signal receiving means.

  Further, as shown in FIG. 8, the counters 22a and 22b of the skew measurement circuits 20a and 20b are connected to the CPU 6, and the CPU 6 acquires the skew values that are the counter values of the counters 22a and 22b and transfers them. It controls the transfer timing of the image data from the control units 7a and 7b. The counter values of the counters 22a and 22b are held for a predetermined time and cleared to 0 by a specific signal (for example, a reset signal and a hold clear signal) not shown.

  As shown in FIG. 9, the transfer control units 7a and 7b are equipped with delay circuits 40a and 40b, respectively, and the delay circuits 40a and 40b adjust the output timing of the image data.

  As shown in FIG. 10, the delay circuits 40a and 40b are a plurality (five in FIG. 10) of shift registers 41 to 45 for delaying image data, the image data output from the shift registers 41 to 45, and A selector 46 or the like for inputting image data to be input to the leading shift register 41 is provided, and a selection signal is input to the selector 46 from the CPU 6. The clock CLK is input to the shift registers 41 to 45, and the shift registers 41 to 45 output the input image data to the shift registers 42 to 45 and the selector 46 at the subsequent stage in synchronization with the clock CLK. The selector 46 transmits the undelayed image data and the image data selected from the delayed image data by the shift registers 41 to 45 to the print processing unit 8 based on the selection signal from the CPU 6. The shift amounts of the shift registers 41 to 45 are set according to the number of flip-flops. Therefore, the delay circuits 40a and 40b and the CPU 6 function as output adjustment means as a whole.

  Next, the operation of this embodiment will be described. The composite apparatus 1 according to the present embodiment transfers image data with appropriate synchronization when transferring image data requiring synchronization from the two transfer control units 7a and 7b to the print processing unit 8.

  That is, the composite apparatus 1 performs color image data input from the image input unit 2 with the image processing unit 3 and then converts it into image data for printing (CMYK, etc.) with the memory control / controller 4. Then, the data is stored in the memory 5, read from the memory 5, and transferred to the transfer control units 7 a and 7 b of the transfer control unit 7.

  The transfer control units 7a and 7b transfer the print image data transferred from the memory 5 to the print processing unit 8. At this time, the transfer control units 7a and 7b are synchronized with the reference signal Ks sent from the print processing unit 8. Transfer image data. However, if there is a transmission time difference (skew) between the transmission path for transmitting the reference signal Ks from the print processing unit 8 to the transfer control unit 7a and the transmission path for transmitting the reference signal Ks from the print processing unit 8 to the transfer control unit 7b. A time difference occurs in the image data transmitted from the transfer control unit 7a and the transfer control unit 7b to the print processing unit 8, and the image quality deteriorates.

  Therefore, in this embodiment, the reference signal Ks transmitted from the print processing unit 8 to each transfer control unit 7a, 7b is transferred as a comparison reference signal Ksh to the other transfer control unit 7a, 7b, and each transfer control unit 7a and 7b measure the time difference between the reference signal Ks and the comparison reference signal Ksh by the skew measurement circuits 20a and 20b. Based on the measured time difference (skew), the transfer control units 7a and 7b transfer to the print processing unit 8. The timing of the image data to be transmitted is adjusted by the delay circuits 40a and 40b under the control of the CPU 6.

  That is, as illustrated in FIG. 5, the transfer control unit 7 a inputs the reference signal Ks transmitted from the print processing unit 8 to the skew measurement circuit 20 a and transfers the other through the reference signal transfer path 11. The transfer control unit 7b transfers the reference signal Ks transmitted from the print processing unit 8 to the skew measurement circuit 20b as shown in FIG. 6. At the same time, it is transferred as a comparison reference signal Ksh to the other transfer control unit 7a via the reference signal transfer path 11. At this time, as shown in FIG. 8, the transfer control unit 7a and the transfer control unit 7b skew the reference signal Ks transmitted from the print processing unit 8 via the reference signal input / transfer circuits 30a and 30b. While inputting to measurement circuit 20a, 20b, it transfers to the other transfer control part 7a, 7b.

  The signal waveforms in the transfer control units 7a and 7b of the reference signal Ks and the comparison reference signal Ksh are shown as in FIG. 11, and in FIG. 11, the top stage is the waveform of the clock CLK, and Ks1a and Ks1b are This is a signal waveform when the reference signal Ks is input to the reference signal input buffers 31a and 31b of the reference signal input / transfer circuits 30a and 30b. Note that the reference signal Ks used in the present embodiment is a signal that becomes Hi only for a predetermined period (in FIG. 1, between 5 clocks CLK). FIG. 11 shows that a skew of (Ks1a−Ks1b) has occurred on the transmission path for transmitting the reference signal Ks from the print processing unit 8 to the transfer control unit 7a and the transfer control unit 7b.

  In FIG. 11, Ks2a and Ks2b are signal waveforms when the reference signal Ks is input to the OR circuits 21a and 21b of the skew measurement circuits 20a and 20b, and the reference signal input / transfer circuit 30a of the transfer control units 7a and 7b. , 30b, a predetermined time elapses after being input to the OR circuit 21a, 21b of the skew measuring circuits 20a, 20b after being input to the reference signal input buffers 31a, 31b.

  Furthermore, in FIG. 11, Ks3a and Ks3b are the comparison reference signals Ksh transferred from the other transfer control units 7a and 7b to the OR measurement circuits 21a and 21b of the transfer control units 7a and 7b. A time difference indicated by Tab between the reference signal Ks directly transmitted from the print processing unit 8 and the comparison reference signal Ksh transferred from the other transfer control units 7a and 7b. Has occurred.

  In FIG. 11, ORa is an OR output waveform of the reference signal Ks output from the OR circuit 21a of the transfer control unit 7a to the counter 22a and the comparison reference signal Ksh. In FIG. The counter 22a counts this period. ORb is an OR output waveform of the reference signal Ks and the comparison reference signal Ksh output from the OR circuit 21b of the transfer control unit 7b to the counter 22b. In FIG. 11, the output is Hi only for 7 clocks CLK. The counter 22b counts this period.

  As described above, the reference signal Ks and the comparison reference signal Ksh are signals that become Hi for a predetermined time, and the counters 22a and 22b are ORed between the reference signal Ks input from the OR circuits 21a and 21b and the comparison reference signal Ksh. The period during which the output signal is Hi is counted. As described above, the counter 22a of the transfer control unit 7a counts 9 clocks CLK, and the counter 22b of the transfer control unit 7b counts 7 clocks CLK.

  That is, in the transmission of the reference signal Ks and the comparison reference signal Ksh, the delay difference between the path for transmitting the reference signal KS directly from the print processing unit 8 to the transfer control unit 7a and the path for transmitting to the transfer control unit 7b becomes a skew, Since the path for transmitting the comparison reference signal Ksh between the transfer control unit 7a and the transfer control unit 7b transmits the same signal system, there is no delay difference.

  The OR output of Hi from the OR circuits 21a and 21b starts with the reference signal Ks or the comparison reference signal Ksh that changes quickly from Low to Hi, and ends with the reference signal Ks or the comparison reference signal Ksh that changes slowly from Hi to Low. To do.

  Therefore, the Hi period of the OR output of the OR circuits 21a and 21b of the transfer control units 7a and 7b having the smaller delay from the print processing unit 8 to the transfer control units 7a and 7b becomes longer, and the transfer control unit having the larger delay. The Hi period of the OR output of the OR circuits 21a and 21b of 7a and 7b is shortened. The timing difference at which the OR output of the OR circuits 21a and 21b of the two transfer control units 7a and 7b changes from Low to Hi becomes a skew in the data transfer of the transfer control units 7a and 7b. Since the timing difference that changes from Hi to Low of the output becomes the skew in the data transfer of the transfer control units 7a and 7b, the difference in the change of the OR circuits 21a and 21b includes a double skew difference. Become.

  Therefore, the difference between the count values of the counters 22a and 22b of the respective transfer control units 7a and 7b, in the case of FIG. 11, 9 clock CLK-7 clock CLK = 2 half of the clock CLK, that is, 1 clock CLK is the reference signal. Ks skew.

  Further, as a case where the difference in skew of the reference signal Ks is small, there is a case as shown in FIG. 12, and in the case of FIG. 12, the difference between the count values of the counters 22a and 22b of the transfer control units 7a and 7b When 7clk-6clk = 1clk, the skew of the reference signal Ks is 1 / 2clk.

  In the skew measurement in this case, since the reference signal transfer path 11 transferred via the other transfer control units 7a and 7b is the same, it cannot be measured simultaneously.

  Therefore, measurement is required twice, and the measurement counts the result of the OR processing of the OR circuits 21a and 21b. Therefore, even if the interval for measuring twice is different, it can be appropriately measured.

  In the skew measurement process, the CPU 6 reads the count values held in the counters 22a and 22b, and the timing of receiving the reference signal Ks is late depending on which of the two read count values is smaller. Determine if it is fast. The CPU 6 can know whether the skew value and the reception timing of the reference signals of the transfer control units 7a and 7b are early or late, and an image to be transmitted to the print processing unit 8 in order to correct the skew by the reference signal Ks. Adjust the timing difference of data.

  The CPU 6 outputs a selection signal for eliminating this timing shift to the selectors 46 of the delay circuits 40a and 40b, and sets the delay amounts of the delay circuits 40a and 40b.

  That is, of the transfer control units 7a and 7b, the CPU 6 has a transfer control unit 7a or 7b that has received the reference signal Ks earlier than the transfer control unit 7a or 7b that has received the reference signal Ks later. A selection signal serving as a delay amount for delaying the image data transmission timing by the skew value is output.

  For example, in the case of FIG. 11, since the skew value is 1 clock CLK, the delay amount is set to the earlier transfer control unit 7a by 1 clock CLK, and the delay amount is set to the later transfer control unit 7b. Is set to 0. That is, the CPU 6 first causes the delay circuit 40a of the transfer control unit 7a to select the output image data of the shift register 41 by the selector 46 and output it to the print processing unit 8, and the delay circuit 40b of the transfer control unit 7b to the delay circuit 40b. Then, the image data input to the first shift register 41 is selected by the selector 46 and output to the print processing unit 8.

  Also, as shown in FIG. 12, when the waveform skew value is 1/2, the delay setting 0 is set so that there is no skew at the clock cycle level, so both the transfer control units 7a and 7b are set to delay 0. To output image data.

  As described above, the multifunction apparatus 1 according to the present embodiment transmits the data that needs to be transmitted in synchronization to the print processing unit 8 that transmits the synchronization reference signal Ks from the plurality of transfer control units 7a and 7b. When transmitting image data, the reference signal Ks received by each transfer control unit 7a, 7b is mutually transmitted and received as a comparison reference signal Ksh by the reference signal input / transfer circuits 30a, 30b and the reference signal transfer path 11, The time difference between the reference signal Ks and the comparison reference signal Ksh is detected, and the data transmission timing to the print processing unit 8 is adjusted based on the skew value that is the time difference.

  Therefore, even when the reference signal Ks transmitted from the print processing unit 8 to each of the transfer control units 7a and 7b has a skew, the skew can be obtained and image data can be transferred in consideration of the skew. It is possible to prevent the received image data from being shifted in the processing unit 8 and improve the printing performance.

  In the composite apparatus 1 of this embodiment, the CPU 6 adjusts the delays of the delay circuits 40a and 40b based on the skews measured by the skew measurement circuits 20a and 20b of the transfer control units 7a and 7b.

  Accordingly, the transfer control units 7a and 7b can be unified in a simple configuration, and the print processing unit 8 can be prevented from shifting received image data at low cost, thereby improving the printing performance.

  13 to 15 are diagrams showing a second embodiment of the present invention, and FIG. 13 is a circuit block diagram of a skew measuring circuit of a composite apparatus to which the second embodiment of the present invention is applied.

  The present embodiment is applied to a composite apparatus similar to the composite apparatus 1 of the first embodiment. In the description of the present embodiment, the same reference numerals are used for the same components as in the first embodiment. In addition, the same components as those not shown will be described using the same reference numerals used in the description of the first embodiment.

  In this embodiment, it is possible to correct even a skew of a half cycle of the clock CLK.

  Therefore, in the composite apparatus 1 of this embodiment, the skew measuring circuits 50a and 50b shown in FIG. 13 and the delay circuits 60a and 60b shown in FIG. 14 are mounted on the transfer control unit 7a and the transfer control unit 7b, respectively.

  In FIG. 13, the skew measurement circuit 50a is mounted on the transfer control unit 7a, and the skew measurement circuit 50b is mounted on the transfer control unit 7b.

  The skew measurement circuits 50a and 50b include OR circuits 51a and 51b, counters 52a and 52b, counters 53a and 53b, holding circuits 54a and 54b, and selectors 55a and 55b. The clocks CLK are supplied to the counters 52a and 52b. The inverted clock CLK is input to the counters 53a and 53b via the inverting circuits 56a and 56b.

  As in the case of the first embodiment, the OR circuits 51a and 51b receive the reference signal Ks sent directly from the print processing unit 8 and the comparison reference signal sent via the other transfer control units 7a and 7b. Ksh is input, and OR outputs of the reference signal Ks and the comparison reference signal Ksh are output to the counters 52a and 52b and the counters 53a and 53b.

  The counters 52a and 52b count the period when the OR output from the OR circuits 51a and 51b is Hi by the clock CLK, and output the count result to the selectors 55a and 55b and the holding circuits 54a and 54b.

  The counters 53a and 53b count the period when the OR output from the OR circuits 51a and 51b is Hi by the inverted clock CLK, and output the count result to the holding circuits 54a and 54b.

  The holding circuits 54a and 54b hold the count value when the counters 52a and 52b count the period when the OR output is Hi by the clock CLK, and the count values when the counters 53a and 53b count the period when the OR output is Hi by the clock CLK. Then, the data is output to the selectors 55a and 55b.

  The selectors 55 a and 55 b selectively output the count values of the counters 52 a and 52 b and the counter values held by the holding circuits 54 a and 54 b to the CPU 6 in accordance with the selector signal from the CPU 6.

  The CPU 6 determines the skew based on the counter values of the counters 52a and 52b and the counter values held by the holding circuits 54a and 54b, and controls the delay circuits 60a and 60b.

  As shown in FIG. 14, the delay circuits 60a and 60b have a plurality (10 in FIG. 14) of shift registers 61a to 70a, 61b to 70b and selectors 71a and 71b whose shift amounts are set according to the number of flip-flops. The shift registers 61a to 65a and 61b to 65b receive the clock CLK, and the shift registers 66a to 70a and 66b to 70b receive the inverted clock CLK inverted by the inversion circuits 72a and 72b.

  The image data to be transferred is input to the shift registers 61a and 61b and the shift registers 66a and 66b, and the undelayed image data input to the shift registers 61a and 61b and the shift registers 66a and 66b is input to the selectors 71a and 71b. Is also entered. The shift registers 61a to 64a and 61b to 64b shift the image data input from the previous stage to the subsequent stage based on the clock CLK, and also output it to the selectors 71a and 71b. The shift registers 65a and 65b in the last stage are output. Shifts the image data input from the preceding shift registers 64a and 64b based on the clock CLK and outputs them to the selectors 71a and 71b.

  The shift registers 65a to 70a and 65b to 70b shift the image data input from the preceding stage to the subsequent stage based on the inverted clock CLK and output the shifted image data to the selectors 71a and 71b. 70b shifts the image data input from the preceding shift registers 69a and 69b based on the inverted clock CLK and outputs the shifted image data to the selectors 71a and 71b.

  The selectors 71 a and 71 b select undelayed image data and the image data delayed by the shift registers 61 a to 70 a and 61 b to 70 b based on the selection signal from the CPU 6, and transmit them to the print processing unit 8.

  That is, in the composite apparatus 1 of this embodiment, as shown in FIG. 15, the clock CLK, the reference signal, and the comparison reference signal in each part of the transfer control units 7a and 7b are the same as those in the first embodiment. As indicated by ORa, when the OR output period of Hi of the OR circuit 51a that the counter 52a of the transfer control unit 7a counts with the clock CLK is indicated as a normal rotation count, when the clock is 7 clocks CLK, The counter value of the counter 53a that counts the Hi OR output period of the circuit 51a is 8 clocks CLK as shown as an inverted count. Further, as indicated by ORb, when the OR output period of Hi of the OR circuit 51b that the counter 52b of the transfer control unit 7b counts with the clock CLK is indicated as normal count, when the clock is 7 clock CLK, the inverted clock CLK Thus, the counter value of the counter 53b that counts the OR output period of Hi of the OR circuit 51b is 6 clocks CLK as shown as an inversion count.

  Accordingly, when the skew is calculated for the normal clock CLK and the inverted clock CLK by the CPU 6, the skew value in the normal clock CLK becomes 7 from 7clk-7clk = 0, and the skew in the inverted clock CLK. Since the value is 8clk-6clk = 2 and the skew is ½, the value is 1. Then, the CPU 6 sets, as the skew value, the larger skew value of the skew value of the normal clock CLK and the skew value of the inverted clock CLK. In the above case, a skew of 1 clk is set by the inverted clock CLK.

  Then, the composite apparatus 1 sets the delay circuits 6a and 60b shown in FIG. 14 based on the forward clock CLK and the inverted clock CLK, and sets the delay circuits 60a and 60b of the earlier transfer control units 7a and 7b. The selectors 71 a and 71 b select the image data with the calculated skew (for example, 1 clock CLK) and transmit it to the print processing unit 8.

  As described above, the composite apparatus 1 according to the present embodiment measures the time difference between the reference signal Ks and the comparison reference signal Ksh using the clock CLK and the inverted clock CLK, and measures the time difference with double accuracy.

  Therefore, the skew adjustment of the image data transferred from the transfer control units 7a and 7b to the print processing unit 8 can be adjusted in a cycle that is half the frequency of the clock CLK that is the operating frequency, and the skew adjustment is performed with higher accuracy. Thus, the printing performance can be further improved.

  16 to 18 are diagrams showing a third embodiment of the present invention, and FIG. 16 is a circuit block diagram of a skew measuring circuit of a composite apparatus to which the third embodiment of the present invention is applied.

  The present embodiment is applied to a composite apparatus similar to the composite apparatus 1 of the first embodiment. In the description of the present embodiment, the same reference numerals are used for the same components as in the first embodiment. In addition, the same components as those not shown will be described using the same reference numerals used in the description of the first embodiment.

  In the present embodiment, even when the comparison reference signal Ksh has a large delay in the reference signal transfer path 11 and the reference signal Ks changes from Hi to Low and then the comparison reference signal Ksh is input to the OR circuit, The skew value is obtained and the delay is controlled.

  Therefore, the composite apparatus 1 according to the present embodiment includes the skew measurement circuits 70a and 70b illustrated in FIG. 16 in the transfer control unit 7a and the transfer control unit 7b, respectively.

  In FIG. 16, the skew measurement circuit 70a is mounted on the transfer control unit 7a, and the skew measurement circuit 70b is mounted on the transfer control unit 7b.

  The skew measurement circuits 70a and 70b include OR circuits 81a and 81b, OR circuits 82a and 82b, AND circuits 83a and 83b, AND circuits 84a and 84b, shift registers 85a and 85b, shift registers 86a and 86b, inverting circuits 87a and 87b, and Counters 88a and 88b are provided, and a clock CLK is input to the shift registers 85a and 85b and the shift registers 86a and 86b.

  As in the first embodiment, the OR circuits 81a and 81b receive the reference signal Ks sent directly from the print processing unit 8 and the feedback of the outputs of the shift registers 85a and 85b, and the OR output is an AND circuit. Output to 83a and 83b. The OR circuits 82a and 82b receive the comparison reference signal Ksh sent through the other transfer control units 7a and 7b as an inverted signal, and receive feedback from the outputs of the shift registers 86a and 86b. The OR output is output to the AND circuits 84a and 84b.

  Further, the Hi “1” fixed signal and the outputs of the inverting circuits 87a and 87b are input to the AND circuits 83a and 83b, and these AND outputs are output to the counters 88a and 88b via the shift registers 85a and 85b. Feedback is provided to the ORs 81a and 81b via the shift registers 85a and 85b.

  Further, a Hi “1” fixed signal and a clear signal that becomes “0” at a predetermined timing are input to the AND circuits 84a and 84b, and these AND outputs are passed through the shift registers 86a and 86b and the inverting circuits 87a and 87b. While outputting to AND circuit 83a, 83b, it is made to feed back to OR82a, 82b via shift register 86a, 86b.

  The counters 88a and 88b count the AND output periods of the Hi AND circuits 83a and 83b from the shift registers 85a and 85b with the clock CLK.

  That is, as shown in FIG. 17, in the composite apparatus 1 of this embodiment, the clock CLK, the reference signal, and the comparison reference signal in each part of the transfer control units 7a and 7b are the same as those in the first embodiment. As indicated by ORa, the delay amount between the reference signal Ks and the comparison reference signal Ksh, that is, the difference delay amount by which the comparison reference signal Ksh is sent through the reference signal transfer path 11 is the reference signal Ks is “1”. When longer than a certain period, in the case of the first embodiment and the second embodiment, the reference signal Ks is inputted with the comparison reference signal Ksh after the output of the OR circuit 21a once falls from Hi to Low. Although it becomes Hi again, in the case of the first and second embodiments, the low period TL cannot be counted by the counter 22a or the like, and an accurate skew value cannot be calculated. . That is, in the case of the first and second embodiments, the white circle portion of ORa in FIG. 17 is counted by the counter 22a or the like, and therefore it cannot be counted in the low portion.

  However, as shown in FIG. 18, the skew measurement circuits 80a and 80b according to the present embodiment can input an ORa to the counters 88a and 88b as a corrected ORa to calculate an accurate skew value.

  That is, when the reference signal Ks is input to the OR circuits 81a and 81b, the skew measurement circuits 80a and 80b receive the Hi AND output from the AND circuits 83a and 83b via the shift registers 85a and 85b. As shown in FIG. 18 as the modified ORa, the data is output to the counters 88a and 88b, and the counters 88a and 88b start counting during the Hi period, and the AND output of this Hi is output to the OR circuit 81a via the embodiments 85a and 85b. , 81b, and the input to the counters 88a, 88b is kept Hi.

  Thereafter, when the comparison reference signal Ksh is input to the OR circuits 82a and 82b, and the comparison reference signal Ksh is changed from Hi to Low, the AND circuits 84a and 84b change the shift registers 86a and 86b and the inverting circuits 87a and 87b. Are input to the AND circuits 83a and 83b as a Low signal, and the modified ORa signal is set to Low.

  The counters 88a and 88b use the clock CLK to count the period during which the modified ORa signal is Hi, so that the period indicated by the black circle in FIG. 18 can be counted, and the comparison reference signal Ksh is delayed in the reference signal transfer path 11. When the comparison reference signal Ksh is input to the OR circuit after the reference signal Ks has changed from Hi to Low, the skew value is appropriately obtained and the delay control is performed.

  As described above, in the composite apparatus 1 of this embodiment, the comparison reference signal Ksh has a large delay in the reference signal transfer path 11, and after the reference signal Ks changes from Hi to Low, the comparison reference signal Ksh is input to the OR circuit. Even in such a case, it is possible to appropriately obtain the skew value and control the delay.

  19 and 20 are diagrams illustrating a fourth embodiment of the present invention, and FIG. 19 is a circuit block diagram of a transfer control unit of a composite apparatus to which the fourth embodiment of the present invention is applied.

  The present embodiment is applied to a composite apparatus similar to the composite apparatus 1 of the first embodiment. In the description of the present embodiment, the same reference numerals are used for the same components as in the first embodiment. In addition, the same components as those not shown will be described using the same reference numerals used in the description of the first embodiment.

In this embodiment, the transfer control unit obtains the skew value from the difference between the counter values and adjusts the data transfer timing. Therefore, as shown in FIG. 19, the composite apparatus 1 of this embodiment has skew measurement circuits 20a and 20b. Transfer control units 90a and 90b and delay circuits 40a and 40b.

  The skew measurement circuits 20a and 20b are the same as the skew measurement circuits 20a and 20b of the first embodiment. The OR circuits 21a and 21b output the OR outputs of the reference signal Ksh and the comparison reference signal Ksh, and the counters 22a and 22b output the skew values. Count and output to the skew determination circuits 100a and 100b. The skew measurement circuit is not limited to the skew measurement circuits 20a and 20b of the first embodiment, and the skew measurement circuits 50a and 50b of the second embodiment or the skew measurement circuits 80a and 80b of the third embodiment. There may be.

  As shown in FIG. 20, the skew determination circuits 100a and 100b include counter value transmission / reception circuits 101a and 101b, counter value difference calculation circuits 102a and 102b, and difference value determination circuits 103a and 103b. FIG. 20 shows the skew determination circuit 100a of the transfer control unit 90a. In the following description, the skew determination circuit 100a will be described, but the skew determination circuit 100b of the transfer control unit 90b has the same configuration and performs the same operation.

  The counter value transmission / reception circuit 101a receives a skew value, which is a counter value, from the skew measurement circuit 20a, and the skew value, which is a counter value counted by the skew measurement circuit 20b of the transfer control unit 90b, is a counter of the skew determination circuit 100b. It is transmitted from the value transmission / reception circuit 101b. The counter value transmission / reception circuit 101a transmits the skew value input from the skew measurement circuit 20a to the counter value transmission / reception circuit 101b of the skew determination circuit 100b of the transfer control unit 90b, and the skew value from the skew determination circuit 100b of the transfer control unit 90b. Is output to the counter value difference calculation circuit 102a. Therefore, although the transfer control unit 90a and the transfer control unit 90b are configured by ASIC, they are provided with external terminals for transmitting and receiving these signals.

  The skew value transmitted from the skew determination circuit 100b of the transfer control unit 90b is input to the counter value difference calculation circuit 102a via the counter value transmission / reception circuit 101a, and the counter value counted by the own skew measurement circuit 20a is counted. The skew value is input, and the difference between the two skew values is calculated and output to the difference value determination circuit 103a.

  The difference value determination circuit 103a determines whether the difference is “0”, that is, whether both skew values are the same, and whether the skew value is larger when the difference is not “0”. Then, the determination result is output to the delay circuit 40a.

  The delay circuits 40a and 40b delay the image data according to the skew determination result from the skew determination circuits 100a and 100b.

  That is, in the composite apparatus 1 of the present embodiment, the transfer control units 90a and 90b have the reference signal Ks sent directly from the print processing unit 8 and the comparison reference sent via the other transfer control units 90a and 90b. The time difference of the signal Ksh is measured as a skew value by the skew measurement circuits 20a and 20b, the difference between the skew values measured by the respective skew measurement circuits 20a and 20b is determined by the skew determination circuits 100a and 100b, and the delay circuits 40a and 40b. To adjust the transfer timing of the image data.

  As described above, in the composite apparatus 1 according to the present embodiment, the transfer control units 90a and 90b communicate the time differences (skews) detected by the skew measurement circuits 20a and 20b with each other, and delay circuits based on the skews. Skew determination circuits 100a and 100b for adjusting the transmission timing of image data by adjusting the delays 40a and 40b are incorporated.

  Therefore, it is possible to perform image data skew adjustment only by the transfer control units 90a and 90b without setting from the CPU 6.

  FIG. 21 is a principal block diagram of the transfer control unit of the composite apparatus to which the fifth embodiment of the present invention is applied.

  The present embodiment is applied to a composite apparatus similar to the composite apparatus 1 of the first embodiment. In the description of the present embodiment, the same reference numerals are used for the same components as in the first embodiment. In addition, the same components as those not shown will be described using the same reference numerals used in the description of the first embodiment.

  In this embodiment, the skew between the transfer control units when there are more than two transfer control units is measured, and FIG. 21 shows a case where there are three transfer control units.

  In FIG. 21, the multifunction apparatus 1 includes three transfer control units 110, 120, and 130, and the reference signal Ks sent directly from the print processing unit 8 to each of the other transfer control units 110, 120, and 130. The mutual skew is measured on the basis of the comparison reference signal Ksh transferred via the.

  Therefore, each transfer control unit 110, 120, and 130 is equipped with two skew measurement circuits 111 and 112, skew measurement circuits 121 and 122, and skew measurement circuits 131 and 132, respectively. All have the same circuit configuration and are the same as the skew measurement circuits 20a, 20b, 50a, 50b, 80a, 80b of the first to third embodiments.

  In FIG. 21, the signal system path that directly receives the reference signal Ks from the print processing unit 8 is not shown, and the signal system of the comparison reference signal Ksh that is transferred between the transfer control units 110, 120, and 130. Only signal paths (internal interconnection means) L13 for exchanging the reference signal Ks between the two skew measurement circuits 121 and 122 are shown only in the paths (interconnection means) L11 and L12 and the middle transfer control unit 120. Has been.

  In the composite apparatus 1, the skew measurement circuit 111 of the transfer control unit 110 and the skew measurement circuit 121 of the transfer control unit 120 are connected by a signal line L11, and the skew measurement circuit 122 of the transfer control unit 120 and the skew measurement of the transfer control unit 130 are connected. A circuit 132 is connected by a signal line L12. The skew measurement circuit 121 and the skew measurement circuit 122 of the transfer control unit 120 are connected by a signal line L13.

  The composite apparatus 1 obtains the skew value between the transfer control unit 110 and the transfer control unit 120 by the skew measurement circuit 111 and the skew measurement circuit 121 connected by the signal system path L11, and determines the transfer control unit 120 and the transfer control. The skew measurement circuit 122 and the skew measurement circuit 132 connected to each other by the signal system path L12 are obtained by the skew measurement circuit 122 and the skew measurement circuit 132.

  The CPU 6 can calculate the skew values of the transfer control unit 110 and the transfer control unit 130 from these two skew values.

  For example, when the skew relationship of the skew measurement results is such that the transfer control unit 110> the transfer control unit 120 and the transfer control unit 120> the transfer control unit 130, the transfer control unit 110> the transfer control unit 120> the transfer control unit 130. It becomes. Note that> indicates that the transfer rate of the reference signal Ks is fast (low skew value)> slow (high skew value).

  On the contrary, when the skew relationship of the skew measurement results is such that the transfer control unit 110 <the transfer control unit 120 and the transfer control unit 120 <the transfer control unit 130, the transfer control unit 110 <the transfer control unit 120 <the transfer control unit. 130.

  However, if the skew values of the skew measurement results are such that the transfer control unit 110> the transfer control unit 120 and the transfer control unit 120 <the transfer control unit 130, the transfer control unit 110 <the transfer control unit 120 and the transfer control unit 120. > When the transfer control unit 130 is not in order as in the transfer control unit 130, the magnitude relationship between the skew values of the transfer control unit 110 and the transfer control unit 130 is unknown.

  However, the composite apparatus of the present invention is provided with the signal system path L13 that connects the two skew measurement circuits 121 and the skew measurement circuit 122 of the middle transfer control unit 120, and the transfer is performed via the signal system path L13. The skew measurement circuit 111 of the control unit 110 and the skew measurement circuit 132 of the transfer control unit 130 are connected to transfer the comparison reference signal Ksh.

  That is, from the skew measurement circuit 111 to the skew measurement circuit 132, the skew measurement circuit 111 → the signal system path L11 → the skew measurement circuit 121 → the signal system path L13 → the skew measurement circuit 122 → the signal system path L12 → the skew measurement circuit 132. The comparison reference signal Ksh is transferred, and the comparison reference signal Ksh is transferred from the skew measurement circuit 132 to the skew measurement circuit 111 through the reverse path.

  In this case, if the signal path L13 between the skew measurement circuit 121 and the skew measurement circuit 122 is a different path depending on the signal transfer direction, it is necessary to take into account the delay difference in this portion other than the skew of the reference signal Ks. Therefore, it is necessary to develop a small delay difference during design development.

  Note that, in the composite apparatus 1 of this embodiment, the skew measurement circuit 111 and the skew measurement circuit 121 and the skew measurement circuit 122 and the skew measurement circuit 132 are simultaneously performed twice in both directions. A total of four measurements are performed twice in both directions between the skew measurement circuit 122 and the skew measurement circuit 121 from the circuit 132 in a bidirectional manner, so that all the transfer control units 110 to 130 are connected. You can skew.

  As described above, the composite apparatus 1 according to the present embodiment includes the three transfer control units 110, 120, and 130. Each transfer control unit 110, 120, and 130 includes two skew measurement circuits 111 and 112, and a skew. The measurement circuit 121, 122 and the skew measurement circuit 131, 132 are provided, and the skew measurement circuit 111, 121, 122, 132 of the adjacent transfer control units 110, 120, 130 receives the transfer reference signal Ksh by serial bidirectional communication. L13 is connected by signal paths L11 and L12 for transmitting and receiving, and two skew measurement circuits 121 and 122 provided in the intermediate transfer control unit 120 connected in series communicate with each other the transfer reference signal Ksh. Are connected to each other, and the skew measurement circuits 111, 121, 122, 132 of each transfer control unit 110, 120, 130 are connected to each other. And detects the skew is the time difference based on the comparison reference signal Ksh and the reference signal Ks transmitted and received system path L11, L12 or the signal pathway L11, L12 and the signal pathway L13.

  Therefore, even when three or more transfer control units 110, 120, 130, etc. transfer image data to the print processing unit 8 in synchronization, the skew between the transfer control units 110, 120, 130 is appropriately measured. The image data can be appropriately transmitted to the print processing unit 8 in synchronization.

  22 and 23 are diagrams showing a sixth embodiment of the present invention, and FIG. 22 is a circuit block diagram of a transfer control unit of a composite apparatus to which the sixth embodiment of the present invention is applied.

  The present embodiment is applied to a composite apparatus similar to the composite apparatus 1 of the first embodiment. In the description of the present embodiment, the same reference numerals are used for the same components as in the first embodiment. In addition, the same components as those not shown will be described using the same reference numerals used in the description of the first embodiment.

  In this embodiment, when there are more than two transfer control units, the skew between the transfer control units is measured only by each transfer control unit having one skew measurement circuit. The case where there are three control units is shown.

  In FIG. 22, the composite apparatus 1 includes three transfer control units 140, 150, and 160, and the reference signal Ks directly sent from the print processing unit 8 to each of the transfer devices 140, 150, and 160. The mutual skew is measured on the basis of the comparison reference signal Ksh transferred via the.

  Therefore, each of the transfer control units 140, 150, and 160 includes one skew measurement circuit 141, skew measurement circuit 151, and skew measurement circuit 161, and each of the skew measurement circuits 141 to 161 has the same circuit configuration. As shown in FIG. 23, a selector 171, an OR circuit 172, a counter 173, and a holding unit 174 are provided.

  In each of the transfer control units 140, 150, and 160, skew transfer circuits 141, 151, and 161 are connected to each other by signal paths (interconnect means) L21, L22, and L23. In FIG. 22, only the signal paths L21, L22, and L23 for transferring the comparison reference signal Ksh between the transfer control units 140 to 160 are shown, but the reference signal Ks from the print processing unit 8 is shown. The description of the signal line is omitted.

  As shown in FIG. 23, each skew measurement circuit 141, 151, 161 selects an input signal by the selector 171, performs OR processing on the signal selected by the selector 171 by the OR circuit 172, and outputs the OR output to the counter 173. Output.

  The counter 173 counts the number of clocks CLK while the OR output is Hi, and outputs the counted number to the holding unit 174.

  The holding unit 174 has a function of holding the counter value of the counter 173 by at least the number (three) of combinations of signals selected by the selector 171, and holds the counter value of the counter 173.

  In the composite apparatus 1 of this embodiment, the plurality of transfer control units 140 to 160 and the skew measurement circuits 141, 151, and 161 mounted on the transfer control units 140 to 160 can have the same configuration, and the configuration is simplified. On the other hand, the image data transfer control can be performed by obtaining the skew values between all the transfer control units 140 to 160.

  In this case, since each of the transfer control units 140 to 160 includes one skew measurement circuit 141, 151, 161, the transfer control unit 140 and the transfer control unit 150, the transfer control unit 150, the transfer control unit 160, and the transfer Since it is necessary to measure the skew between the control unit 160 and the transfer control unit 140 by connecting them two times, the skew value between all the transfer control units 140 to 160 can be obtained by measuring a total of six times. Can be sought.

  As described above, the composite apparatus 1 of this embodiment includes three or more transfer control units 140 to 160, and each transfer control unit 140 to 160 has one skew measurement circuit 141, 151, 161 having the same configuration. Only equipped. The skew measurement circuits 141, 151, 161 are connected to each other by signal paths L 21, L 22, L 23, and the skew measurement circuits 141, 151, 161 are directly transmitted from the print processing unit 8. A selector 171 for selecting one of the comparison reference signals Ksh transmitted from the other transfer control units 140, 150, and 160 by Ks and the signal paths L21, L22, and L23 is provided. Each skew measurement circuit 141, 151, 161 detects a time difference skew between the reference signal Ks selected by the selector 171 and the comparison reference signal Ksh.

  Accordingly, when image data is transferred from three or more transfer control units 140, 150, 160 to the print processing unit 8 in synchronization, one skew measurement circuit 141, 151, 161 is provided for each transfer control unit 140, 150, 160. The image processing apparatus can measure the skew between the transfer control units 140, 150, and 160, and transmit the image data to the print processing unit 8 appropriately in synchronization with an inexpensive and simple configuration. be able to.

  Although the invention made by the present inventor has been specifically described based on the preferred embodiments, the present invention is not limited to that described in the above embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  The present invention can be used for a data transfer apparatus such as a composite apparatus, a copying apparatus, and a printer apparatus that transfer data from a plurality of transfer control sections to a print processing section, a data transfer control method, a data transfer control program, and a recording medium.

DESCRIPTION OF SYMBOLS 1 Compound apparatus 2 Image input part 3 Image processing part 4 Memory control / controller part 5 Memory 6 CPU
DESCRIPTION OF SYMBOLS 7 Transfer control part 7a, 7b Transfer control part 8 Printing part 9 General-purpose bus 20a, 20b Skew measurement circuit 21a, 21b OR circuit 22a, 22b Counter 30a, 30b Reference signal input / transfer circuit 31a, 31b Reference signal input buffer 32a, 32b Reference signal buffer 33a, 33b Internal buffer 34a, 34b Comparison signal buffer 35a, 35b Input / output buffer 40a, 40b Delay circuit 41-45 Shift register 46 Selector 50a, 50b Skew measurement circuit 51a, 51b OR circuit 52a, 52b Counter 53a , 53b counter 54a, 54b holding circuit 55a, 55b selector 60a, 60b delay circuit 61a-70a, 61b-70b shift register 71a, 71b selector 81a, 81b OR circuit 82 a, 82b OR circuit 83a, 83b AND circuit 84a, 84b AND circuit 85a, 85b Shift register 86a, 86b Shift register 87a, 87b Inverting circuit 88a, 88b Counter 90a, 90b Transfer control unit 100a, 100b Skew determination circuit 101a, 101b Counter Value transmission / reception circuit 102a, 102b Counter value difference calculation circuit 103a, 103b Difference value determination circuit 110, 120, 130 Transfer control unit 111, 112, 121, 122, 131, 132 Skew measurement circuit 140, 150, 160 Transfer control unit 141, 151, 161 Skew measurement circuit 171 Selector 172 OR circuit 173 Counter 174 Holding unit Ks Reference signal Ksh Comparison reference signal

JP 2006-50102 A Japanese Patent No. 3966511

Claims (9)

A plurality of transmission means for transmitting data that needs to be transmitted in synchronization;
Receiving means for receiving the data from each of the transmitting means by outputting a synchronization signal for synchronizing the data to each of the transmitting means connected to each of the plurality of transmitting means via a communication path;
Data output adjusting means for adjusting the transmission timing of the data from each of the transmitting means to the receiving means;
With
Each transmitting means includes a signal receiving means for receiving the synchronization signal sent from the receiving means;
Transfer means for transferring the synchronization signal received by the signal reception means to the other transmission means as a transfer synchronization signal;
Transfer signal receiving means for receiving a transfer synchronization signal transferred from the transfer means of the other transmitting means;
A time difference detecting means for detecting a time difference between the synchronization signal received by the signal receiving means and the transfer synchronization signal received by the transfer signal receiving means;
With
The data transfer apparatus, wherein the output adjusting means adjusts an output timing of the data transmitted from the transmitting means to the receiving means based on the time difference detected by the time difference detecting means.   2. The data transfer apparatus according to claim 1, wherein the time difference detection means detects a time difference between the synchronization signal and the transfer synchronization signal using an internal clock and an inverted clock of the internal clock. The synchronization signal is a pulsed signal that remains in a high state for a predetermined time,
The time difference detecting means is a time when the synchronization signal and the transfer synchronization signal are continuously in a high state or when the transfer synchronization signal is input high after the synchronization signal has changed from high to low. 3. The data according to claim 1, wherein the time difference is detected based on a time when the synchronization signal and the transfer synchronization signal are in a high state including a time when the synchronization signal becomes low. Transfer device. Each of the transmission means includes transmission / reception means for communicating with each other the time difference detected by the time difference detection means,
The said output adjustment means is incorporated in each said transmission means, The output timing of the said data transmitted to the said reception means is adjusted based on the time difference exchanged by the said transmission / reception means, The Claim 1 characterized by the above-mentioned. Item 4. The data transfer device according to Item 3. The data transfer device
Comprising three or more transmission means,
The transmitting means includes two time difference measuring devices each including the signal receiving means, the transferring means, and the time difference detecting means, and the time difference measuring devices are connected in series by the transmitting means and the signal receiving means adjacent to each other. The two time difference measuring devices provided in the intermediate transmission means connected to each other by the interconnection means for transmitting and receiving the transfer synchronization signal by bidirectional communication mutually exchange the transfer synchronization signal. Connected by internal interconnection means to communicate,
The time difference detecting means of the time difference measuring device of the transmitting means detects the time difference based on the transfer synchronization signal transmitted and received by the interconnection means or the interconnection means and the internal interconnection means and the synchronization signal. The data transfer device according to claim 1. The data transfer device
Comprising three or more transmission means,
In the transmission unit, the signal reception unit, the transfer unit, and the time difference detection unit having the same configuration are configured as one time difference measurement device,
Each transmission means includes an interconnection means for connecting the time difference measuring devices of the transmission means to each other,
Each of the time difference measuring devices includes a selection unit that selects one of the synchronization signals and one of the transfer synchronization signals transmitted from the other transmission unit by the interconnection unit,
2. The data transfer apparatus according to claim 1, wherein the time difference detection means detects a time difference between the synchronization signal selected by the selection means and the transfer synchronization signal. A plurality of transmission processing steps for transmitting data that needs to be transmitted synchronously;
A plurality of transmission processing steps connected to each other through a communication path, and a reception processing step for receiving the data from each transmission processing step by outputting a synchronization signal for synchronizing the data to each transmission processing step;
A data output adjustment processing step for adjusting the transmission timing of the data from each transmission processing step to the reception processing step;
Have
Each transmission processing step includes a signal reception processing step for receiving the synchronization signal transmitted from the reception processing step;
A transfer processing step of transferring the synchronization signal received in the signal reception processing step to another transmission processing step as a transfer synchronization signal;
A transfer signal reception processing step for receiving a transfer synchronization signal transferred from the transfer processing step of the other transmission processing steps;
A time difference detection processing step for detecting a time difference between the synchronization signal received in the signal reception processing step and the transfer synchronization signal received in the transfer signal reception processing step;
Have
The data transfer control method, wherein the output adjustment processing step adjusts an output timing of the data transmitted from the transmission processing step to the reception processing step based on the time difference detected in the time difference detection processing step. On the computer,
A plurality of transmission processes for transmitting data that needs to be transmitted in synchronization;
A receiving process that is connected to each of the plurality of transmission processes via a communication path and outputs a synchronization signal for synchronizing the data to each of the transmission processes and receives the data from each of the transmission processes;
A data output adjustment process for adjusting the transmission timing of the data from each of the transmission processes to the reception process;
And execute
As each of the transmission processes, a signal reception process for receiving the synchronization signal transmitted from the reception process;
A transfer process for transferring the received synchronization signal of the signal reception process to another transmission process as a transfer synchronization signal;
A transfer signal reception process for receiving a transfer synchronization signal transferred from the transfer process of the other transmission processes;
A time difference detection process for detecting a time difference between the synchronization signal received by the signal reception process and the transfer synchronization signal received by the transfer signal reception process;
And execute
A data transfer control program for adjusting the output timing of the data to be transmitted from the transmission process to the reception process based on the time difference detected in the time difference detection process as the output adjustment process.   A computer-readable recording medium on which the data transfer program according to claim 8 is recorded.

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