JPH0646028A - Signal speed conversion circuit - Google Patents

Abstract

PURPOSE:To realize a low-cost signal speed conversion circuit having a simple circuit constitution at the time of subjecting low-speed data including 14.4kbps data to speed conversion to multiplex data with respect to the signal speed conversion circuit of a digital transmission equipment. CONSTITUTION:This signal speed conversion circuit consists of a flip flop 2 for speed conversion, to which low-speed data outputted from a low-speed signal interface 1 and a clock 8 for speed conversion are inputted and which converts this data to transmission data synchronized with the clock 8 for speed conversion, and a transmission data multiplexing shift register 3 for multiplexing of transmission data of plural channels and is characterized by converting the speed of low-speed data to be transmitted to the signal speed for multiplexing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal speed conversion circuit for a digital transmission device, and more particularly, to a low speed data digital transmission for multiplexing low speed data having various transmission speeds and transmitting the multiplexed data through a digital transmission line. The present invention relates to a signal speed conversion circuit of a device.

[0002]

2. Description of the Related Art Conventionally, in data communication through a digital transmission line, a transmission speed of 64 kbps is basically used.
An integer multiple speed of 4 kbps is used. On the other hand, RS2
The transmission speed of data transmitted and received from a terminal device such as a personal computer having a serial transmission port such as 32C is lower than that of digital transmission, and the following transmission speed is usually used. 300bps, 600bps, 1.2k
bps, 2.4 kbps, 4.8 kbps, 9.6 kb
ps, 14.4 kbps, 19.2 kbps.

The low speed data having these transmission speeds is mainly transmitted through an analog transmission line using a modem. When low speed data is transmitted through a high speed digital transmission line, a low speed data of a plurality of channels is usually used. The data is multiplexed and converted into high-speed data having a speed of 64 kbps for transmission.

Conventionally, when low speed data having several speeds are multiplexed at 64 kbps, two methods are mainly used.

One is to transfer the low-speed data to be multiplexed onto the 64 kHz clock for each channel to 64.
It is the first method of converting to a kbps speed and multiplexing.

The other is to multiplex low-speed data at a speed obtained by multiplying the common multiple of the speeds of some low-speed data to be multiplexed by the number of multiplexing channels, and then perform data rearrangement and speed conversion, It is the second method of multiplexing at a speed of 64 kbps.

[0007]

However, the conventional method has the following problems. In the case of the above-mentioned first conventional method, since the speed of low-speed data is directly converted to 64 kbps, there is an advantage that a clock of 64 kbps or more is not necessary and it can be synchronized with the clock of the terminal. For each, it is necessary to use a memory for exclusive use of speed conversion called an elastic store and a dual port RAM having two ports for writing data as a buffer.

This elastic store or dual port RAM is expensive, and since it is necessary for each channel to be multiplexed, there is a problem that the cost of the signal speed conversion circuit becomes high.

In the case of the above-mentioned second conventional method, since the rearrangement of data and the speed conversion are collectively performed by the dual port RAM after the multiplexing, the cost is lower than that of the first method, but it is used for the multiplexing. There is a problem that the speed of the low speed data to be processed is limited to the common multiple.

For example, of the speeds of 300 bps to 19.2 kbps used for the above-mentioned low speed data, 14.
Since all speeds except 4 kbps are divisors of 19.2 kbps, they can be multiplexed with a clock of 19.2 kHz × (the number of channels to be multiplexed), but 14.4 kbps.
Since s is 3/4 of 19.2 kbps, 14.4 k
In order to add low-speed data of bps at the same time as it is, the least common multiple of 14.4 and 19.2 is 19.2.
Clocks of (kHz) × 3 (= 57.6 kHz), which is a multiple of the number of channels to be multiplexed, are required.

However, when a high-speed clock is used, there is a problem that the circuit scale is increased and the cost is increased to generate the high-speed clock, and many conventional speed converters are compatible with 14.4 kbps. Some have not.

The present invention has been made in consideration of the above circumstances, and when low speed data including 14.4 kbps is speed-converted and multiplexed, the speed of the low speed data is reduced by using a simple circuit structure. To provide a signal speed conversion circuit that can be multiplexed with a clock of 19.2 kHz × the number of channels by converting the signal to 19.2 kbps.

[0013]

FIG. 1 shows a block diagram of the configuration of the present invention. As shown in FIG.
A low-speed signal interface 1 for controlling transmission / reception of low-speed data, a transmission-side speed conversion unit 4 and a reception-side speed conversion unit 7 for performing mutual conversion between the low-speed data speed and the transmission path speed,
In a signal speed conversion circuit of a digital transmission device that multiplexes low-speed data and transmits it to a transmission line, low-speed data output from a low-speed signal interface 1 and a speed conversion clock 8 are input and transmission is performed in synchronization with the speed conversion clock 8. The speed conversion flip-flop 2 for converting into data, and the transmission data multiplexing shift register 3 for collecting and multiplexing the transmission data output from the speed conversion flip-flop 2 by the number of a plurality of channels, and transmitting at a low speed The present invention provides a signal speed conversion circuit characterized by converting a data speed into a signal speed for multiplexing.

Also, in the signal speed conversion circuit of the digital transmission device, for separating received data for separating the multiplexed data received from the receiving side speed converting section 7 and generating received data in synchronization with the speed converting clock 8. A shift register 6 and a speed conversion flip-flop 5 that receives the received data output from the received data separation shift register 6 and a low-speed signal clock 9 and outputs low-speed data in synchronization with the low-speed signal clock 9. The present invention provides a signal speed conversion circuit characterized by converting the speed of received data separated and separated into the speed of low speed data.

A signal speed conversion circuit for converting the speed of the low speed data to be transmitted into a signal speed for multiplexing and a signal speed conversion circuit for converting the speed of the separated received data into the speed of the low speed data. May be provided, and mutual conversion between the speed of low-speed data and the signal speed for multiplexing may be performed.

Further, when converting low-speed data having a speed of 14.4 kbps to a speed of 19.2 kbps and multiplexing, 14.4 kH is used as the low-speed signal clock 9.
z, 19.2 kHz as the speed conversion clock 8
However, in order to reliably determine the data at the rising edge of each clock, it is preferable to prepare clocks at 14.4 kHz and 19.2 kHz that have phases such that the falling positions of the clocks coincide.

When converting low-speed data having a speed of 19.2 kbps, as the low-speed signal clock 9, a 19.2 kHz clock having a phase opposite to that of the 19.2 kHz speed conversion clock 8 should be prepared. Is preferred.

9.6 kbps, 4.8 kbps, 2.4
kbps, 1.2 kbps, 600 bps and 300
When converting low-speed data having a speed that is a so-called divisor of 19.2 kbps of bps to 19.2 kbps, 1 is set as the low-speed signal clock 9 corresponding to each speed.
It is preferable to prepare a clock whose rising edge does not match that of the speed conversion clock 8 of 9.2 kHz.

[0019]

According to the present invention having the above-mentioned structure, the speed conversion flip-flop 2 performs speed conversion of the low speed data in synchronization with the low speed signal clock 9 using the speed conversion clock 8, and vice versa. When the speed conversion flip-flop 5 performs speed conversion of the reception data synchronized with the speed conversion clock 8 using the low speed signal clock 9, when the speed of the low speed data to be multiplexed includes 14.4 kbps. However, speed conversion can be performed with a simple circuit configuration, and a low-cost signal speed conversion circuit can be realized.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on the embodiments shown in the drawings. The present invention is not limited to the embodiments. FIG. 2 is a block diagram of a signal speed conversion circuit in the embodiment of the present invention. Figure 3
It is a time chart which shows the example of signal speed conversion in the Example of this invention.

In FIG. 2, reference numeral 21 is a low speed signal interface for connecting to a terminal device such as a personal computer having a serial transmission interface such as RS232C. Three
0 is the low-speed signal clock 29 for the transmission data SD sent from the terminal device side through the low-speed signal interface.
(FIG. 3 CKA-1) is a signal synchronization flip-flop that synchronizes and shapes the signal waveform.

Reference numeral 22 denotes a signal synchronization flip-flop 30.
DATA1 which is the output of the speed conversion clock 19.2
Synchronize at kHz (Fig. 3 CKB-1) and set the speed to 1
It is a speed conversion flip-flop that generates a signal DATA2 converted to 9.2 kbps. Reference numeral 23 is a multiplexing shift register that collects and multiplexes a plurality (n) of data (DATA2) synchronized with the speed conversion clock 19.2 kHz (CKB-1 in FIG. 3).

Reference numeral 24 is the above-mentioned multiplexing shift register 23.
It is a transmission side speed conversion unit for converting the data multiplexed by the above method into 64 kbps which is the speed at which it is sent to the digital transmission line. 27 is 64k sent from digital transmission line
It is a reception side speed conversion unit for speed converting the data of bps into 19.2 × nkbps.

Reference numeral 26 designates the 19.2 × nkbps data sent from the receiving side speed converting section 27 at 19.2 kHz.
Data DA synchronized with the speed conversion clock 28
This is a separation shift register that separates into TA3. 25
Is the data DAT synchronized with the 19.2 kHz clock
It is a speed conversion flip-flop that resynchronizes A3 with the low speed signal clock 29 (CKA-2 or CKA-3 in FIG. 3) to convert the speed.

Reference numeral 32 is an inverter for inverting the phase of the low speed signal clock 29. Reference numeral 31 denotes reception data (DATA converted in speed by the speed conversion flip-flop 25).
4 or DATA 5) is a signal-determining flip-flop which is shifted by half a clock and sent to the low-speed signal interface 1.

Reference numeral 28 is a speed conversion clock that serves as a reference for converting the speed of low-speed data to be transmitted, and in this embodiment, 19.2 kHz is used. Reference numeral 29 is a low-speed signal clock that serves as a reference for synchronization and speed conversion of low-speed data transmitted and received.

The low-speed signal clock 29 supplies a clock having a frequency corresponding to the speed of low-speed data transmitted and received through the low-speed interface. For example, when low-speed data of 9.6 kbps is transmitted,
Provides a 9.6 kHz clock. As shown in FIG. 2, the low-speed signal clock 29 is supplied to the low-speed interface 21, and is further given to the terminal device as the transmission clock ST2 and the reception clock RD.

As the low speed signal clock 29, 1
19.2k when supplying a 9.2kHz clock
The clock has a phase opposite to that of the Hz speed conversion clock 28. Also, as the low speed signal clock 29, 14.4k
In the case of supplying a clock of Hz, a clock having a phase such that the falling edge matches the speed conversion clock 28 of 19.2 kHz. Furthermore, when a divisor of 19.2 kHz, which is 9.6 kHz or less, is supplied as the low-speed signal clock 29, a clock having a phase whose rising edge does not coincide with the speed conversion clock 28 of 19.2 kHz is used.

First, the general operation of the signal speed conversion circuit having the above configuration will be described. Although the signal speed conversion circuit occupies a part of the digital transmission device, it also serves as an interface with the digital transmission line in the digital transmission device and mainly performs speed conversion with data on the transmission line having a transmission speed of 64 kbps. A speed conversion unit (comprising a transmission side speed conversion unit 24 and a reception side speed conversion unit 27)
And a terminal device that mainly transmits low-speed data of 19.2 kbps or less.

The signal speed conversion circuit in the embodiment receives the transmission data SD synchronized with the transmission clock ST2 sent from the terminal device through the low speed signal interface 21 to the terminal side by the low speed signal interface 21, and outputs it at 19.2 kHz.
Then, the data is transmitted to the transmission side speed converting section 24 after being subjected to speed conversion into a multiplex.

On the contrary, the multiplexed data received from the receiving side speed converting unit 27 is separated into the receiving data of 19.2 kbps and further converted into the speed of the low speed data corresponding to the transmission clock ST2, and the low speed signal interface 21 Through the low speed reception data RD to the terminal device.

In FIG. 2, a signal synchronization flip-flop 30 removes jitter contained in the transmission data SD sent through the low-speed signal interface 21 to shape the signal waveform, and a signal confirmation flip-flop. Reference numeral 31 is for shifting the speed-converted received data by a half clock to perform phase matching so as to meet the standard of the low-speed signal interface.

As described above, the signal synchronizing flip-flop 30 and the signal determining flip-flop 31 shown in this embodiment are for ensuring signal transmission in the low speed signal interface 21, and are essential for speed conversion. Not a circuit.

Next, the operation of the embodiment will be described with reference to the time chart of FIG. In FIG. 3, 1 low-speed data of 14.4 kbps is transmitted through the low-speed signal interface 21.
The time chart in the case of performing speed conversion into a signal of 9.2 kbps is shown.

In the figure, (1-1) is 14.4k.
It is a clock of Hz, and shows the low speed signal clock 29 in FIG. (1-2) is the data DATA1 output from the signal synchronization flip-flop 30, and is the same 14.4 kHz clock CK as (1-1).
It is data synchronized with A-1.

(1-3) is a clock of 19.2 kHz, and shows the speed conversion clock 28 in FIG. As described above, in (1-3), 19.
It is assumed that the 2 kHz clock and the (1-1) 14.4 kHz clock are supplied with clocks having phases such that their falling edges match. (1-4) is the data DATA2 output from the speed conversion flip-flop 22,
Same as (1-3), 19.2 kHz clock CKB-1
The data is synchronized with.

(1-5) is the same as (1-3) 19.2.
It is a clock CKB-1 of kHz. (1-6) is the received data DA output from the separation shift register 26
TA3, which is data synchronized with the 19.2 kHz clock CKB-1.

(1-7) and (1-9) are the same low-speed signal clock 29 of 14.4 kHz as (1-1).
(1-7) and (1-9) of the 14.4 kHz clock are
Although it has a phase in which the falling edge matches the 19.2 kHz clock CKB-1 of (1-5), the received data DATA
In relation to 3, the 14.4 kHz clock is CKA-2
It may take two phases, (1-7) and CKA-3 (1-9).

(1-8) is the received data DATA4 output from the speed conversion flip-flop 25, which is 1
It is data synchronized with CKA-2 (1-7) having a 4.4 kHz clock. (1-10) is the reception data DATA5 output from the speed conversion flip-flop 25, which is data synchronized with CKA-3 (1-9) of the 14.4 kHz clock.

First, the operation at the time of transmission for speed-converting the input transmission data of 14.4 kbps through the low speed signal interface 21 will be described. In the signal synchronization flip-flop 30, the input transmission data of 14.4 kbps is synchronized at the rising edge of the clock CKA-1 of 14.4 kHz and 14.4 such as data DATA1.
Data synchronized with the low speed signal clock 29 of kHz is output.

In the speed conversion flip-flop 22, the input data DATA1 is speed-converted in synchronization with the rising edge of the speed conversion clock CKB-1 at 19.2 kHz, and 19.2k like the data DATA2.
Data synchronized with the Hz clock is output. Where 1
Since the 4.4 kHz clock CKA-1 and the 19.2 kHz clock CKB-1 have the phases in which the falling edges are the same, the data can be surely converted at the rising edge of the 19.2 kHz clock CKB-1. 3 bits (A, B, C) of data DATA1 of 4 kbps is 19.
4 bits of data DATA2 of 2 kbps (A, A,
The speed is converted to B, C). However, the first 14.4k
The first bit (A) of bps is 2b of 19.2 kbps.
It is associated with it minutes.

After this, the clock CKB of 19.2 kHz
The data DATA2 synchronized with −1 is multiplexed by the shift register 23 for multiplexing together with some other data synchronized with the clock CKB-1 of 19.2 kHz and sent to the transmission side speed conversion unit 24. When the number of data to be multiplexed here is n, 19.2 × nkHz
The multiplexed data is generated in synchronization with the clock.

Further, the low-speed signal clock 29 is set to 1
19.2 kHz if anything other than 4.4 kHz is used
In the case of Hz, 19.2 kHz speed conversion clock 2
A clock having a phase opposite to that of 8 is used, and when the frequency is 9.4 kHz or less, a clock whose rising edge does not coincide with the speed conversion clock 28 of 19.2 kHz is used.
Data can be converted at the rising edge of the kHz clock.

Next, the operation at the time of reception for speed-converting the received data input from the receiving side speed converter 27 will be described.
In the separation shift register 26, 19.2 × nkH
Received data synchronized with the z clock is input and separated into n pieces of data. The separated data DATA3 is
This is 19.2 kbps data synchronized by the speed conversion clock 28 of 19.2 kHz.

In the speed conversion flip-flop 25, the input data DATA3 is speed-converted in synchronization with the rising edge of the low-speed signal clock CKA-2 or CKA-3 of 14.4 kHz. Clock CKA-
In the case of a phase such as 2, the data is converted into data having a phase of DATA 4, and in the case of a phase such as the clock CKA-3, it is converted into data having a phase of DATA 5.

In case of clock CKA-2, 19.2k
Hz clock CKB-1 and 14.4 kHz clock CK
At the rising position of CKA-2 before the clock where the falling edge of A-2 coincides, the front bit of the data (A) allocated for 2 bits is taken out, and the 1-bit data (A) for DATA4 is taken out. Becomes

In the case of the clock CKA-3, 19.2k
Hz clock CKB-1 and 14.4 kHz clock CK
At the rising position of CKA-3 after the clock where the falling edge of A-3 coincides, the rear bit of the data (A) allocated for 2 bits is taken out, and the 1-bit data (A) for DATA5 is taken out. Becomes

That is, during the period of the data which is allocated to 2 bits by the data DATA3 which is synchronized with 19.2 kHz (2 clocks of 19.2 kHz),
In both cases of the 14.4 kHz clocks CKA-2 and CKA-3, these 14.4 kHz clocks have only one rising edge, so only one of the 2 bits of data (A) is output. Is taken out.

In this way, the speed conversion flip-flop 2
4 to 19.2 kbps data by 5
The data DATA4 or DATA5 converted into 3-bit data of 4.4 kbps is sent to the low-speed signal interface 21 by the signal confirmation flip-flop 31.

The low-speed signal clock 29 of 14.4 kHz inverted by the inverter 32 is input to the signal determining flip-flop 31, and the received data DATA4 or DATA5 is synchronously converted by this clock.

As the low speed signal clock 29, 1
19.2 kHz if anything other than 4.4 kHz is used
In the case of Hz, 19.2 kHz speed conversion clock 2
A clock having a phase opposite to that of 8 is used, and in the case of 9.4 kHz or less, a clock whose rising edge does not coincide with the speed changing clock 28 of 19.2 kHz is used, so that 19.2 is surely obtained.
Data can be converted at the rising edge of the kHz clock.

[0052]

According to the present invention, the speed of low-speed data is converted by one flip-flop, and the speed of the low-speed data is converted by another flip-flop on the other hand. It is possible to perform conversion, and it is possible to realize a low-cost signal speed conversion circuit. Further, in particular, if the configuration of the present invention is used,
Speed conversion of low-speed data having a speed of 4.4 kbps can be realized at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of the present invention.

FIG. 2 is a block diagram of a circuit configuration according to an embodiment of the present invention.

FIG. 3 is a time chart of a speed conversion operation in the embodiment of the present invention.

[Explanation of symbols]

 21 Low-speed signal interface 22 Speed conversion flip-flop 23 Multiplexing shift register 24 Transmission speed conversion part 25 Speed conversion flip-flop 26 Separation shift register 27 Reception speed conversion part 28 Speed conversion clock 29 Low speed signal clock 30 signal Flip-flop for synchronization 31 Flip-flop for signal determination 32 Inverter

Claims (3)

[Claims] 1. A low-speed signal interface (1) for controlling the transmission / reception of low-speed data, a transmission-side speed conversion unit (4) and a reception-side speed conversion unit (4) for performing mutual conversion between the speed of low-speed data and the transmission path speed. In a signal speed conversion circuit of a digital transmission device which includes 7) and multiplexes low speed data to a transmission line, the low speed data output from the low speed signal interface (1) and a speed conversion clock (8) are input,
A speed conversion flip-flop (2) for converting into transmission data in synchronization with the speed conversion clock (8) and transmission data output from the speed conversion flip-flop (2) are collected and multiplexed for a number of channels. A signal speed conversion circuit comprising a transmission data multiplexing shift register (3) and converting the speed of low speed data to be transmitted into a signal speed for multiplexing. 2. A low-speed signal interface (1) for controlling transmission / reception of low-speed data, a transmission-side speed conversion unit (4) and a reception-side speed conversion unit (4) for performing mutual conversion between the speed of low-speed data and the transmission line speed. In a signal speed conversion circuit of a digital transmission device that includes 7) and multiplexes low-speed data and transmits it to a transmission line, the multiplexed data received from the reception-side speed conversion unit (7) is separated and a speed conversion clock ( 8), a shift register (6) for separating received data for generating received data, a received data output from the shift register (6) for separating separated data, and a clock (9) for low speed signal And a speed conversion flip-flop (5) that outputs low-speed data in synchronization with the clock (9) for converting the speed of the separated reception data to the speed of the low-speed data. And a signal speed conversion circuit. 3. A signal speed conversion circuit comprising the signal speed conversion circuit according to claim 1 and the signal speed conversion circuit according to claim 2, wherein the signal speed conversion performs mutual conversion between the speed of low-speed data and the signal speed for multiplexing. circuit.