KR930007133B1 - Waiting time gitter dropping circuit of synchronous muliple apparatus - Google Patents

Abstract

The circuit decreases waiting time jitter generated in a reverse mapping unit during stuffing. The circuit includes a line driving unit (15) for transmitting and for receiving DS3 asynchronous signal, a stuffing and synchronizing unit (1) connected to the line driving unit to map DS3 asynchronous signal to VC32 signal, a de-stuffing and reverse-synchronizing unit (18) connected to the line driving unit to map VC32 signal to DS3 asynchronous signal, and an interface unit (17) for supervising the stuffing and synchronizing unit (1) and the de-stuffing and reverse-synchronizing unit (18).

Description

Latency Jitter Reduction Circuit for Synchronous Multiple Devices

1 is a block diagram of a C32 frame used in the present invention.

2 is a block diagram of a latency jitter reduction circuit according to the present invention.

3 is a signal waveform diagram of each part of FIG.

* Explanation of symbols for main parts of the drawings

1: stuffing and synchronization unit 2,26: signal control unit

3: stuffing control part 4,25: PLL

5: byte part alignment part 6: C32 formation part

7: S / P converter 8,11,22,32: read address generator

9,19: 32-stage sync buffer 10,14,28,31: Write address generator

12,20: buffer monitor 13,21: 16-speed asynchronous buffer

15 line termination and drive unit 16 code violation detection unit

17: processor interface 18: de-stuffing and reverse synchronization unit

23: reverse synchronization unit 24: de-stamping control unit

27: P / S conversion section 29: C bit extraction section

30: C32 dismantling

In the synchronous multiplexing device, the present invention provides a method for performing a stuffing mechanism required to map a digital signal level 3 (DS3): 44.736 Mbps signal to a C32 (Container-32) synchronization signal at a speed of 50.112 Mbps. It relates to a wait time jitter reduction circuit for reducing waiting time jitter (WTJ) in history.

Conventional synchronous multiplex devices have a long history of stuffing mechanisms required to map 44.736 Mbps asynchronous signals to 50.112 Mbps C32 synchronous signals when mapping asynchronous DS3 slave signals to synchronous payloads in synchronous hierarchy. There is a problem that latency jitter occurs.

Therefore, in the synchronous multi-device, the present invention includes an elastic buffer circuit for compensating for a frequency offset between a system clock in a synchronous system and a clock extracted from a reception dependent signal on a line, and a 44.736 Mbps DS3 signal. The purpose of this is to provide a latency jitter reduction circuit for reducing the latency jitter generated by the desynchronizer when the synchronous payload is mapped.

In order to achieve the above object, the present invention provides a delay jitter reduction circuit of a synchronous multiple device for minimizing latency jitter when a digital signal level 3 (DS3) asynchronous signal is synchronized to a synchronous payload (C32). Line termination and driving means for inputting and outputting signals; Stuffing and synchronization means connected to said line termination and drive means (15) for mapping said DS3 asynchronous signal to a VC32 signal of 50.112 Mbps; Connected to the line termination and driving means (15), and de-stamping and desynchronizing means for mapping 50.112 Mbps VC32 signals into 44.736 Mbps DS3 asynchronous signals; And a processor interface means connected to said line termination and drive means, stuffing and synchronization means, and de-stuffing and desynchronization means, and monitoring and controlling said stuffing and synchronization means 1 and de-stuffing and desynchronization means. It is characterized by being provided.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a diagram showing the configuration of a C32 frame used in the present invention.

As shown in the figure, the C32 frame is a multi-element of the synchronous multi-device except for the VC32 path overhead (POH) in the VC32 frame. The C32 frame consists of a total of 6264 bits with a repeating cycle of 125μs (8KHz). The C32 frame is composed of nine subframes, and each subframe is composed of 696 bits, and this subframe is used as a basic frame of stuffing synchronization. Thus, the repetition period of the subframe is 13.9 μs (72 KHz), which is 125/9 μs. In addition, the C32 subframe includes an 8-bit time slot for VC32 path overhead (POH), 59 bits of a fixed stuff bit, as shown in a timing diagram for stuffing and de-stamping of FIG. 3. Bit stuffing control bits (C1 to C5), 2 bits reserved overhead bit (O), 621 bits of information bits (I), 1 bit stuffing providing bits (S), according to the present invention The latency jitter reduction circuit mainly uses the 5-bit stuffing control bits C1 to C5 and the 1-bit stuffing providing bit S.

2 is a block diagram of a latency jitter reduction circuit according to the present invention, in which 1 is a stuffing and synchronization unit, 2 and 26 are signal control units, 3 is a stuffing control unit, 4 and 25 are phase locked loops, 5 is a byte alignment unit, 6 is a C32 (Container-32) forming unit, 7 is a serial / parallel (S / P) conversion unit, 8, 11, 22 and 32 are read address generators, and 9 and 19 are 32-speed sync Buffer, 10, 14, 28 and 31 are write address generators, 12 and 20 are buffer monitors, 13 and 21 are 16-speed asynchronous buffers, 15 are line terminations and drivers, 16 are code violation detectors, 17 are processor interface parts 18 is a de-stuffing and desynchronization unit, 23 is a de-synchronization unit, 24 is a de- stuffing control unit, 27 is a parallel / serial conversion unit, 29 is a stuffing control information (C) bit extraction unit, and 30 is a C32 unit. (Container-32) A dismantling part is shown, respectively.

As shown in FIG. 2, the latency jitter reduction circuit according to the present invention connects the stuffing and synchronization unit 1 to the line termination and driving unit 15 to which an asynchronous 44.736Mbps DS3 signal is inputted and outputted, and terminates the line termination and The code violation detection unit 16 is connected to the driving unit 15, and the processor interface 17 is connected to the line termination and driving unit 15, the code violation detection unit 16, the stuffing and synchronization unit 1, and the line termination is performed. And a de-stuffing and desynchronization unit 18 connected to the driving unit 15 and the processor interface 17.

The detailed configuration of the stuffing and synchronization unit 1 for mapping an input asynchronous 44.736 Mbps DS3 signal to a 50.112 Mbps VC32 signal is provided to a signal control unit 2 to which a J1 signal (8 KHz) and a 50 Mbps system clock are input. A byte alignment unit 5 and a stuffing control unit 3 are connected, and a PLL (Phase Locked Loop) 4 is connected between the signal control unit 2 and the stuffing control unit 3. A read address generator (RA) 8, 11 and a write address generator (WA) 10 are connected to the stuffing controller 3, respectively, and the data output terminal and the stuffing of the line termination and the driver 15 are connected. The write address generator 14 is connected to one output terminal of the controller. In addition, a 32-stage synchronous buffer 9 is connected to the output terminal of the read and write address generators 8 and 10, and each output terminal of the read and write address generators 11 and 14, the line termination and the driver 15 A 16-step asynchronous buffer 13 is connected to the clock CLK output terminal, and one output terminal of the 16-step asynchronous buffer 13 is connected to the 32-step synchronous buffer 9. In addition, an input terminal of the buffer monitoring unit 12 is connected to an output terminal of the 16-stage asynchronous buffer 13 and an output terminal of the 32-stage synchronous buffer 9, and an output terminal thereof is connected to the processor interface 17. In addition, an S / P converter 7 is connected to the byte alignment unit 5 and an output terminal of the 32-stage sync buffer 9, and C32 data is output to the signal control unit 2 and the S / P converter 7 output terminal. The C32 formation part 6 which outputs is connected.

On the other hand, the de-stamping de-synchronization unit 18 is connected to the signal control unit 26, the J1 signal (8KHz) 50Mbps system clock is input, the de-stamping control unit 24, C32 disassembly unit 30 for receiving C32 data Is connected to one output terminal of the signal controller 26. In addition, an input terminal of the P / S converter 27 is connected to the other one output terminal of the signal controller 26 and the output terminal of the C32 disassembly unit 30, respectively, and the signal controller 26 and the de-stamping controller 24 are connected to each other. The PLL 25 is connected to each other, and the read and write address generators 28, 31, and 32 are connected to the de-stuffing controller 24, respectively. The P / S converter 27 output terminal and the read and write address generators 28 and 32 output terminals are connected with a 32-stage sync buffer 9, and the P / S converter 27 output terminal and the signal controller ( The C bit extraction unit 29 is connected between the two. Also, a read synchronization buffer 22 is connected to an output terminal of the address buffer 31 and a read signal buffer 22 is configured to apply a clock signal CLK to the line termination and the driver 15 at the reverse synchronization unit 23. Is connected to the output terminal of the read and write address buffers 22 and 31 and the one output terminal of the 32 stage synchronization buffer 9, and the data output terminal is connected to the line termination and the driving unit 15. Is connected to the 16-speed asynchronous buffer 21. In addition, a buffer monitoring unit 20 is connected to each of the 16 stage asynchronous buffers 21 and the output stages of the 32 stage synchronous buffer 19. The buffer monitoring unit 20 output terminal is the stuffing and synchronization unit 1. Likewise connected to the processor interface 17.

The processor interface unit 17 communicates with the CPUs in the buffer monitoring units 12 and 20 of the system to perform monitoring and control functions of the stuffing and synchronization unit or the de-stuffing reverse synchronization unit.

The data received on the line is written to the 16-stage asynchronous buffer 13 by generating a write address through the 16-stage asynchronous buffer write address generator 14 using the recovered clock, and an intermediate frequency (44.784 Mbps) synchronized with the system clock. When reading from the first buffer by generating a read address, data must be stuffed as much as the difference between the two frequencies so that lossless data can be mapped. Here, stuffing means transmitting dummy data in a time slot for stuffing a dependent signal.

The normal stuffing ratio (nominal stuffing rata) is the actual stuffing frequency ratio with respect to the maximum stuffing frequency that can occur. The normal stuffing ratio of the latency jitter reduction circuit according to the present invention is 0.666 [(44.784-44.736) MHz / 72KHz]. This stuffing ratio minimizes latency jitter.

The stuffing control unit 3 compares the phases of the read address clock and the write address clock at a 72KHz subframe period, and determines whether stuffing is performed using the comparison output and the 72KHz subframe clock from the signal controller 2. For example, when stuffing is required, the 44.784 Mbps clock coming out of the PLL circuit 4 is gapped (cleared), and when stuffing is not required, it is not gapped. In addition, by providing a gapped 44.784 Mbps clock to the 16-stage buffer read address generator 11, an effect of stuffing dummy data by two frequency differences is generated, and the information is transmitted to the signal controller 2.

In detail, the PLL circuit 4 uses the 44.784 Mbps clock, the phase-related information of the read and write address clocks, and the subframe clock from the signal controller 2 to stuff each subframe. It determines whether or not and transfers it to the signal controller 2 to request stuffing on the C32 frame.

At this time, the associated function is controlled such that the latency jitter exists above the PLL low-blocking band of the desynchronization unit. This will be described in detail as follows.

The stuffing controller 3 determines stuffing according to the phase accuracy of the two clocks by periodically using the contents of the read and write counters of the first buffer in the first overhead portion of each subframe. When stuffing is required, the phases of the read and write clocks are approaching the threshold or higher, and the counter drive clock of the read address generator 11 between the 16-stage asynchronous buffer 13 and the 32-stage synchronous buffer 9 is removed. This is done by giving a one shot. That is, it is performed by once gapping the 44.784 Mbps clock, which is the output of the PLL circuit 4, at the most significant bit bit position of the third byte after the POH of the VC32.

On the other hand, the stuffing performance information of the stuffing controller 3 is provided to the signal controller 2, and the signal controller 2 sets the stuffing control information C of 5 bits of the C32 frame to "1" when a stuffing request is requested. Then, dummy data is transmitted to the relevant timeslot on the C32 frame by time-spacing the 50.112Mbps clock from the stuffing timeslot. The gapped 50.112Mbps system clock is provided to the 32-stage buffer read address generator 8 to obtain dummy data by not reading the contents of the 32-stage buffer in the corresponding stuffing timeslot. The 5-bit stuffing control information (C) inserted in the stuffing stage is used to determine whether stuffing occurs in history. The signal controller 2 fixes all of the overhead bits C1 to C5 of the C32 frame to "1". This transfers this state to the desynchronization unit.

Thereafter, the 32-stage buffer output data is converted into data in parallel form by the S / P converter 7 under the control of the byte alignment unit 5, and the frame overhead POH is reduced by the C32 frame forming unit 6. The remaining bits are inserted.

The stuffing function is completed through the above process, and the operation process of the de-stuffing function is as follows.

De-stuffing operation uses 5 bits of stuffing control bits (C1 to C5) in C32 frame, and interpreted by 3 out of 5 majority decision principle of 2 error correction function considering the effect of error in transmission path When it is determined that stuffing has been performed, that is, when three or more bits among the 5-bit stuffing control bits C1 to C5 are "1", the dummy bit inserted in the stuffing time slot of the corresponding subframe is removed. This is done by removing it. In other words, the de-stuffing operation is performed in the reverse order of the stuffing operation.

The C32 disassembly unit 30 extracts the 5-bit C bits from the C32 data received by the upper VC32 processing unit, and transfers the 5-bit C bits to the C-bit extracting unit 29. The C-bit extracting unit 29 uses three out of five majority logic. Determination is made or not and the information is transmitted to the signal controller 26. When the signal controller 26 determines that de-stamping should be performed, a 50.112 Mbps clock is clocked by one clock and transferred to the 32-stage buffer write address generator 28. The data from the C32 disassembly unit 30 is converted into serial data by the P / S conversion unit 27 to the 32-level synchronous buffer 19 using the clock of the 32-stage buffer write address generator 28. Is written. The signal control unit 26 is configured to transmit whether or not de-stamping to the de-stamping control unit 24.

On the other hand, the de-stamping control section 24 properly fixes the initial phase of the 32-stage sync buffer 19 to prevent redundant writing and reading of data in the 32-stage sync buffer 19. In addition, when de-stamping is to be received from the signal control unit 26 and de-stamping is to be performed, the 32-stage buffer read address generator 32 and 16 by bit-gapping the 44.784 Mbps clock from the PLL circuit 25 are performed. However, it is supplied to the buffer write address generator 31. The 32-stage synchronous buffer 19 output data output by the control of the 32-stage buffer read address generator 32 is written to the 16-stage asynchronous buffer 21 using the clock of the 16-stage buffer write address generator 31.

The line termination and driver 15 must be supplied with a transmission clock in which the jitter of the output digital signal can satisfy the CCITT and domestic jitter specifications.

To this end, a phase comparator comparing the phases of the 16-stage asynchronous buffer 21, the 16-stage buffer write address generator 31, and the 16-stage buffer read address generator 22, and the latency jitter inserted in the 44.784 Mbps gap clock. 44.736 using a low pass filter (LPF) to remove high frequency components and a voltage controlled oscillator (VCO) consisting of a CCITT and a voltage controlled oscillator (VCO) that generates a read clock of 44.784 Mbps that meets domestic jitter specifications. It is configured to remove the latency jitter component of the high frequency component in the Mbps clock.

Under the control of the 16-stage buffer read address generator 22, the data output from the 16-stage asynchronous buffer 21 is transferred to the line termination and the driver 15, and the output clock of the VCO of the de-synchronizer 23 is used. Bipolar with 3 Zero Substitution (B3ZS) coding and line driving functions are performed. At this time, the size of the second buffer is composed of 16 stages to prevent data loss during continuous de-stamping, which can sufficiently accommodate the effects of latency jitter power over the low pass bandwidth.

Meanwhile, the code violation detection unit 16 has an input terminal connected to the line termination and the driver 15, an output terminal thereof connected to the processor interface 17, and performs a code violation detection function.

In general, a signal encoded by a line rule at a transmitter must exist as specified when it is decoded at the receiver. If this rule is not met, the error is referred to as a "sign violation" signal. In the present invention, the error value is stored in the sign violation detection unit 16 including a counter and a register. The counter is reset when Num is read, and the register is kept in the previous value to increase its operational reliability.

FIG. 3 shows timing relationships when performing the stuffing and de-stamping operations of FIG. 2, wherein a 72 KHz clock representing a subframe boundary, a stuffing position in a 16-stage buffer for stuffing, a stuffing position in a C32 frame, and a stuffing The phases of the majority decision logic judgment position and the stuffing position in the 32-stage buffer are shown. As described above, the C32 subframe shown in FIG. 1 includes an 8-bit time slot for VC32 path overhead (POH), a 59-bit fixed stuff bit, and a 5-bit stuffing control bit (C1). To C5), 2 bits of reserved overhead bits (O), 621 bits of information bits (I), and 1 bit of stuffing providing bits (S), and the 44.736Mbps digital signal standby according to the present invention. The time jitter reduction circuit mainly uses the 5-bit stuffing control bits C1 to C5 and the 1-bit stuffing providing bit S.

The present invention constructed and operated as described above minimizes the latency jitter occurring during the synchronous payload mapping of 44.736Mbps DS 3 signal in a synchronous multiple device, while satisfying the maximum network allowable jitter standard defined by the domestic network. It has the effect of realizing efficient thought and history techniques as synchronous payload.

Claims (6)

In the latency jitter reduction circuit of a synchronous multiple device for minimizing the latency jitter when a digital signal level 3 (DS3) asynchronous signal is synchronized to the synchronous payload (C32), a line termination and a driver for inputting / outputting the DS3 asynchronous signal. 15); Stuffing and synchronization means (1) connected to said line termination and drive means (15) for mapping said DS3 asynchronous signal to a VC32 signal of 50.112 Mbps; Connected to the line termination and driving means (15), and de-stamping and desynchronizing means (18) for mapping 50.112 Mbps VC32 signals into 44.736 Mbps DS3 asynchronous signals; And the line termination and drive unit 15, the stuffing and synchronizing means 1, and the de-stuffing and desynchronizing means 18, and the stuffing and synchronizing means 1 and the de-storing and de-synchronizing means ( 18. A latency jitter reduction circuit comprising a processor interface means (17) for monitoring and controlling 18). 2. A code violation detection means (16) according to claim 1, wherein an input end is connected to the line termination and drive unit (15), and an output end thereof is connected to the processor interface means (17), and a code violation detection means (16) which performs a code violation detection function is performed. The latency jitter reduction circuit further comprises. 3. The apparatus according to claim 1 or 2, wherein the stuffing and synchronizing means (1) comprises: signal control means (2) for inputting a J1 signal (8KHz) and a 50Mbps stuffing clock to generate a 72KHz sub-frame clock and a synchronizing signal; PLL means (4) connected to the signal control means (2) for generating an intermediate frequency synchronized with the system clock; Stuffing control means (3) connected to the PLL means 4 and the signal control means (2) to control whether stuffing is performed using the intermediate frequency of the PLL means (4) and the subframe clock of the signal control means (2). ); A byte alignment means (5) connected to the signal control means (2) to align and control byte phases; A 32-stage buffer read address generating means (8) and write address generating means (10) connected to the stuffing adjusting means (3); 32 stage synchronous buffer means (9) connected to said 32 stage buffer read address generating means (8) and write address generating means (10); 16-stage buffer write address generating means (14) connected to the stuffing adjusting means (3) and the line termination and driving means (15); Read address generating means (11) connected to the stuffing adjusting means (3); 16 stage asynchronous buffer means (13) connected to said read address generating means (11), write address generating means (14), line termination and driving means (15), and 32 stage synchronous buffer means (9); Buffer monitoring means (12) connected to said 16-speed asynchronous buffer means (13), 32-speed synchronous buffer means (9), and processor interface means (17); And a C32 forming means (6) connected to the serial / parallel converting means (7) connected to said byte alignment circuit (5) and a 32-stage synchronous buffer means (9). 3. The apparatus as claimed in claim 1 or 2, wherein the de-stuffing and desynchronization means (1) comprises: C32 decommissioning means (30) for receiving VC32 data and extracting a stuffing control bit; Signal control means (26) connected to the C32 disassembly means (30) for inputting a J1 signal (8KHz) and a 50Mbps system clock to generate a 72KHz subframe clock and a synchronization signal; C bit extracting means (29) connected to said C32 disassembling means (30) and signal control means (26); PLL means 25 connected to the signal control means 26 for generating an intermediate frequency synchronized with the system clock; De-stuffing control means (24) connected to said PLL means (25) and signal control means (26) to control de-stuffing; A 32-stage buffer read address generating means 32 and a 32-stage buffer write address generating means 28 connected to the de-stuffing control means 24; Parallel / serial conversion means 27 connected to the C32 disassembly means 30 and the signal control means 26; 32 stage synchronous buffer means (19) connected to said 32 stage buffer read address generating means (32), 32 stage buffer write address generating means (28) and parallel / serial conversion means (27); 16-stage buffer write address generating means (31) connected to said de-stamping control means (24); Desynchronization means (23) connected to said 16-stage buffer write address generating means (31); A 16-stage buffer read address generating means (22) connected to said line terminating and driving means (15) and reverse synchronization means (23); 16-stage asynchronous buffer means 21 connected to the 32-stage synchronous buffer means 19, 16-stage buffer read address generating means 22, 16-stage buffer write address generating means 31, and line termination and driving means 15; ; And buffer monitoring means (20) connected to said 16-speed asynchronous buffer means (21) and said 32-speed synchronous buffer means (19). 5. The latency jitter reduction circuit according to claim 4, wherein the C-bit extracting means (29) is configured to determine whether or not to de-stamping by three-fold multiplexing logic. 5. The apparatus according to claim 4, wherein said desynchronization means (23) comprises: phase comparison means for comparing phases of said 16-stage buffer write address generating means (31) and said 16-stage buffer read address generating means (22); Means (LPF) coupled to said phase comparing means for removing high frequency components of latency jitter components; And a voltage controlled oscillation means (VCO) connected to the means for removing the high frequency component (LPF) and generating a read clock that satisfies a predetermined jitter specification.