JPH01221948A - Multiplexing circuit and multiplex separation circuit for digital signal - Google Patents

Abstract

PURPOSE:To simplify a circuit and to effectively prevent data from being destroyed by performing the reverse operation of write and readout by constituting the circuit same as that of a multiplexing circuit. CONSTITUTION:At the multiplexing circuit, the data of one frame is held by 12 shift registers (a) and (b) of each 17 stages comprising storage parts A and B as being serial/parallel-converted to 17 parallel data groups with 12 bits width. The held 17 parallel data are read out from corresponding storage parts synchronizing with 17 readout clocks CLK. Also, the write and the readout of the data on the storage parts A and B are performed alternately at every frame. Meanwhile, a multiplex separation circuit operates a write side and a readout side adversely under the same constitution as that of the multiplexing circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital signal multiplexing circuit and a multiplexing/demultiplexing circuit used in the field of digital data communications.

(Prior Art) Multiplexing circuits used in the field of digital data communications write frame-configured digital signals to a frame memory provided for each frame, and read them out at a higher speed than the writing speed. There are some that perform time division multiplexing.

In such a multiplexing circuit, in order to achieve substantial high-speed readout using inexpensive low-speed memory, serial/parallel conversion is performed on the low-order group signal string to be multiplexed to create parallel data of a predetermined bit width. A configuration is adopted in which the written data is written to the frame memory while being converted into parallel data, and the written data is read out in units of parallel data and processed as is, or the parallel/serial conversion is performed using a high-speed shift register and the data is returned to higher-order serial data. There are cases.

That is, the configuration of the multiplexing circuit for one frame is as shown in FIG.
/P) It includes a conversion circuit 2, a selector 3.4, a frequency dividing circuit 5, delay circuits 6 and 7, and a phase comparison circuit 8. Input terminal I
The low-order group signal appearing at
The parallel data is converted into parallel data of an appropriate bit width in synchronization with a clock signal on the write side supplied through the converter circuit 5, and is written into the frame memory 1 in synchronization with a write command output from the frequency dividing circuit 5. On the other hand, reading from the frame memory is performed in units of parallel data in synchronization with the clock signal CKR on the reading side.

In the circuit of FIG. 5, the clock signals on the write side and the read side are not synchronized. For this reason, if the clock signal on the writing side is too early and writing of the next data is started before the reading from the frame memory I is finished, data will be destroyed. In order to prevent this data from being destroyed, the phase comparator circuit 8
The speeds of the clock signals on the write side and the read side are compared, and if the speed on the write side is too fast, delay circuits 6 and 7 are selectively inserted on the write side by switching selectors 3 and 4.

(Problems to be Solved by the Invention) In the conventional multiplexing circuit described above, a serial/parallel conversion circuit is installed in addition to the frame memory, and a phase comparison circuit, a delay circuit, and a selector are installed for adjusting the writing speed. Therefore, there is a problem that the circuit becomes complicated and expensive.

Furthermore, since the write speed is adjusted by comparing the phases of the clock signals on the write side and the read side, control is delicate and there is a risk of data destruction when switching paths.

Further, similar problems exist with demultiplexing circuits.

(Means for Solving the Problems) In the digital signal multiplexing circuit according to the present invention, each frame memory stores one frame's worth of data while serially/parallelly converting it into a parallel data group of an appropriate bit width. The first one includes a group of shift registers that output data units.
．． It consists of a second storage section, and by alternating the writing and reading of data to and from each storage section every frame, it is possible to simplify and reduce the cost of the circuit, and to reduce the distance between the writing position and the reading position by 1. The configuration is such that data destruction can be effectively prevented by spacing the data by a frame or more.

The digital signal multiplexing/demultiplexing circuit according to the present invention has the same circuit configuration as the multiplexing circuit described above, but operates in such a way that the write and read operations are reversed, thereby realizing circuit simplification and cost reduction. is configured to do so.

Hereinafter, the operation of the present invention will be explained in detail together with examples.

(Embodiment) FIG. 1 is a block diagram showing the configuration of one frame of a digital signal multiplexing circuit according to an embodiment of the present invention.

The configuration for one frame includes a first storage section A and a second storage section B. The first storage unit A has 17
12 shift registers al, a2 in stage configuration
It is composed of a12.

The second storage section B is also composed of 12 shift registers bl, b2, . . . b12 each having 17 stages.

On the write side of the first storage section A, twelve clock selectors α1 to α12 are installed corresponding to the twelve shift registers a1 to a12, respectively. There are also 12 shift registers b1 to b on the write side of the second storage unit B.
12 clock selectors β corresponding to each of the 12
l to β12 are installed.

Each of the 12 clock selectors α1 to α12 outputs one of the write clock signals CKI to CK12 appearing at the 12 input terminals 01 to C12 and the read clock signal CLK appearing at the input terminal CK to the input terminal M. It is selected according to the mode selection command and supplied to one of the 12 shift registers a1 to a12. Similarly, each of the 12 clock signal selectors βl to β12 selects one of the write clock signals CKI to CK12 appearing at the 12 input terminals Cl-C12 and the read clock signal CLK appearing at the input terminal CK to the input terminal M. 12 shift registers b1~
b12.

1st. On the read side of the second storage units A and B, there are 12 data selectors γ1. γ2...T12 is installed. These 12 data selectors γ1 to γ12
are the 12 shift registers a1 to a of the first storage unit A.
One of the 12-bit wide parallel data that appears in 12 and the 12-bit wide parallel data that appears in 12 shift registers b1 to b12 of the second storage section B is input to the input terminal M.
is selected according to the mode selection command MS appearing in , and is supplied to 12 data output terminals 01 to 012.

In the circuit of FIG. 1, 1. The data for one frame is serially/parallel-converted into 17 parallel data groups each having a width of 12 bits and held by the 12 shift registers each having 17 stages constituting the second storage units A and B. The 17 pieces of parallel data held during serial/parallel conversion are read out from the corresponding storage units in synchronization with the 17 read clock signals CLK. Also, the above 1. Writing and reading data to and from the second storage units A and B are alternated every frame.

That is, as shown in the waveform diagrams of FIGS. 2 and 3, the first 12 bits of data [DI, D2 . D3...
D12] selector α1 according to the mode selection command MS.
~α12 is the selected write clock signal CKI~CK1
2, the signals are shifted into 12 shift registers a1 to a12. The subsequent 12 bits of data (DI3.DI4.DI5...) included in the low-order signal DT
D24] are shifted into the 12 shift registers a1 to a12 in synchronization with the write clock signals CKI to CK12. Thereafter, in the same manner, 12 bits of data included in the low-order signal DT are shifted into 12 shift registers a1 to a2 in synchronization with the write clock signal, and the last 12 bits of data (D393. D
394...D204), the writing of data for one frame is completed.

As shown in the waveform diagram of FIG. 3, the mode selection command MS on the input terminal M is inverted almost in synchronization with the end of writing for one frame, and the storage section B of the low-order signal for the next one frame is inverted.
Writing to starts.

Writing to this storage section B is performed in the same manner as writing to the storage section A described above. On the other hand, regarding the storage section A, as shown in the waveform diagrams of FIGS. 3 and 4, the input terminal CK
In synchronization with the 17 read clock signals CLK supplied to the
2...DI2), (DI3. DI4...
・D24〕 ...... (D393.D394...
...D204) is read out, and the data selectors γl to γ
12 and output to output terminals 01 to 012.

Similarly, when writing to the second storage section B is completed, writing to the first storage section A is started, and during this writing, reading from the storage section B is performed. The police box is repeated.

The case where the number of stages of shift registers is 17 and the number of shift registers is 12 has been illustrated above. However, the number of stages and the number of shift registers can be selected from other appropriate values depending on the amount of data, read/write speed, etc.

The embodiments of the multiplexing circuit of the present invention have been described above.

Since the demultiplexing circuit of the present invention has the same configuration as the multiplexing circuit described above, it is only necessary to reverse the write side and the read side, so a description of the embodiment will be omitted.

(Effects of the Invention) As explained in detail above, in the digital signal multiplexing circuit according to the present invention, each frame memory serially/parallel converts one frame's worth of data into a parallel data group of an appropriate bit width. The first . It consists of a second storage section, and the writing and reading of data to and from each storage section is done in one piece.
Since the structure is alternated every frame, it is simpler and cheaper than conventional circuits, and data destruction can be effectively prevented by separating the write position and read position by one frame or more. It is played.

Furthermore, the multiplexing/demultiplexing circuit of the present invention also provides the same effects as the multiplexing circuit described above.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a digital signal multiplexing circuit according to an embodiment of the present invention, FIGS. 2 to 4 are waveform diagrams for explaining the operation of the circuit in FIG. 1, and FIG. FIG. 1 is a block diagram showing the configuration of a conventional digital signal multiplexing circuit. A: first storage unit, B: second storage unit, α1~
α12...Shift register, b1-b12...Shift register, α1-α12. β1 to β12...Clock selector, γl to γ12...Data selector,
■...Input terminal for low-order signals to be multiplexed, C1-C1
2... Input terminal for write clock signal, CK... Input terminal for read clock signal, 01-012... Data output terminal. Patent applicant NEC Corporation (one other person) Agent
Patent Attorney Toshihiko Sakurai Figure 1 Figure 2 CK12 - ---''Remedy Figure 4 CLK -----]] He E and Mouth J

Claims (2)

[Claims] (1) In a digital signal multiplexing circuit that performs frame multiplexing by writing a frame-configured digital signal into a frame memory provided for each frame and reading it out at a higher speed than the writing speed, each of the frame memories has the following features: It consists of first and second storage units including a shift register group that serially/parallel-converts and holds one frame's worth of data into a parallel data group of an appropriate bit width, and outputs parallel data units. A digital signal multiplexing circuit characterized in that writing and reading data to and from a section are alternated every frame. (2) A digital signal demultiplexing circuit that performs frame demultiplexing by writing a frame-configured digital signal into a frame memory provided for each frame and reading it out at a slower speed than the writing speed, each of the frame memories having: It consists of first and second storage sections including a shift register group that stores one frame's worth of data consisting of a group of parallel data of an appropriate bit width while performing parallel/serial conversion and outputs it as serial data. A digital signal multiplexing/demultiplexing circuit characterized in that writing and reading data to and from a section are alternated every frame.