JPS62126435A - Speed conversion buffer circuit - Google Patents

Abstract

PURPOSE:To attain speed conversion with buffer capacity smaller than data length by partially superposing the writing time of data in a buffer memory to the reading time of data to control data write/read in/from the buffer mem ory. CONSTITUTION:The titled circuit is provided with a buffer memory 1 and a timing forming circuit 2 and the timing forming circuit 2 generates a timing signal on the slave timing side, e.g. the line side, synchronously with a timing signal on the master timing side, e.g. the high way side, and controls data writing/reading time in/from the buffer memory 1 so as to partially superpose these time synchronously with these timing signals. Since the succeeding data can be written in a part of areas whose reading is completed by writing/reading data in/from the buffer memory 1 so that data writing and reading time can be partially superposed, speed change can be attained with the buffer capacity less than that corresponding to the data length to be changed at its speed.

Description

[Detailed Description of the Invention] [Summary] The writing and reading of data to and from the buffer memory is controlled so that the time for writing data to the buffer memory and the time for reading data partially overlap to accommodate the overlapping time length. This makes it possible to reduce the buffer capacity required, and to convert the speed of data using a small-capacity buffer memory.

[Industrial application field]

The present invention relates to a speed conversion buffer circuit that converts data speed using an economical structure.

In a digital switching system, the data rate on the line side is, for example, 2.048 Mb/s, and the data rate on the highway side is, for example, 6.3 Mb/s, so there is a difference between the line side and the highway side. It is necessary to convert the speed of data between. Also in various information processing systems, when data is transferred between a low-speed device and a high-speed device, it is necessary to convert the data speed.

A speed conversion buffer circuit is used to convert the speed of such data.

[Conventional technology]

As a speed conversion buffer circuit, for example, FIFO (F
irst In First 0ut) memory,
Shift registers and the like are used. The data speed is converted by writing data at one speed and reading the data at the other speed. For example, in a digital switching system, when converting a line-side data rate to a highway-side data rate,
Data added at a predetermined timing of a frame on the line side is once written into a buffer, and after the writing is completed, the data is read out at a predetermined timing on the highway side and multiplexed.

[Problem that the invention seeks to solve]

In conventional speed conversion buffer circuits, data is written at one speed and after writing is completed, the data is read out at the other speed, so a buffer capacity corresponding to the data length is required. It was something to do. Therefore, there is a drawback that the speed conversion buffer circuit becomes large and expensive.

An object of the present invention is to perform speed conversion with a buffer capacity that is small compared to the data length.

[Means for solving problems]

The speed conversion buffer circuit of the present invention reduces the buffer capacity by controlling the write time and read time so that they partially overlap, and will be described with reference to FIG.

The timing generation circuit 2 includes a buffer memory 1 and a timing generation circuit 2, and the timing generation circuit 2 generates a timing signal on a secondary timing side, for example, a line side, in synchronization with a timing signal on a main timing side, for example, a highway side, and also generates a timing signal on a secondary timing side, for example, a line side. It has a configuration in which control is performed so that the writing and reading times of data to and from the buffer memory l partially overlap in synchronization with the timing signal.

[Effect]

By writing and reading data so that the times for writing and reading data to and from the buffer memory 1 partially overlap, it is possible to write the next data in the part of the area where the reading has finished, so speed conversion is possible. This means that the buffer capacity is smaller than the buffer capacity corresponding to the data length.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, in which 11 is a buffer memory, 12 is a timing generation circuit, 13 is a serial-to-parallel conversion circuit, 14 is a parallel-to-serial conversion circuit, and 15.16 is an AND circuit. This is a case of converting the speed of data between the line L side of low-speed data and the highway HW side of high-speed data.

The clock signal CLK1 and the timing signal TMI on the highway HW side are applied to the AND circuit 16, and its output signal is applied to the clock terminal C of the parallel-to-serial conversion circuit 14, and the output signal is applied to the clock terminal C of the parallel-to-serial converter circuit 14, and the 8-bit parallel data read from the buffer memory 11 is is added to the data terminal of the parallel-to-serial conversion circuit 14 and sent to the highway HW as serial data.

Also, the timing signal TMI is the clock signal C on the line L side.
It is added to the timing generation circuit 12 together with LK2, and a timing signal TM2 on the line L side is generated. This timing signal TM2 causes the serial data on the line L side to be applied to the data terminal of the serial/parallel conversion circuit 13, and the clock signal CLK2 and the timing signal TM on the line L side
2 is applied to the AND circuit 15, and its output signal is applied to the clock terminal C, converted into, for example, 8-bit parallel data, and applied to the buffer memory 11.

In synchronization with the timing signal TMI on the highway HW side,
The parallel-to-serial conversion circuit 14 sends out the data converted into serial data, and in synchronization with this timing signal TMI, a timing signal TM2 to the line L side is created, and in synchronization with this timing signal TM2, the data is transmitted from the line L side. The data is converted into parallel data by the serial/parallel conversion circuit 13 and added to the buffer memory 11 . The time for reading data from the buffer memory 11 to send it to the highway HW side and the time for writing the data added from the line L side are made to partially overlap, so that the time after the data is read from the buffer memory 11 is It controls writing the next data into the area.

Figure 3 is a block diagram of the main parts of the timing generation circuit.
21.22 is a flip-flop, 23 is a counter, 24
is a data length counter, and 25 is a NAND circuit. "1" is applied to the data terminal of the flip-flop 21, the timing signal TMI is applied to the clock terminal C, and the output signal of the NAND circuit 25 is applied to the clear terminal CL. Further, the signal from the output terminal Q is applied as an input signal to the J terminal of the flip-flop 22 and one of the NAND circuits 25.

The counter 23 is for frequency-dividing the clock signal CL2 on the line L side, for example, to 1/8, and the output signal of the counter 23 is applied to the clock terminal C of the flip-flop 22 and the data length counter 24. Further, the data length counter 24 presets the data length (byte length) added every frame period, counts the output signal of the counter 23, and adds the output signal based on the preset data length count to the terminal of the flip-flop 22. , outputs the output signal of the output terminal Q of the flip-flop 22 as a timing signal TM2 to the line L side, and adds it as the other input signal of the NAND circuit 25.

FIG. 4 is an explanatory diagram of the operation, where ta) is the timing signal TMI on the highway HW side, and (b) is the flip-flop 2.
1, (C) is the timing signal to the line L side, (d) is the output signal of the counter 23, and +e) is the output signal of the data length counter 24.

The output terminals Q of the flip-flops 21 and 22 are respectively “
0'', as shown in (a), the timing signal TMI on the highway HW side is output from the flip-flop 21.
is applied to the clock terminal C of the flip-flop 2.
The output terminal Q of the flip-flop 22 becomes "L" as shown in (C), and the output signal of the counter 23 shown in (dl) is applied to the clock terminal C of the flip-flop 22. As a result, the output signal of the NAND circuit 25 becomes "0", the flip-flop 21 is cleared and the output terminal Q becomes "O".
becomes. That is, the output terminal Q of the flip-flop 21 is (
The signal shown in b) will be output.

Further, since the data length counter 24 applies an output signal based on the precented data length count to the terminal of the flip-flop 22, the output terminal Q of the flip-flop 22 becomes "O" by the next output signal of the counter 23.

FIG. 5 is an explanatory diagram of the speed conversion operation, and shows a case where the data rate on the highway HW side is 6.3 Mb/s, the data rate on the line L side is 2.048 Mb/s, and the data length is 16 bytes. In the same figure (al is Highway H
The successive output time of data in the frame on the W side, (b) shows the writing time of data on the line L side, and is set so that they partially overlap. Further, (C) is the timing signal TMI on the highway HW side, (d) is the data succession time on the highway HW side showing an enlarged view of (a), and (e) is the timing signal TM2, (fl, (g) on the line L side). ) indicates the writing time of data on the line L side, which is shown by enlarging fb).

The timing signal TM2 on the line L side is created based on the timing signal TMI on the highway HW side, and when the timing signal TMI rises at time t1, the output signal of the counter 23 in FIG. When applied to the clock terminal C of the flip-flop 22, the timing signal TM2 is output to the line L side as shown in (li), and the data on the line L@ is written as shown in ([). However, depending on the time relationship between the rise of the output signal of the flip-flop 21 and the output signal of the counter 23, the timing signal TM2 to the line L side may be delayed by one byte from time t1. ,(
Writing of data on the line L side is started as shown at gl. That is, if) and (g) indicate that the writing time of data on the line L side is delayed by a maximum of 1 byte.

In the first frame, even if data reading on the highway HW side is started, since no data has been written to the buffer memory 11, invalid data will be read. Therefore, data reading is started from time t1, and the buffer memory 11 is cleared at time t2 when the 16th byte of data is read to the parallel-serial conversion circuit. Note that the timing signal TMI falls at time t3 when 16 bytes of data have been read out to the highway. Data writing on the line L side is started by the timing signal TM2, and in the first frame, 4 to 5 bytes from the beginning are used as dummy data. Therefore, at time t2, when the buffer memory If is cleared, the dummy data is cleared.

Data reading on the highway HW side ends at time t3,
Timing signal TM2 on the line L side is at time t1 or t5
If the rising edge occurs at time t4 or t6, the data is written at time t4 or t6.
A total of 16 bytes of data are written, and 12 or 13 bytes of data remain in the buffer memory 11 in the first frame.

This remaining data is read out during the data succession time of the next frame, and since 4 or 3 bytes of data are written during that data succession time, that data is also read out, for a total of 16 bytes.
Byte data will be read. And 12
Alternatively, 13 bytes of data will remain in the buffer memory 11 again. That is, in (al, (bl) of FIG. 5, the data according to the data write time shown in (b), which is shaded, is read out during the data read time shown in (a), which is shaded). Therefore, the buffer memory 11 only needs to have a capacity of 13 bytes, and one frame has a capacity of 16 bytes.
It is possible to perform speed conversion of byte data.

Although the buffer memory 11 described above has a configuration in which 8 bits are written and read in parallel, it is also possible to use a buffer memory configured to write and read serial data. Furthermore, it is of course possible to set the write/read data length per frame to a length other than 16 bytes, and the write address and subsequent address of the buffer memory 11 may be controlled by various known means. can be adopted. Furthermore, it can be applied not only to converting low-speed data to high-speed data but also to converting high-speed data to low-speed data.

〔Effect of the invention〕

As explained above, the present invention generates the timing signal TM2 on the low-speed data side such as the line L side in synchronization with the timing signal TMI on the high-speed data side such as the highway HW side, and generates the timing signal TM2 on the low-speed data side such as the line L side. .7M2 is synchronized with the buffer memory 1.11 to write and read data to convert the data speed, and in that case, the timing is created so that the data writing and reading times partially overlap. Timing signals are created in circuits 2 and 12, making it possible to reduce the amount of data due to the partial overlap between data writing time and continuous output time from buffer memory 1.11, and creating a buffer with a small capacity. Since data speed conversion can be performed using the memories 1 and 11, there is an advantage that the configuration is economical.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is a block diagram of the main part of the timing generation circuit, Fig. 4 is a diagram explaining operation, and Fig. 5 is a speed diagram. FIG. 3 is an explanatory diagram of conversion operation. 1.11 is a buffer memory, 2 and 12 are timing generation circuits, 13 is a serial-to-parallel conversion circuit, 14 is a parallel-to-serial conversion circuit, 15. -16 is an AND circuit.

Claims (1)

[Claims] In a speed conversion buffer circuit that converts the speed of existing data every frame period between transmission lines having different information transmission speeds, a buffer memory (1) that writes and reads the data.
and generating a timing signal for a side that operates at a secondary timing in synchronization with a timing signal for a side that operates at a main timing, and writing and reading data to and from the buffer memory (1) in synchronization with each timing signal. Timing creation circuit (2) that controls the times so that they partially overlap
A speed conversion buffer circuit comprising: