JPH0731530B2 - Synchronous control NC device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a synchronous control numerical control device, and in particular, it is composed of a plurality of units, of which data is transferred between a main unit and a slave unit, and The present invention relates to a numerical control (hereinafter referred to as NC) device in which a unit controls a mechanism while synchronizing with a constant control cycle.

(Prior Art) An NC device has a plurality of units inside, and performs data communication between the units and controls the machine while synchronizing with each other at a constant control cycle.

A method of data communication and synchronization of the NC device according to the prior art will be described with reference to FIG.

The NC device is composed of a main unit 10 and a slave unit 20, and the main unit 10 includes a control command circuit 11 for controlling the entire NC device and each unit in the NC device for operating at a constant control cycle. First sync signal that signals timing
A synchronous control circuit 12 that outputs FS, a transmission data buffer 13 for storing control data for the control command circuit 11 to instruct another unit, and data TD of this transmission data buffer 13 as transfer data TRD And a transmission circuit 14 for outputting to. The slave unit 20 receives the first synchronization signal FS from the master unit 10, operates in the same control cycle as the master unit 10 and controls a machine (not shown), and a master unit 21. Transfer data TRD from 10 is received, and main unit 1 is received in receive data buffer 23.
It comprises a receiving circuit 22 which outputs control data CD from 0, and the receiving data buffer 23 stores the control data CD until the machine control circuit 21 becomes necessary for operation.

The operation of such a configuration will be described with reference to the timing chart of FIG.

The control command circuit 11 is triggered by the time point t _{1 at} which the first synchronization signal FS changes from “0” to “1” as shown in FIG. 4 (A).
Writes the control data in the transmission data buffer 13 as shown in FIG. After the writing of the control data is completed (time point t ₂ ), the transmission circuit 14 sends the data TD of the transmission data buffer 13 to the slave unit 20 as the transfer data TRD (state) as shown in FIG. 4 (C). The receiving circuit 22 of the slave unit 20 sends the contents of the transfer data TRD, that is, the control data to the fourth data.
As shown in FIG. 7D, the received data buffer 23 is written (state), and at the time t ₄ when the next first synchronization signal FS changes from “0” to “1”, the machine control circuit 21 shows the same (E) in FIG. As described above, the control data CD is read from the reception data buffer 23 (state), and at the same time, the control command circuit 11 in the main unit 10 writes the next control data in the transmission data buffer 13 as shown in FIG. After that, the above operation is repeated.

Here, the transfer data TRD starts to be transferred after a certain time delay from the time point when the first synchronization signal FS changes from "0" to "1". This is because the control command circuit 11 is in the control state of the machine. Accordingly, it is the time required to generate the control data, and these times T ₁ , T ₂ , and T ₃ are not necessarily the same. However, the maximum time Tmax is defined so that the transfer of the transfer data TRD is completed before the next change of the first synchronization signal FS from "0" to "1", and the reception by the slave unit 20 side Data buffer
The minimum time Tmin is defined so that the transfer does not start until the reading of 23 is completed.

(Problems to be Solved by the Invention) As described above, the main unit 10 has two types of the first synchronization signal FS for notifying the slave unit 20 of the synchronization timing and the transfer data TRD for transmitting the control command. It is necessary to send each signal of. Therefore, there is a problem that the number of signal lines inside the NC device increases, a space for wiring processing is required, and the cost of wiring increases.

The present invention has been made under the circumstances as described above, and an object of the present invention is to send two kinds of signals, a synchronization signal and transfer data, by one signal in order to solve the above-mentioned drawbacks in the prior art. (EN) Provided is a synchronous control NC device including a master unit and a slave unit capable of performing the same.

(Means for Solving the Problem) The present invention comprises a plurality of units, a synchronous control in which a main unit and a slave unit among them perform data operation, and each unit controls a machine while synchronizing with each other. The above object of the present invention relates to an NC device, wherein data transferred from the master unit to the slave unit is transferred at the same cycle of a first synchronization signal inside the master unit, and the slave unit is transferred from the master unit. A second synchronization signal having the same cycle as the first synchronization signal is extracted based on the transferred data, and the second synchronization signal is delayed for a certain period to have the same cycle as the first synchronization signal. By generating the third synchronization signal that changes at the same timing, the main unit and the slave unit are synchronously controlled at the same cycle and at the same timing. It is made.

(Operation) As is clear from the timing chart of FIG. 4, the transfer data TRD is transferred only once during the period T of the synchronization signal FS. Although the transfer cycle of the transfer data TRD is not constant in FIG. 4, the time until the writing of the control data in the transmission data buffer 13 and the minimum time Tmin are guaranteed, and the transfer data TRD has the first time within a range not exceeding the maximum time Tmax. The operation is not affected even if the transfer start time of the transfer data TRD is fixed at the time when the synchronization signal FS of changes from "0" to "1". Transfer data TRD
Of the synchronization signal FS, the slave unit 20 side generates a second synchronization signal that changes from “0” to “1” at the start of the transfer data TRD. Can be delayed appropriately to obtain a third synchronization signal that changes at the same cycle and at the same timing as the first synchronization signal FS on the main unit 10 side on the slave unit 20 side.

(Embodiment) The configuration of the present invention will be described with reference to FIG. 1 shown in correspondence with FIG.

The main unit 10 includes a control command circuit 11, a synchronous control circuit 12 that outputs a first synchronization signal FS, a transmission data buffer 13 that stores control data from the control command circuit 11, and a data TD of this transmission data buffer 13. As the transfer data TRT, the transmission circuit 15 starts the transfer after the time T ₀ from the time when the first synchronization signal FS changes from “0” to “1” and outputs the data to the outside. In addition, the slave unit 20 uses the transfer data TR
Upon receiving T, the second synchronization signal SS that changes from “0” to “1” is output at the start of the transfer data TRT, and the content of the transfer data, that is, control data is received and output to the reception data buffer 23. The receiving circuit 22, the delay circuit 24 for delaying the second synchronizing signal SS and outputting the third synchronizing signal TS that changes at the same timing as the first synchronizing signal FS, and the third synchronizing signal TS are received. It consists of a machine control circuit 21 that operates in the same control cycle as the main unit 10 and controls the machine, and a reception data buffer 23 that stores control data until the machine control circuit 21 is required for its operation. Has been done.

The operation of such a configuration will be described with reference to the timing chart of FIG.

As shown in FIG. 2 (A), the first synchronizing signal FS is a synchronizing signal having a period T, and is triggered by a time point t ₁₀ when the first synchronizing signal FS changes from “0” to “1”. The control command circuit 11 writes the control data in the transmission data buffer 13 within the time T ₀ as shown in FIG. At time t ₁₁ after the time T ₀ , the transmission circuit 15 sends the data TD of the transmission data buffer 13 to the slave unit 20 as the transfer data TRT as shown in FIG. 2C (state B). The receiving circuit 22 of the slave unit 20 transfers the transfer data TR
Simultaneously with the start of reception of T, that is, at time t ₁₁ , a second synchronization signal SS changing from “0” to “1” is generated and output as in FIG. 2D (state C). Then, the delay circuit 24 delays the second synchronization signal SS by the time T ₁₀ (= T−T ₀ ) at the time point t.
The third synchronizing signal TS is generated and output at ₁₂ as shown in FIG. 2 (E) (state D). By the above operation, the third synchronization signal TS is time T ₀ + T ₁₀ = T ₀ + T with respect to the first synchronization signal FS.
-T ₀ = T, that is, a signal delayed by one cycle, and the first synchronization signal FS and the third synchronization signal TS apparently have the same cycle and change at the same timing.

The operation of writing and reading to / from the reception data buffer 23 is exactly the same as that of the conventional technique (FIG. 2 (F),
(See (G)).

(Effect of the Invention) As described above, according to the present invention, it becomes possible to send the synchronization signal and the transfer data by one signal, the number of signal lines inside the NC device can be reduced, and the electric wire processing space and cost can be reduced. It is possible to realize an NC device that suppresses this.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
FIG. 4 is a timing chart showing an example of its operation, FIG. 3 is a block diagram showing an example of a conventional device, and FIG. 4 is a timing chart showing an example of its operation. 10 ... Main unit, 11 ... Control command circuit, 12 ... Synchronous control circuit, 13 ... Transmission data buffer, 14,15 ... Transmission circuit, 20 ... Slave unit, 21 ... Machine control circuit, 22 ... … Reception circuit, 23 …… Reception data buffer, 24 …… Delay circuit.

Claims (1)

[Claims] 1. A plurality of units, of which data transfer is performed between a master unit and a slave unit,
In a synchronous control numerical control device for controlling the machine while each unit synchronizes, the data transferred from the master unit to the slave unit is transferred at the same cycle as the first sync signal in the master unit, Extracts a second synchronization signal having the same cycle as the first synchronization signal based on the data transferred from the main unit,
By delaying the synchronization signal of No. 2 for a certain period of time, a third synchronization signal that changes at the same cycle and at the same timing as the first synchronization signal is generated, thereby making the main unit and the slave unit have the same cycle and the same timing. Synchronous control numerical control device characterized in that synchronous control is performed by.