JPS63120355A - Bus interface circuit - Google Patents

Abstract

PURPOSE:To shorten the transfer time of data by switching the clock of a main circuit to a bus clock from a reference clock in case a synchronizing bus gives a request to the main circuit for transmission/reception of data. CONSTITUTION:When no request is received from a synchronizing bus 1 for transmission/reception of data, a main circuit 2 works synchronously with a reference clock (y). Thus a switch control circuit 44 outputs a switch signal (f) so that a switch circuit 43 selects the clock (y) as a main circuit clock (z). When a request is received from the bus for transmission/reception of data, the circuit 2 is actuated synchronously with a bus clock (x). Then the circuit 44 outputs the signal (f) so that the circuit 43 selects the clock (x) as the clock (z). Then the clock (z) is switched to the clock (x) from the clock (y). In this case, it is required to secure a period during which both clocks (x) and (y) are not selected so that no noise is produced to the clock (z). This period of time is set the value equal to a single clock pulse at the longest.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a bus interface circuit for a synchronous bus.

(Prior Art) A conventional configuration of this type of bus interface circuit is shown in FIG. 4. In this figure, 1 is a synchronous bus that operates in synchronization with the bus clock A bus interface circuit 4 is provided to exchange data between the synchronous bus 1 and the main circuit 2. Conventionally, this bus interface circuit 4 includes a synchronization circuit (1) 41 for synchronizing the data output from the synchronous bus 1 with a clock y used on the main circuit 2 side, and a synchronization circuit (1) 41 for synchronizing the data output from the synchronous bus 1 with the clock y used on the main circuit 2 side. and a synchronization circuit (2) 42 for synchronizing the clock signal X with the clock X used on the synchronous bus 1 side.

With this configuration, as shown in flowchart 1- of FIG.
A data transmission request signal a output from the synchronous bus 1 in synchronization with the bus clock X is sampled by the synchronization circuit (1) 41 at the falling edge of the main circuit clock y and converted into a synchronization request signal %b. Ru.

The main circuit 2, which has received the synchronization request signal S, makes the response signal C valid when the data e can be made valid at the next falling edge of the main circuit clock y. After data e becomes valid,
The synchronization circuit (2) 42 generates a synchronization response signal d synchronized with the bus clock X. The synchronous bus 1 that has received the synchronization response signal d receives data e and disables the request signal a. Due to this.

The synchronization circuit (1) 41 disables the synchronization request signal in synchronization with the reference clock y. Main circuit 2 requests synchronization (
After the signal becomes inactive, the response signal C is made inactive and the transmission of data e is completed. Since the response signal C has become ineffective, the synchronization circuit (2) 42 receives the synchronization response signal %.
d is disabled in synchronization with the path clock X. The synchronous bus 1 completes the data reception operation when the synchronization response signal d becomes inactive.

(Problems to be Solved by the Invention) However, the above conventional bus interface circuit 4
Since it is configured using two synchronization circuits 41 and 42, there is a problem that it takes time to convert the request signal a to b and the response signal C to d, which increases the data transfer time. There was a point.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a bus interface circuit that reduces data transfer time.

[Structure of the Invention] (Means for Solving the Problems) The bus interface circuit i of the present invention includes a switching circuit that switches from a pass clock to a reference clock in response to a switching signal, and a transmission request signal output from a synchronous bus. The switching control circuit outputs the switching signal to the switching circuit in response, and inputs the transmission request signal to the main circuit in synchronization with the clock output from the switching circuit.

(Function) With the above configuration, when there is a data transmission/reception request from the synchronous bus, the main circuit clock is switched from the reference clock to the pass clock, eliminating the synchronization process of the request signal and response signal, and the data Transfer time can be shortened.

(Example) Hereinafter, the present invention will be described in detail based on the example shown in the drawings. FIG. 1 shows an embodiment of the bus interface circuit of the present invention. In the figure, the same reference numerals as in FIG. 4 indicate the same or corresponding parts, and the difference from the configuration in FIG. 2 as pass clock X or reference clock y
The bus interface circuit 4 is configured by providing a switching circuit 13 for switching to a switching circuit 13, and a switching control circuit 44 for generating a switching signal f for the switching circuit 43.

With this configuration, as shown in the time chart of FIG. 2, when there is no data transmission/reception request from the synchronous bus 1, the switching control circuit 44 operates the main circuit 2 in synchronization with the reference clock y. The circuit 43 outputs a switch 43 f that selects the reference clock y as the main circuit clock Z. When there is a data transmission request signal a from the synchronous bus 1, the switching control circuit 44 operates the main circuit 2 in synchronization with the bus clock X, so that the switching circuit 43 uses the pass clock as the main circuit clock Z. A switching signal f for selecting X is output.

Pass clock X from main circuit clock 2 to reference clock y
In order not to generate noise in the main circuit clock 2 when switching to the main circuit clock 2, it is necessary to provide a time period in which neither clock is selected. This time requires a maximum of 1 clock as the path clock X. shall be.

At the same time, when the data transmission request signal a becomes valid, the switching control circuit 44 inputs a request signal b' to the main circuit 2 in synchronization with the main circuit clock 2 output from the switching circuit 43.

The main circuit 2 makes the response signal C valid when the data e to be transmitted can be made valid at the next falling edge of the main circuit clock 2. Since the response signal C is a signal synchronized with the path clock, it is directly returned to the synchronous bus 1. The synchronous bus 1 receives data at the falling edge of the pass clock and also disables the request signal a.

When the request signal a becomes ineffective, the switching control circuit 44 disables the main circuit request signal b' in synchronization with the main circuit clock 2. Since the request signal b' becomes inactive, the main circuit 2 makes the response signal C inactive and completes the transfer of the data e.

Next, the response signal C becomes inactive and the synchronous bus 1
When the completion of the first data transfer is known, in order to request the second data transfer, the request signal a is again sent to the bus clock
Sync and enable. but.

If request signal a remains inactive at this point,
Since the data transfer is now completely completed, the switching circuit 43 selects the reference clock y again and outputs it as the main circuit clock Z.

When the request signal a becomes valid, the switching control circuit 44
sends the request signal b' to the main circuit 2 in synchronization with the main circuit clock 2.
Thereafter, the second data e is transferred in the same manner as described above.

As can be seen from the above description, in order for the main circuit clock 2 to switch from the reference clock y to the bus clock X without generating noise, it takes at most one clock of the bus clock X. Therefore, during the first data transfer, the data transfer time is increased by the time required for this clock switching, but from the second time onwards, this switching time is eliminated and the data transfer time is further shortened.

In this way, according to this embodiment, the time required for synchronizing the request signal and the response signal, which was necessary in the conventional bus interface circuit, is almost no longer required, so the time required for data transfer is reduced to data access. It will only be time,
Data transfer time can be significantly reduced.

3 shows another embodiment of the present invention. In FIG. 0, the same reference numerals as in FIG. 1 indicate the same or corresponding parts, and
The difference from the figure is that the main circuit 2 is replaced with a memory 2', the reference tarlock generator 3 is replaced with another synchronous bus, and the synchronous bus 1 is replaced with two synchronous buses 11 and 12.

The bus interface circuit 4 also has a memory clock 2.
A switching circuit 43 for switching the bus clock X' of the synchronous bus (1) 11 or a bus clock y' for the synchronous bus (202), and a switching control circuit 44 for generating a switching signal f.

In this configuration, synchronous bus (1) 11 and synchronous bus (
2) In response to access request signals a1 and a2 from 12, the switching control circuit 44 outputs a switching control signal f to the switching circuit 43 so as to select the bus clock of the bus to which access rights have been granted as the memory clock. Since the memory operations based on access requests from the two buses are synchronized with the respective bus clocks, there is no time to synchronize the access request signal and the response signal C, and the access time can be shortened.

[Effects of the Invention] As described above, according to the present invention, synchronization processing of data sent and received between the synchronous bus and the main circuit is almost unnecessary, and data transfer time can be significantly shortened.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a bus interface circuit showing one embodiment of the present invention, FIG. 2 is a timing diagram for explaining FIG. 1, and FIG. 3 is a bus interface showing another embodiment of the present invention. A block diagram of the circuit, Figure 4 is a block diagram of a conventional bus interface circuit, and Figure 5 is a block diagram of the conventional bus interface circuit.
The figure is a timing diagram for explaining FIG. 3. 1.11.12...Synchronous bus, 2...Main circuit. 3... Reference clock generator, 4... Bus interface circuit, 41.42... Synchronization circuit, 43...
- Switching circuit, 44... switching control circuit.・' ＼ Agent Patent Attorney Crest 1) Makoto...' )゛Mata-/ Figure 1Xrtl > ゝD u Φ -N 3rd
Figure 4

Claims (1)

[Claims] In a bus interface circuit between a synchronous bus that operates in synchronization with a first clock and a main circuit that operates in synchronization with a second clock during normal operation, the first clock is switched in response to a switching signal. a switching circuit that switches from the synchronous bus to the second clock, and outputs the switching signal to the switching circuit in response to a transmission request signal output from the synchronous bus, and outputs the transmission request signal from the switching circuit. A bus interface circuit comprising: a switching control circuit that inputs data to the main circuit in synchronization with a clock.