JPS6411980B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a bus transfer circuit, and particularly to a bus transfer circuit that transmits and receives signals via a bus in synchronization with a clock.

[Prior art]

In conventional bus transfer circuits, the transmitting holding circuit and receiving holding circuit connected to the bus were operated by a single periodic clock. If the minimum delay time to the circuit is smaller than the sum of the hold time of the transmitting holding circuit and the clock skew, racing will occur and the signal will not be transferred from the transmitting holding circuit to the receiving holding circuit, especially the signal between the buses. The minimum delay time of the transfer time is small, and if the skew is large compared to the clock cycle, racing may occur.

That is, in the conventional example, referring to FIG. 1, an information signal 4 is set in a first register 1 by a clock 8, outputted as an information signal 5, and given to a bus 2, and an information signal 6 output from the bus 2 is set. It is set in register 3 by clock 9, and register 3 outputs information signal 7.

In this case clocks 8 and 9 are cycle time
_However , if clock 9 has a clock skew of ±ΔT _c compared to clock 8, then the following relationship is satisfied between signal 6, which is the input of holding circuit 3, and clock 9. Then, signal transfer will occur normally.

t _ipdMIN +Td _MIN >ΔT _c +t _2hpld (1) t _ipdMAX +Td _MAX <T _c −t _2setup −ΔT _c (2) However, t _ipdMIN , t _ipdMAX ; Information signal 5 is output from clock 8 of first register 1, respectively. Minimum and _maximum delay _time from when information signal 5 is given to bus 2 until information signal 6 is output, _Tc , ± _ΔTc ; The cycle time of clocks 8 and 9 and the timing skew of clocks 8 and 9, respectively, t _2setup and t _2hpld ; the setup time and hold time of second register 3, respectively. The relationship between clocks 8, 9,
As shown for information signal 6, it can be seen that as the clock skew ±ΔT _c increases, the hold time indicated by equation (1) becomes severe.

[Purpose of the invention]

An object of the present invention is to eliminate such drawbacks of the conventional ones and to transfer information signals synchronized with a periodic clock between a transmitting holding circuit and a receiving holding circuit via a bus. The object of the present invention is to provide a bus transfer circuit that prevents racing.

[Structure of the invention]

The present invention includes a signal bus, a holding circuit connected to the signal bus and transmitting an output signal, a holding circuit connected to the signal bus receiving an input signal, and a periodic clock for setting both holding circuits. In bus transfer circuits including clock circuits that generate
At least two receiving or transmitting holding circuits are provided, and the clock circuit alternately sets one of the two holding circuits by generating a low frequency clock synchronized with the periodic clock. and means for alternately outputting the outputs of these two holding circuits at low frequency timing synchronized with the clock,
The corresponding clocks for setting the transmission holding circuit and the reception holding circuit are arranged in a time relationship that does not cause racing.

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 4 shows its operating waveform diagram, where 1 is the first register, 2 is the bus, 4, 5, and 6 are information signals, and 8 and 9 are the clocks. , 10 is a third register which receives the information signal 6 and the complement output 23 of the second flip-flop 15 and outputs the information signal 25;
11 is a fourth register which receives the information signal 6 and the output 24 of the second flip-flop 15 and outputs the information signal 26; 12 receives the information signals 25 and 26 and the output 22 of the first flip-flop 14; A selection circuit 13 receives the clock 9 as an input and an inverted clock 20 as an output. 14 receives the clock 9, its own complement output 21, and a reset signal 30 as inputs, and outputs 22 and 27. A first flip-flop 15 has a complement output 21 as its output, and a second flip-flop 15 has an inverted clock 20, its own inverted output 23 and a reset signal 30 as inputs, and has an output 24 and a complement output 23 as its outputs.

Next, the operation of the embodiment of the present invention will be explained with reference to FIGS. 3 and 4.

First, the first flip-flops 14 and 15
is reset by a reset signal 30. Then, when clocks 8 and 9 are applied as clocks 8 and 9 in FIG. 4, first register 1 in FIG. 3 outputs information signal 6 via bus 2 after setting information signal 4. However, on the other hand, clock 9
The inverting clock 20 of the second flip-flop 1
5 and by making the output 23 the data input of the second flip-flop 15, the output 2
3 and 24 are inverted every clock, and the output 2
3 and 24 are output as shown in FIG. These outputs 23, 24 (low frequency clocks made from clock 9) are input as clocks for the fourth register 11 and the third register 10, and the information signal 6 is alternately sent to the fourth register 11 and the third register 10. and outputs information signals 26 and 25. Furthermore, the clock 9 is connected to the first flip-flop 1.
4 and by making the output 21 the data input of the first flip-flop 14, the output 2
2 The low frequency timing created from clock 9 is set to 1.
It is inverted every clock and outputs the output 22 shown in FIG. 4, which is given to the selection circuit 12.
The information signal 27 is converted into the information signal 2 as shown in FIG.
6 and 25 are selected and output alternately.

In this case, the conditions for correctly setting the information signal 6 in the third register 10 or the fourth register 11 are as follows.

t _ipdMIN +Td _MIN +(T _c −Tφ) −ΔTφ＞t _hpld (1)′ t _ipdMAX +t _dMAX ＜Tφ−t _setup −ΔTφ (2)′ However, Tφ, ±ΔTφ; From clock 8 of outputs 23 and 24, respectively delay time and output 23,2
4 skew, _thpld , _tsetup ; 3rd and 4th register 1, respectively
Comparing equations (1) and (2) with equations (1)' and (2)' for setup and hold times of 0 and 11, the hold time is improved because T _c −Tφ>0, and the setup time is improved. Since T _c >Tφ, there is no margin, but it can be seen that in the receiving register, which does not have a margin for the hold time, the operating margin increases and racing can be prevented.

In the above explanation, we have shown a circuit for improving the bus reception register when the signal transfer time between the buses is short and the clock skew is large compared to the clock cycle. If the delay time of the bus is large compared to the clock cycle and racing occurs in the bus reception holding circuit, two holding circuits may be provided in the same way, and the delay time of the bus may be delayed by one or more clocks. After setting the holding circuit according to the time, the output thereof may be alternately outputted by the selection circuit.

Furthermore, in the embodiment of the present invention, two sets of holding circuits are provided on the receiving circuit side via the bus, but after they are provided on the transmitting circuit side and set alternately, the selection circuit is set by the clock of the holding circuit on the receiving side. The holding circuit may be operated to output two sets of holding circuit outputs to the bus.

〔Effect of the invention〕

As explained above, the present invention is applicable to the case where information signals are transferred between a transmitting holding circuit and a receiving holding circuit via a bus in synchronization with a periodic clock.
By providing two holding circuits for either one, setting them alternately using a low frequency clock, and alternately selecting the outputs of these two circuits at low frequency timing, it is effective to prevent racing. This has the effect of providing a circuit suitable for.

[Brief explanation of drawings]

Figure 1 is a block diagram of an example of a conventional system;
3 is a block diagram of an embodiment of the present invention, and FIG. 4 is a diagram explaining the operation. 1...First register, 2...Bus, 3...Second register, 4, 5, 6, 7, 25, 26...
Information signal, 8, 9...Clock, 10...Third register, 11...Fourth register, 12...Selection circuit, 13...Inverting circuit, 14...First flip-flop, 15...Flip-flop 2 flip-flop, 20...inverted clock, 21...first flip-flop complement output, 22...first
flip-flop output, 23... second flip-flop complement output, 24... second flip-flop output.

Claims (1)

[Claims] 1. Generates a signal bus, a holding circuit connected to the signal bus to transmit an output signal, a holding circuit connected to the signal bus to receive an input signal, and a periodic clock for setting both holding circuits. In a bus transfer circuit including a clock circuit, at least two circuits of either a reception or transmission holding circuit are provided, and the clock circuit holds the two circuits by simultaneously generating a low frequency clock synchronized with the periodic clock. The transmitting holding circuit and the receiving holding circuit include means for alternately setting either one of the circuits, and means for alternately outputting the outputs of these two holding circuits at low frequency timing synchronized with the clock. A bus transfer circuit characterized in that the corresponding clocks to be set have a time relationship that does not cause racing.