JP2002351818A - Bus control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve transfer efficiency in a system equipped with at least two layers of buses by eliminating synchronizing circuit of target device which is to be a transfer target by making a master device connected with one side of bus capable of changing a clock synchronizing signals depending on the transfer destination of the output data. SOLUTION: A function for decoding a transfer destination address is set up at a bus bridge which delivers a transfer from a primary bus to a secondary bus. The number of times of synchronization occurring at one time of transfer is reduced by eliminating synchronization circuits inside of a transfer destination device through selecting dynamically a clock synchronizing a signal line which outputs in accordance with the result of decoding. Furthermore, a function to select the clock to synchronize the signal to be outputted to the secondary bus inside of an arbiter which adjusts transfer requirement of the secondary bus and a plurality of masters become connectable to the secondary bus without setting up the synchronization circuit inside the device of transfer destination.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control for a computer system having a bus operating at a plurality of different frequencies.

[0002]

2. Description of the Related Art In a system requiring a high-speed operating frequency for a processor, a relatively low-speed bus for connecting peripheral devices and the like is prepared separately from a high-speed processor bus for connecting a processor and a storage device. There is a method of realizing an increase in the operating frequency of the processor bus by reducing the number of connected devices. The bus connecting a plurality of devices is generally a clock synchronous bus, but the devices connected to the low-speed bus are diversified in terms of both function and maximum operating frequency, and have a single frequency. In order to connect a plurality of devices to the clock synchronous bus, a method is adopted in which the operation clock of the device is the same as the bus clock or a synchronization circuit is provided on the device side. In general, devices to be connected can be operated at their respective maximum frequencies. Therefore, it is considered that a system provided with a synchronization circuit has better performance of the entire system.

FIG. 2 shows an example of the configuration of a system having a bus hierarchical structure in which a synchronization circuit is provided on the device side. In FIG. 2, 101 is a synchronous primary bus, 102 is a synchronous secondary bus operating at a frequency different from that of the primary bus 101,
103 is a processor connected to the primary bus 101,
A master device 104 outputs a transfer request connected to the primary bus 101, a target device 105 receives a transfer request connected to the primary bus 101,
06 transfers the transfer request generated on the primary bus 101 to the secondary bus 1
02, a bus bridge for transmitting a clock to each device; 107, a clock supply unit for supplying a clock to each device;
Target devices A and 109 connected to the secondary bus 102 and operating on the clock A are connected to the secondary bus 102,
A target device B 114 operating on the clock B is a clock X operating on the primary bus 1, and 201 is a secondary bus 1 on the secondary bus 1.
Clocks Y and 115 for operating the target device 02 are clocks A and 116 for operating the target device A 108, and a clock 116 for operating the target device B 109 is clock B. Here, clock X114, clock Y201, clock A
The clock 115 and the clock B 116 are independent clocks having different frequencies, and it is assumed that the clock X114 has the highest frequency among the four types of clocks. Also, 111
Is a signal synchronized with the clock X114 for operating the primary bus 101 and the clock Y201 for operating the secondary bus 102.
The signal synchronized with the clock Y201 for operating the secondary bus 102 is transmitted to the clock X114 for operating the primary bus 101.
A synchronization circuit for synchronizing a signal synchronized with the clock Y201 to the clock A115, and a synchronization circuit synchronizing a signal synchronized with the clock A115 to the clock Y201, respectively, and 203 a clock Y20.
1 to the clock B116 and the clock B1
16 is a synchronizing circuit for synchronizing a signal synchronized with 16 with a clock Y201. Target device A108
A device that operates with a clock different from the operation clock of the bus to be connected, such as the target device B109 and the target device B109, includes synchronization circuits 202 and 203, and outputs a signal that operates with the operation clock of each device to the bus clock Y.
It is necessary to synchronize and output the signal synchronized with the bus clock Y201 and to use the signal synchronized with the input bus clock Y201 with the operation clock of each device.

Next, the processor 10 on the primary bus 101
3 and the target device A10 on the secondary bus 102
8 will be described with reference to FIG.
The transfer request generated by the processor 103 is issued on the primary bus 101 by specifying the transfer destination to the target device A108. Upon receiving the transfer, the bus bridge 106
To transfer the transfer to the secondary bus 102, the primary bus 101
Are synchronized by the synchronization circuit 111. By passing through the synchronization circuit 111, the signal is synchronized with the operation clock Y201 of the secondary bus 102 and is issued on the secondary bus 102. In the secondary bus 102, the synchronization circuit 1 receives the transfer from the target device A108, which is the transfer destination, and operates the received signal with the clock A115.
12 to synchronize.

In the system as shown in FIG. 2, each target device must have a synchronization circuit, so that the logic scale and power consumption increase. In addition, when each target device passes through the synchronization circuits of both the target device and the bus bridge, , The transfer efficiency is reduced. As a means for solving these problems, a method described in JP-A-6-83770 in which devices having different operating frequencies are connected to the same bus can be considered. In the method described in Japanese Patent Application Laid-Open No. 6-83770, when a plurality of devices having different operation frequencies share an address bus and a data bus, a command generation circuit for generating a command synchronized with the operation frequency of each device is provided. The transfer is performed in such a manner that a command is sent to each device, a data transmission / reception end signal from the device is received, and the transfer is terminated. If this method is used, when a bus having a simple protocol for transmitting and receiving only one type of data with one address output is adopted as the secondary bus, the synchronization circuit on the device side can be eliminated. is there.

[0006]

In the conventional system, when a bus having a complicated protocol is adopted as a secondary bus,
Since it is necessary to provide a control line synchronization circuit corresponding to the type of clock of the device connected to the next bus, the scale of the synchronization circuit of the bus bridge becomes large, and one signal line is not provided for each device. In this case, the number of interface signals of the bus bridge also increases. Further, when a bus having a protocol for switching addresses and data at a predetermined timing using the same signal line is adopted as a secondary bus, the address / data lines are also output in synchronization with the clock of each device. Therefore, the bus bridge must have all signals of the bus as interface signals for the number of clock frequencies.

An object of the present invention is to provide a device which operates at different frequencies without increasing the number of synchronization circuits and interface signals on the bus bridge side even if a bus having a complicated protocol is selected as a secondary bus. An object of the present invention is to enable connection, reduce logical scale and power consumption, and improve transfer efficiency.

[0008]

According to the present invention, in order to solve the above-mentioned object, the operation of the secondary bus is determined from the operation clocks of several types of devices connected to the secondary bus by a clock selection signal from a bus bridge. A clock selection unit for selecting a clock is provided, and a function of transmitting a signal synchronized with the clock output from the clock selection unit from the bus bridge is provided. Also, in a secondary bus corresponding to a plurality of masters, a bus arbiter for selecting a clock of the secondary bus at the same time as arbitration of a transfer request is provided to enable connection of a target device to the secondary bus without using a synchronization circuit. . Here, as a master device other than the bus bridge, both a master device having no unique operation clock and a master device having a unique operation clock are supported. By eliminating the need for a synchronization circuit of the target device, a reduction in logic scale and an improvement in transfer efficiency are realized.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIG. In FIG. 1, reference numeral 110 denotes a primary bus 101.
The address decoder 112 decodes the address input from the address decoder 112, the clock selector 112 selects the clock A115 and the clock B116, and 113 denotes the address decoder 1.
A clock selection signal 117 indicating an operation clock of the target device specified as the transfer destination in 10 is a synchronization circuit clock selected by the clock selector 112. In the first embodiment, a bus control system is shown in which two or more target devices operating with clocks having different frequencies are connected to the same bus and realized without providing a synchronization circuit inside the target device.

Although two clocks are input to the bus bridge 106 from the clock supply unit 107 as in the conventional example of FIG. 2, in this embodiment, a clock selector is used instead of the operation clock of the secondary bus 102. The synchronization circuit clock 117 selected in 112 is used. In addition, only one operation clock of each device is input to the target device connected to the secondary bus 102, and the synchronization circuit is omitted. The secondary bus 102 does not have a prescribed operation clock. When the data transfer destination is the target device A 108, the clock A 115
When the transfer destination is the target device B109, a signal synchronized with the clock B116 is sent to the bus bridge 1 respectively.
The output of 06 enables data transfer on the secondary bus 102 without the synchronization circuit of the target device.

The bus bridge 106 needs to dynamically change a clock for synchronizing a signal output on the secondary bus 102 with each generated transfer, so that an address input from the primary bus 101 is used as an address decoder. By decoding the data at 110 and specifying the transfer destination target, and sending the result to the clock selector 112, the clock to which the signal is to be synchronized is selected.

The flow of data transfer from the processor 103 on the primary bus 101 to the target device A 108 on the secondary bus 102 will be described with reference to FIG. The transfer request generated by the processor 103 is issued on the primary bus 101 by specifying the transfer destination to the target device A108. The bus bridge 106 that has received the transfer decodes the address of the received transfer, and processes the target device A 108 and the target device B 109 on the secondary bus.
Is determined. As a result of the judgment,
The transfer from the processor 103 is the target device A1
When the transfer is determined to be the transfer to the clock selector 08, the determination result is sent to the clock selector 112 in order to synchronize the signal output from the bus bridge 106 with the clock A115.
13 is output. The clock selector 112 selects the clock A 115 as the synchronization circuit clock 117 according to the value of the clock selection signal 113. The clock selection signal 113 is kept at a constant value until the transfer on the secondary bus 102 is completed. In the bus bridge 106, the determination result of the address decoder 110 is transmitted to the clock selector 1.
12 to transmit the transfer to the secondary bus 102 and the signal input from the primary bus 101 to the synchronization circuit 1
Synchronize at 11. According to the above flow, a signal synchronized with the clock A is output to the secondary bus 102, and the target device A 108 specified as the transfer destination receives the transfer. The same transfer procedure is performed when the transfer destination is the target device B109.

The relationship between the clock switching timing in the clock selector 112 and the synchronization of the signal input from the primary bus 101 will be described with reference to FIGS. FIG. 3 shows the primary bus 101 of the bus bridge 106.
FIG. 4 is a block diagram showing the periphery of a synchronization circuit 111 for synchronizing a signal input from the synchronizer, and FIG. 4 is a timing chart thereof. In FIG. 3, reference numeral 301 denotes a flip-flop that operates at the rising edge of the clock X114;
Reference numeral 3 denotes a flip-flop that operates at the rising edge of the clock A115, 304 denotes a signal 1 (X) input from the primary bus 101 to the bus bridge 106 synchronized with the clock X114, and 305 denotes a signal output from the flip-flop 301. 2 (X) and 306 are flip-flops 3
02 output from the flip-flop 303 to the signal 3 (A) and 307 output from the flip-flop 303 to the secondary bus 102.
(A). In FIG. 4, X1 to X9 indicate the time of the clock X114, and A1 to A6 indicate the time of the clock A115. Here, clock X114, clock A11
5. It is assumed that the clock B116 has different frequencies and phases.

In the time chart of FIG. 4, the signal 2 (X) 305 changed at X4 is taken into the flip-flop 302 at the rising edge of the clock A115 of A3. In A3, since the occurrence time of the state change of the signal 2 (X) 305 and the rising edge occurrence time of the clock A115 are extremely close to each other, the flip-flop 302 cannot take in the state change of the signal 2 (X) 305 well and output. The signal 3 (A) 306 obtained is in an indeterminate state (meta-stable state) at A4. To eliminate this metastable state, a time interval of one clock is set, and signal 3
(A) 306 is input to the flip-flop 304 of the other stage at the rising edge of the clock A115 of A5, and a signal 4 (A) 307 synchronized with the clock A116 is generated.

In the first embodiment, the bus bridge 106
The clock used in the synchronization circuit 111 is a synchronization circuit clock 117 that has selected the clock A115 and the clock B116. This synchronization circuit clock 117
Is the timing of the state change of the clock selection signal 113 obtained as a result of decoding the address synchronized with the clock X114.
Since the clock 114, the clock A115, and the clock B115 have different frequencies and phases, the time between the rising edges of the synchronization circuit clock 117 before and after the switching timing is not guaranteed.

If the address is the same as the signal 1 (X) 304,
If it is input to the bus bridge at the timing of 3,
The state change of the clock selection signal 113 generated through the address decoder 110 is later than that of the signal 1 (X) 304. Assuming that synchronization is started with respect to the signal 1 (X) 304, the value of the flip-flop 302 is changed at X 3 where the rising edge of the synchronization circuit clock 117 selected by the clock selection signal 113 occurs. It is taken in. Here, assuming that the output signal of the flip-flop 302 is in a metastable state, if the metastable state is not escaped during Tck during the time until A3 which is the next rising edge of the synchronization circuit clock 117, In step 303, the metastable state cannot be removed. As described above, before and after the switching timing of the synchronization circuit clock 117, the time between the rising edges of the clock is not guaranteed, so that Tck becomes very short, and the flip-flop 302
May not be able to escape the metastable state.

Therefore, in order to perform normal synchronization, it is necessary to input a signal to be synchronized to the synchronization circuit at a timing later than the clock selection signal 113. In the examples of FIGS. 3 and 4, the input signal 1 (X) 113 is input to the flip-flop 301 operated by the clock X114, and the state change is delayed by one clock before being input to the synchronization circuit 111.

In the conventional method without selecting a clock to be input to the synchronization circuit 111, the flip-flop 30
Since 1 is not required, it becomes large considering the latency of the bus bridge 106 alone. However, in the whole system, the clock X114 is the clock A115 and the clock B
Since the operating frequency is considered to be higher than 116,
Target device A108 or target device B1
09 is eliminated by eliminating the synchronization circuit of the flip-flop 3 operating with the clock X114.
01 is sufficiently longer than the transit time of 01, and it can be said that the effect of adopting this method is not affected.

Next, the bus bridge 10 is connected to the secondary bus 102.
Second Embodiment A case where a master device other than the sixth device is connected will be described with reference to FIG. Second Embodiment 10 in Second Embodiment
The master device newly connected to 2 operates on a single clock and is assumed to be a device capable of dynamic clock change. An example of such a device is a DMA controller that issues a transfer request by setting a register. In FIG. 5, reference numeral 501 denotes a master device that issues a transfer request connected to the secondary bus 102, 502 denotes a bus arbiter that arbitrates a plurality of bus users, and 503 denotes a bus bridge transfer request output from the bus bridge 106 to the bus arbiter 502. , 504 are bus bridge transfer permission signals output from the bus arbiter 502 to the bus bridge 106, 505 is a master transfer request output from the master device 501 to the bus arbiter 502, and 506 is a master transfer permission output from the bus arbiter 502 to the master device 501. A signal 507 is a clock selection signal. Here, it is assumed that the clock selection signal is output to the bus arbiter 502 at the same time as the transfer request signals 503 and 504 are output.

Although a bus to which a plurality of masters can be connected needs a mechanism for arbitrating a bus user, in the second embodiment, the bus arbiter 502 outputs not only a bus user but also a clock selection signal. . In FIG. 5, the secondary bus 1
The bus bridge 106 and the master device 501, which are two devices that issue a transfer request connected to the device 02, output a clock selection signal to the bus arbiter 502, which specifies not only the transfer request but also a clock to be operated. .

The bus arbiter 502 selects a device that can start a transfer on the secondary bus 102, transmits transfer permission signals 504 and 506 to the device, and simultaneously outputs a clock selection signal issued by the selected device. The clock is output to the clock selector 112, and a clock having a frequency required by the device having the bus right is selected. In the bus arbiter 502, the clock is also switched at the timing of switching the right to use the bus. Therefore, before and after the switching, it is necessary to prevent the occurrence of bus collision and metastable using some method. Therefore, in the second embodiment, a method of introducing a mechanism for operating the clock switching timing by the bus arbiter 502 and a method of operating the clock by the bus bridge 106 are adopted.

First, a method of operating clock switching timing in the bus arbiter 502 will be described with reference to a detailed diagram of the bus arbiter 502 in FIG. 6 and a bus arbitration timing chart in FIG. 6, reference numeral 601 denotes a bus bridge clock selection signal output by the bus bridge 106 to select the synchronization circuit clock 117, and 602 denotes a master device output by the master device 501 to select the synchronization circuit clock 117. A clock selection signal 603 is a clock selection signal selector for selecting a clock selection signal of a device to which the bus right has been given, and 604 is a bus arbiter for transmitting a bus bridge transfer request 503 which is a signal output in synchronization with the clock X114 of the primary bus 101. 5
The clock 117 for the synchronization circuit, which is the operation clock 02
605, a post-synchronization bus bridge transfer request synchronized by the synchronization circuit 604, 606 receives the post-synchronization bus bridge transfer request 605 and the master transfer request 505, and determines any priority. A priority determining unit 607 determines which device is given a bus right by a method, 607 is a bus bridge selection signal which is a result determined by the priority determining unit 606, and 608 is a secondary bus 10
A control signal 609; a bus idle detector 609 for detecting that the secondary bus 102 is not in use by using the control signal 606; a bus right switching timing signal 610 resulting from the bus idle detector 607; The signal 607 is fetched when the bus right switching timing signal 610 is asserted, 611 is a flip-flop for generating a bus bridge transfer permission signal, 612 is an inverter, 613 is a signal inverted by the inverter 612, 614
Is a synchronization circuit for synchronizing the master transfer permission signal 506 at the clock frequency required by the master device 501. In FIG. 7, A1 to A5 are clocks A11
Time B5, B1 to B6 are the time of clock B116, 7
Reference numeral 01 denotes an internal signal of the synchronization circuit 610 shown in FIG. 6, which is an output signal of a first-stage flip-flop of two-stage flip-flops prepared for synchronization.

A procedure in which bus arbitration is performed by the bus arbiter 502 will be described. The transfer request signal 503 from the bus bridge 106 is synchronized with the synchronization circuit clock 117 in the synchronization circuit 604, and the 117 master device 501 already synchronized with the synchronization circuit clock is used.
The transfer request signal 505 from
6 is input. The priority determination unit 606 determines which transfer request has a higher priority by using an arbitrary priority determination algorithm, and outputs a bus bridge selection signal 607 that is asserted when the bus bridge 106 is selected.

At the same time, the bus idle detector 607
The control signal 608 of the secondary bus 102 is observed, and the secondary bus 1
02 is being used, and if not, the bus right switching timing signal 610 is asserted. The bus bridge selection signal 607 is captured by the flip-flop 611 at the rising edge of the clock when the bus right switching timing signal 610 is asserted, and the bus bridge transfer permission signal 504 is generated. Master transfer permission signal 506 is the inverse of bus bridge transfer permission signal 504.

As a premise of the second embodiment, it is assumed that the master device 501 is a device that generates a transfer request by setting a register. Such a device issues a transfer request after it is normally ready to transfer data. Therefore, when the master device 501 receives the transfer permission signal 506 for the transfer request, the master device 501 performs the next synchronization without passing through the synchronization circuit. The bus output operation can be started at the rising edge of the circuit clock 117. Therefore, the bus arbiter 502 must output the master transfer permission signal 506 to the master device 501 having no synchronization circuit in synchronization with the clock requested by the master device 501. On the other hand, the bus bridge 106
03 is issued to acquire the bus right, and the signal is output to the secondary bus 102 through the synchronization circuit 111. Therefore, the bus bridge transfer permission signal 504 does not need to be synchronized with the clock. When the bus bridge transfer permission signal 504 is synchronized, the synchronization is doubled. Therefore, as shown in FIG. 6, the bus bridge transfer permission signal 504 uses the output of the flip-flop 611 as it is, and the master transfer permission signal 506 inverts the output of the flip-flop 611 by the inverter 612.
12 is synchronized with the synchronization circuit clock 117 after the clock is switched by the synchronization circuit 614 and is output, thereby avoiding duplication of synchronization.

Details of the timing when the bus right is switched from the bus bridge 106 to the master device 501 are shown in the timing chart of FIG. At A1, the master device 501 issues the transfer request 503 while the bus bridge 106 is transferring data on the secondary bus 102 in synchronization with the clock A115. Here, it is assumed that the master device 501 has requested transfer to the target device B109 and wishes to operate at the clock B116.
The transfer of the bus bridge 106 ends at A1, and the bus bridge 106 lowers the transfer request 503 at the rise of the clock A115 of A2. At the same time, since the secondary bus 102 is in an unused state, the bus right switching timing signal 610
Is asserted. At the rising edge of the clock A115 of A3, the bus bridge transfer permission signal 504 is negated, and the clock selection signal 507 is set as the master device 5
01 master device clock selection signal 6
02 is selected. After the switching of the clock selection signal 507, the clock 117 for the synchronization circuit becomes the clock A115.
To B116. Since the bus bridge transfer permission signal 504 is negated at the rising edge of the clock A115 of A3, which is the clock switching timing, the inverted signal is used as it is as the transfer permission signal 506 to the master device 501, and the master device 501 Becomes an asynchronous signal with the clock B116 which is the operation clock required by. Therefore,
At the rising edge of the clock B116 of B4, the value of the inverted signal 613 of the bus bridge transfer permission signal 504 becomes synchronized 1
The clock B of B5 is taken into the flip-flop
At the rise of 116, the value of the output signal 701 from the first-stage synchronization flip-flop is taken into the second-stage synchronization flip-flop, whereby the master transfer permission signal 506 synchronized with the clock B116 is generated.

Next, a method of operating the clock by the bus bridge 106 will be described. The master device 501 used in the second embodiment issues a transfer request 505 by setting a register by the processor 103.
Issues the transfer request 505, the processor 103 must know before issuing the transfer request. Therefore, in the present system, a mechanism that can be set inside the bus bridge 106 so that a transfer is performed by selecting a clock scheduled to be selected at the time of issuing the transfer request 505 as a clock when accessing the register to the master device 501 is performed. Provide.
Several methods are conceivable as examples of such a mechanism. One is to provide a dedicated register for setting the operation clock of the transfer to be issued inside the bus bridge 106, to set it before issuing the transfer for setting the register of the master device 501, and to set the value of the dedicated register to the clock selection signal. Is output as The other is that, when an address at the time of issuing the transfer request 503 of the master device 501 is set in a register inside the master device 501, a mechanism for decoding the set value of the address is provided inside the bus bridge 106, and the clock selection signal is output. How to decide. If the clock is selected when the master device 501 accesses the register in this way, no clock switching occurs when the master device 501 issues the transfer request 505, so that when the bus arbiter 502 outputs the master transfer permission signal 506, There is no need to provide a synchronization circuit, and the time required for bus arbitration can be reduced.

Further, as a third embodiment, the secondary bus 102
FIG. 8 illustrates a case where the device connected to the device has its own operation clock because it is connected to an external I / O or another bus. 8, reference numeral 801 denotes a master device having an external interface in addition to the interface with the secondary bus 102; 802, an external I / O connected to the master device 801; 803, an address decoder from the external I / O 802; , 804 are input signals from the external I / O 802 to the clock 1 for the synchronization circuit.
17, the input signal from the secondary bus 102 is transferred to the external I / O 8
A synchronization circuit for synchronizing with the operation clock of No. 02,
Reference numeral 805 denotes a clock C for operating the master device 801 and the external I / O 802. Reference numeral 806 denotes a bus arbiter that receives a transfer request from the bus bridge 106 and the master device 801 and arbitrates the bus.

In the third embodiment, since the master device 801 has the clock C805 which is an original operation clock, it is necessary to provide the same function as the bus bridge 106 in the first embodiment. That is, the address input from the external I / O 802 is decoded by the address decoder 803 and the master transfer request 50 is sent to the bus arbiter 806.
5 at the same time as receiving the master transfer permission signal 506, the synchronization circuit 804 outputs the clock C805.
Is synchronized with the synchronization circuit clock 117.

FIG. 9 shows the internal configuration of the bus arbiter 806 of the third embodiment. 9, reference numeral 901 denotes synchronization for synchronizing a master transfer request 505 which is a signal output in synchronization with a clock C 805 which is an operation clock of the master device 801, to a synchronization circuit clock 117 which is an operation clock of the bus arbiter 502. The circuit 902 is a post-synchronization master transfer request synchronized by the synchronization circuit 901.
Since the synchronization circuit 804 exists in the master device 801, the master transfer permission signal 506
It is output only by inverting the bus bridge transfer permission signal 504 generated in step S11. Even if the master device 801 operates with its own clock, no synchronization circuit is required for the two types of target devices.

[0031]

According to the present invention, in a system having a hierarchical bus structure, a bus bridge connecting a primary bus (high-speed processor bus) and a secondary bus (a relatively low-speed bus connecting peripheral devices and the like) is provided. By providing a mechanism for selecting a clock for synchronizing an output signal depending on a transfer destination on the secondary bus of data, a synchronization circuit of a target device serving as a transfer destination is eliminated, and a logical scale and power consumption are reduced. Can be reduced, and the transfer efficiency can be improved. Further, by providing a bus arbiter for selecting a clock for synchronizing data output from each master in addition to bus arbitration on the secondary bus, the target device does not need to have a synchronization circuit, and thus has a second arbiter.
Enables multiple master connections to the next bus. Further, when a master device other than the bus bridge connected to the secondary bus does not have its own operation clock, the synchronization circuit inside the master device can be deleted.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional example.

FIG. 3 is a configuration diagram of a synchronization circuit inside a bus bridge.

FIG. 4 is a timing chart showing timings of signal lines in FIG. 3;

FIG. 5 is a configuration diagram of a second embodiment of the present invention.

FIG. 6 is a configuration diagram of a bus arbiter in a second embodiment.

FIG. 7 is a timing chart of bus arbitration in the bus arbiter of FIG. 6;

FIG. 8 is a configuration diagram of a third embodiment of the present invention.

FIG. 9 is a configuration diagram of a bus arbiter in a third embodiment.

[Explanation of symbols]

101: a synchronous primary bus, 102: a synchronous secondary bus operating at a frequency different from the primary bus, 103: a processor connected to the primary bus, 104 ... a transfer request connected to the primary bus , A master device that outputs
A target device for receiving a transfer request connected to the primary bus, 106...
A bus bridge for communicating to the device of the next bus 102, 107
... Clock supply unit that supplies a clock to each device
08 ... Target device A connected to the secondary bus and operating at clock A, 109 ... Target device B connected to the secondary bus and operating at clock B, 110 ... Address for decoding the address input from the primary bus Decoder, 112 ... Clock selector for selecting clock A and clock B, 113 ... Clock selection signal indicating which of clock A and clock B is selected, 117 ... Clock for synchronization circuit selected by clock selector, 1
14: Clock X for operating the primary bus, 115: Clock A for operating the target device A, 116: Clock B, for operating the target device B, 111: Synchronizing circuit inside the bus bridge, 201: Secondary bus operating Clock Y, 202 ... synchronization circuit inside target A,
Reference numeral 203: a synchronization circuit inside the target B; 301, a flip-flop that operates at the rising edge of the clock X; 302, 303, a flip-flop that operates at the rising edge of the clock A; 304, which is synchronized with the clock X input to the bus bridge Signal 1 (X), 30
5: signal 2 output from flip-flop 301
(X), 306... The signal 3 (A) output from the flip-flop 302, 307... The signal 4 (A) output from the flip-flop 303 to the secondary bus, 501... Master device to issue, 50
2. Bus arbiter for mediating a plurality of bus users, 50
3: Bus bridge transfer request output from bus bridge to bus arbiter 502; 504: Bus bridge transfer enable signal output from bus arbiter 502 to bus bridge; 505: Bus arbiter 5 from master device 501
02, a master transfer request output from the bus arbiter 502 to the master device 501, 507 a clock selection signal output from the bus arbiter 502, 507 a bus output from the bus bridge for selecting a clock for the synchronization circuit A bridge clock selection signal, 602... A master device clock selection signal output by the master device 501 to select a synchronization circuit clock, 603.
A clock selection signal selector 604 for selecting a clock selection signal of a device to which a bus right has been given; a synchronization circuit 604 for synchronizing a bus bridge transfer request, which is a signal output in synchronization with the clock X, with a synchronization circuit clock; 605... Receives a bus bridge transfer request after synchronization synchronized by the synchronization circuit 604, 606... Receives a bus bridge transfer request after synchronization and a master transfer request, and gives a bus right to which device by an arbitrary priority determination method. A priority determining unit for determining whether or not the secondary bus is not in use by using a bus bridge selection signal, a result of the determination by the priority determining unit, a control signal for a secondary bus, and a control signal A bus idle detecting section for detecting that the bus is idle, 610... A bus right switching timing signal as a result of the bus idle detecting section, 611. Flip-flop for generating a ridge transfer permission signal; 612, an inverter; 613, a signal inverted by the inverter; 614, a synchronization circuit for synchronizing the master transfer permission signal with a clock frequency required by the master device 501; The internal signal of the conversion circuit 614, the output signal of the flip-flop of the first stage among the flip-flops prepared for two stages for synchronization, 801 ...
A master device having an interface with the outside in addition to the interface with the secondary bus, 802... External I / O connected to the master device 801, 803.
Address decoder from O, 804... Master device 8
01 internal synchronization circuit, 805 ... master device 801
, A bus arbiter that receives a transfer request from the bus bridge and the master device 801 and arbitrates the bus, and 901... A master transfer request 505 that is a signal output in synchronization with the clock C for a synchronization circuit. A synchronization circuit that synchronizes with the clock 117; 902 a master transfer request after synchronization synchronized by the synchronization circuit 901;
X1 to X9 ... time of clock X114, A1 to A6 ... time of clock A115, B1 to B6 ... clock B116
time of.

Claims (6)

[Claims] 1. A primary bus and a secondary bus which are at least two types of clock synchronous buses, a bus bridge connecting the two types of buses, and at least one bus for outputting a transfer request connected to the primary bus. Types of clock synchronous master devices 1 and at least two types of clock synchronous target devices that operate on clocks connected to the secondary bus and that have different frequencies or periods and receive transfer requests; In a system including a target device and a clock supply unit that supplies a clock to the bus bridge, an address decoder for detecting a transfer destination of a transfer request from the master device, and a transfer detected by the address decoder are provided inside the bus bridge. Means for outputting a target device selection signal indicating the target device, and the primary bus. A synchronizing circuit for synchronizing a signal operating with the clock of the secondary bus with the clock of the secondary bus and a signal operating with the clock of the secondary bus with the clock of the primary bus. A bus control system comprising: a clock selection unit that selects clocks of the two types of target devices and inputs the clocks to the synchronization circuit as a clock of the secondary bus. 2. The bus control system according to claim 1, wherein
A bus control system, wherein a signal output to the secondary bus is synchronized with a different clock depending on a data transfer destination. 3. At least one type of bus, at least two types of clock synchronous master devices connected to the bus, and operating at clocks connected to the bus and having different frequencies or periods to receive a transfer request. At least two types of clock synchronous target devices, a clock supply unit that supplies clocks to the master device and the target device, and one of operation clocks of the two types of target devices is selected as an operation clock of the bus. In a system including a clock selection unit, arbitrating transfer requests output by the two types of master devices,
A bus use permission is alternately given to the two types of master devices, and a function of selecting a desired operation clock of the master device given the bus use permission as an operation clock of the bus is provided. A bus arbiter for arbitrating transfer requests so that signals do not collide on a secondary bus. 4. The bus control system according to claim 1, wherein
A bus control system comprising: at least one type of master device connected to the secondary bus; and a bus arbiter for arbitrating a transfer request from the bus bridge and the master device. 5. The bus control system according to claim 1, further comprising at least one type of master device connected to said secondary bus and operating only with an operation clock of said secondary bus. 4. A bus control system comprising a bus arbiter according to claim 3, wherein a transfer permission signal to said master device 2 is output in synchronization with an operation clock of said secondary bus desired by said master device 2. 6. The bus arbiter according to claim 3, and at least one type of master device connected to said secondary bus and operated only by an operation clock of said secondary bus which outputs a transfer request by setting an internal register. 2. The bus control system according to claim 1, further comprising: operating the secondary bus at the same clock as the operation clock request of the secondary bus scheduled to be issued by the master device, and performing the internal register setting of the master device. Bus control system characterized by: