JPH09185582A - Clock control system and its method for local bus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock control system and its method effectively controlling the transfer rate of a local bus by providing not less than one local bus, a CPU bus, the bus bridge of both and a clock generator for a CPU clock and a local bus clock so as to transfer data mutually between the buses through the bus bridge. SOLUTION: The clock of an medium rate with the frequency between the CPU clock and the local bus clock is newly provided so that when the opposite side of data transfer is the CPU bus 6, a slow clock is set to be the local bus clock and when the opposite side is the local bus 1, the clock of the medium rate is set to be the local bus clock. In addition, the speed of the clock of the medium rate is set to be the same as the maximum rate of a bus master 2. In addition the clock of the medium rate is set normally and changed to a slow clock only at the time of transferring data to the CPU bus 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for controlling a clock frequency of a local bus so as to synchronize it with a CPU bus in a computer system in which a CPU bus and a local bus are interfaced by a bus bridge logic. The present invention relates to a local bus clock control method capable of effectively managing a transfer rate.

[0002]

2. Description of the Related Art Conventionally, a CPU bus used for a central processing unit (hereinafter referred to as a CPU) for controlling the entire system, a cache memory, etc., and a local bus used for an input / output circuit and peripheral circuits subordinate thereto are provided. In a computer system, it is important that information can be transferred smoothly to and from the local bus without hindering the overall processing of the CPU bus. Various methods have been proposed.

FIG. 3 is a block diagram of a conventional example disclosed in Japanese Patent Laid-Open No. 5-2552. The conventional example shown in FIG.
The PU 110 has three types of functional blocks 130, 140, 1 via a host P / M bus (hereinafter referred to as a CPU bus).
Connect with 50 to communicate. 130 is a bus interface block (hereinafter, abbreviated as BIB),
A plurality of slots 131 connected to the micro channel 131
a and an interface with the SCSI controller 131b for the fixed disk device, and other functional blocks 1
It has a microprocessor that acts as a master in communicating with 40,150. A memory block (memory and cache controller: PIB) 140 controls access to the plurality of DRAMs 141 and the ROM 142 for the BIOS. Reference numeral 150 denotes a peripheral interface block (peripheral device and video graphic array interface), which are input / output devices 151a to 151a.
c and the peripheral devices 152a and 152b.

FIG. 4 is a block diagram specifically showing the BIB in FIG. The BIB 130 of the conventional example shown in FIG.
The CPU bus 120 is connected to an internal transaction bus 134 via a CPU bus interface HPI (host P / M bus interface) 132, and this transaction bus (hereinafter, referred to as local bus) 134.
Includes a DMA controller 135 and a synchronizer SYN 136 that mediates communication with the Micro Channel 131. 137 is a micro channel controller MC
A. In each of the other functional blocks 140 and 150 as well, as in the BIB 130, communication with the respective lower device groups is performed via the local bus.
The IB 130 will be described as a typical example.

Next, the operation of the conventional example will be described. Normally, on the local bus 134 of the BIB 130,
The timing of data transfer is based on the CPU clock, and all the operations in its function block are independently executed in one cycle of the system. In the CPU bus 120, for example, the preparation of the transfer data requested by the CPU 110 can be received by the CPU 110 in the next one cycle after the BIB 130 is completed. Basically CP
U spends only two cycles of the CPU clock for data transfer with the local bus 134, and suppresses the standby state required during that time in a short time.

On the other hand, the BIB 130 is a CPU bus 120.
Access right to the CPU 110, occupy the CPU bus for a plurality of cycles, and function as a bus master that transfers data to and from the memory block 140. At that time, the DMA controller 135 of the BIB 130 is
Local bus 1 via PI 132 and CPU bus 120
34 and the memory block 140 are directly connected, and data transfer can be continuously performed in the burst mode. Since the burst mode does not require the CPU 110 to intervene in data transfer between each other, the effective speed required for a series of data transfer is reduced as compared with the normal mode. Therefore, it is often used when exchanging image data with the fixed disk device.

The control system of data transfer by a single CPU clock has been described above. In addition to this, the CPU bus 12
0 and the local bus 134 may use different clocks. For example, for a high-speed CPU bus 120 that uses an expensive CPU element even at a high speed, a low-speed local bus 13 configured by peripheral circuit elements that are slower but cheaper than this
There is a computer system consisting of four.

In this case as well, it is necessary to transfer information in synchronization between the high-speed CPU bus 110 and the low-speed local bus 134, and one cycle of the CPU bus 110 cannot follow one cycle of the local bus 134. Even CP
The next one cycle of the U bus 110 is matched and synchronized.
At this time, since it is necessary to use the same clock generator also for simplification of the circuit, the clock of the CPU bus 110 is divided to divide the clock into half or an integer, and the local bus 1 is divided.
It may also form a clock for 34.

[0009]

However, there have been the following problems in attempting efficient data transfer using the conventional local bus clock control system. If the clock of the CPU bus is set to 50 for the high speed CPU
Low-speed C with MHz and local bus clock is inexpensive
If the maximum frequency is 33MHz according to PU, 50MH
If z is divided to 25 MHz and used as the clock of the local bus, data transfer between buses can be synchronized, but the maximum speed of 33 MHz cannot be maintained even in normal operation that is processed only by the local bus, and device performance is effective. I can't withdraw.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a clock control system and a clock control method for a local bus that can effectively manage the transfer rate of the local bus.

[0011]

In order to solve the above problems, the clock control system for a local bus of the present invention controls at least one local bus whose access right is arbitrated by an arbiter at the request of a bus master and the entire system. A CPU bus by a CPU, a bus bridge for interfacing a local bus and a CPU bus, a high-speed first frequency clock for the bus bridge and the CPU, and a low-speed first frequency divided for the bus bridge and the bus master. In a computer system, which comprises a clock generator for supplying clocks of two frequencies, respectively, and transfers data between buses via a bus bridge by the clocks of the first and second frequencies, the clocks are:
A clock of a third frequency, which is an intermediate speed between the first and second frequencies and is supplied to each device of the local bus system, is newly provided, and the bus master is in the first state in which the other party of the data transfer is the CPU bus or the local state. It is a bus that sends a frequency conversion request signal to the arbiter to notify it of a second state that requires high-speed processing. The arbiter introduces this frequency conversion request signal, and if it is in the first state, In the configuration, two frequencies are designated to the clock generator in the second state, and a third frequency is designated to the clock generator.

According to the above clock control method, normally C
When the PU is operating, a CPU clock divided by frequency is used as the local bus clock in order to reduce overhead due to synchronization. However, when the bus master requests the access right of the local bus to the arbiter for data transfer, if it knows in advance that the transfer partner is a device on the local bus, the bus master requests the access right and the local bus clock. Request the arbiter to speed up. The arbiter arbitrates the access right of the local bus, and instructs the clock generator to speed up the local bus clock when the bus master acquires the access right. When the bus master finishes the data transfer and releases the access right, the arbiter gives an instruction again to restore the local bus clock to the original frequency.

In the clock control system for the local bus according to the second aspect, the third frequency is the same as the maximum speed possessed by the bus master. According to the clock control method of the second aspect, the local bus clock becomes the same as the maximum speed at which the bus master can operate.

In the local bus clock control system according to claim 3, the arbiter normally designates the third frequency to the clock generator, and designates the second frequency only when the data is transferred to the CPU bus. is there. According to the clock control method of the third aspect, normally, the intermediate speed local bus clock is instructed to the clock generator by the arbiter, and the low speed clock is instructed only when the data is transferred to the CPU bus.

According to a fourth aspect of the present invention, there is provided a local bus clock control method, in which at least one local bus is arbitrated by an arbiter in response to a request from a bus master, a CPU bus for controlling the entire system, a local bus and a CPU bus. A high-speed first frequency clock to the bus bridge and the CPU, and a first high-speed clock to the bus bridge and the bus master.
A clock generator that supplies a low-speed second frequency clock whose frequency is divided,
In a computer system that transfers data between buses via a bus bridge with a frequency clock,
The bus master determines whether or not the data is transferred to and from the CPU bus, and notifies the arbiter, and only when the data is transferred to other than the CPU bus, the arbiter designates the clock generator to determine the first and second frequencies. The third frequency, which is the intermediate speed of and is supplied to each device of the local bus system, is supplied to the bus bridge, the bus master, and the like.

According to the clock control method of the fourth aspect, whether or not the data transfer with the CPU bus is judged by the bus master and notified to the arbiter, and the CP is transmitted.
The arbiter specifies the clock generator only when the data is transferred to a device other than the U bus.
The third frequency, which is an intermediate speed of the frequency and is supplied to each device of the local bus system, is supplied to the bus bridge, the bus master, and the like.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram illustrating a configuration of an embodiment according to the present invention. The main part of this embodiment is a known bus master (PCI master) 2 for instructing data transfer in the local bus 1, an arbiter 3 for instructing high-speed data transfer by this instruction, and changing the clock frequency by this instruction. The clock generator 4 is a clock generator 4 that performs data transfer between the CPU buses 6 via the well-known host bridge 5.

The local bus 1 employs, for example, a PCI bus, one or more of which is provided, operates according to the local bus clock S1, and is connected to a PCI slave 7 such as an input / output device or a peripheral device. Further, the CPU bus 6 is operated by the CPU clock S2 and is also connected to the CPU 8 and the main memory 9 which control the entire system.

Generally, the CPU clock S2 has a high speed first frequency (for example, 50 MHz) and is supplied to the CPU and the bus bridge, and also the local bus clock S1.
Is a low-speed second frequency obtained by dividing the first frequency (for example, 2
5 MHz) and supplies to the bus master and the bus bridge. Both clocks are generated from a single clock generator 4, and the local bus clock S1
Has a very small skew difference from the edge of the source CPU clock. Therefore, the overhead in the host bridge 5 due to the synchronization is sufficiently suppressed.
In addition to this, the clock generator 4 of the present invention has a first
And a clock of a third frequency (for example, 33 MHz) that is an intermediate speed of the second frequency and is supplied to the bus master 2.

The bus master 2 is a CP for data transfer.
A frequency change request signal S3 is sent to the arbiter for notifying the first state, which is the U bus, or the second state, which is the local bus and requires high-speed processing. At the same time, a publicly known bus request signal (BRE) for requesting an access right of the local bus.
Q) S4 is sent to the arbiter 3, and a well-known bus permission signal (BGNT) S5 indicating permission of this access is sent to the arbiter 3.
Introduce from.

The second state may be data transfer independent of the CPU bus, which is known to be completed by only the local bus. Not only the data transfer with the PCI slave 7 but also, for example, not shown. It may be to another PCI slave, an input / output device, a peripheral device, etc., or to a different local bus via another bus bridge.

The arbiter 3 confirms the acquisition of the access right by the bus master 2 by introducing the frequency change request signal S3, forms the frequency change designation signal S6 and sends it to the clock generator 4. This frequency change designation signal S6 is
It is a signal that specifies the second frequency when the frequency change request signal S3 is in the first state and a new third frequency when it is in the second state. Further, the bus request signal S4 from the bus master 2 and the bus request signal S7 from the host bridge 5 are accepted,
A point for arbitrating access rights to the local bus 1 by both parties, and a bus permission signal S to the bus master 2 depending on the result of the arbitration.
It is known to send back 5 or send the bus grant signal S8 to the host bridge 5.

The new third frequency is an intermediate speed between the first and second frequencies and is used as a clock to be supplied to each device of the local bus system such as the bus master 2, the host bridge 5 and the PCI slave 7. . For example, if the maximum speed of each device such as the bus master 2 is provided, the processing completed in the local bus system can be most efficiently performed. The host bridge 5 includes the local bus 1 and C
It is an interface of the PU bus 6, and the CPU clock is used as a basic operation clock, and the local bus clock is referred to when data is transferred to and from the local bus. Also,
The main memory control signal S8 is sent to the main memory 9 and used for DMA control and the like in the burst mode.

Next, the operation of this embodiment will be described. FIG. 2 is a flowchart illustrating the operation of the embodiment according to FIG. In FIG. 2, in this operation, the processing cycle activated by the CPU 8 at 50 MHz is an access to the PCI slave 7, and
The case where it spreads on the local bus of 5 MHz will be described as an example.

First, the bus master 2 sends a bus request signal S4 to the arbiter 3 or the like to request the access right of the local bus 1 in order to transfer data on the local bus 1 (step 21). In this case, it is judged in advance whether the access destination of the bus master 2 is the PCI slave 7 (step 22), and if it is known (Yes)
s) can send the frequency change request signal S3 to the arbiter 3 at the same time as asserting the bus request signal to request the local bus clock S1 to be speeded up from 25 MHz to 33 MHz (step 23). Note that step 20
Is the last processing cycle on the local bus.

Subsequently, the arbiter 3 arbitrates the access right of the local bus 1 between the bus master 2 and the host bridge 5 (step 24). At this time, if a request to speed up the clock is issued, it is confirmed that the bus master 2 has acquired the access right, and the clock change designation signal S6 is sent to the clock generator 4 to instruct the clock frequency change. In response to this instruction, the clock generator 4 immediately changes the local bus clock to 33 MHz, and the bus master 2 starts accessing the PCI slave 7 (step 25). When this access is completed, the bus master 2 notifies the arbiter 3 that the local bus is released (step 26), and the arbiter 3 uses the local bus clock 33M.
Clock generator 4 returns from Hz to 25 MHz
To be specified.

Next, when it is unknown whether the access destination of the bus master 2 is each device on the local bus 1 or the main memory 9 on the CPU bus 6 (N in step 22).
o) will be described. In this case, the bus master 2 does not send the clock change request signal S3 when requesting the access right of the local bus 1. Therefore, the arbiter 3
This access right is arbitrated, but the frequency change designation signal S6 is not sent to the clock generator 4 (step 2).
7). That is, the bus master 2 executes this processing cycle for 2
It is performed at 5 MHz, and even if this is an access to the main memory 9 on the CPU bus 6, it can be completed in correct synchronization (steps 28 and 29). In addition,
Step 30 is the next processing cycle on the local bus.

The case where the third frequency is provided has been described above. However, even if the third frequency is plural and the fourth frequency is used for another second bus master or the like, the second CPU in the multiprocessor system is used. It is also possible to use a configuration to maintain the maximum allowable processing speed between multiple types of local bus access. It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention.

[0029]

As described above, the local bus clock control system and clock control method of the present invention have the following effects. First, when the CPU bus operates at a high-speed CPU clock according to a high-speed CPU and the local bus operates at an intermediate-speed local bus clock according to an inexpensive low-speed CPU, the CPU clock is divided to a low speed. Even if the data transfer is synchronized between the buses as the local bus clock of the device, the operation at the intermediate speed can be maintained during normal operation that is processed only by the local bus, so the device performance on the local bus can be efficiently extracted. You can Secondly, as a result, it becomes possible to provide a clock control system and a clock control method for the local bus that effectively manages the transfer rate on the local bus.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a configuration of an embodiment according to the present invention.

FIG. 2 is a flowchart illustrating the operation of the embodiment according to FIG.

FIG. 3 is a configuration diagram showing a configuration of a conventional example disclosed in Japanese Patent Laid-Open No. 5-2552.

FIG. 4 is a configuration diagram specifically showing a BIB in FIG.

[Explanation of symbols]

 1 ... Local bus 2 ... Bus master 3 ... Arbiter 4 ... Clock generator 5 ... Host bridge 6 ... CPU bus 7 ... PCI slave 8 ... CPU 9 ... Main memory

Claims (4)

[Claims] 1. An at least one local bus in which an arbiter arbitrates an access right in response to a request from a bus master, a CPU bus for controlling a system as a whole, a bus bridge for interfacing the local bus and the CPU bus, a bus bridge, and A clock generator for supplying a high-speed first frequency clock to the CPU and the like, and a clock generator for supplying a low-speed second frequency clock obtained by dividing the first frequency to the bus bridge and the bus master, respectively. In a computer system that transfers data between buses via a bus bridge, the clock is a medium frequency intermediate clock between the first and second frequencies, and a third frequency clock supplied to each device of the local bus system is newly added. The data transfer partner of the bus master is the CPU bus. Is transmitted to the arbiter, and the arbiter introduces the frequency conversion request signal. In the first state, the second frequency is designated to the clock generator, and in the second state, the third frequency is designated to the clock generator. 2. The local bus clock control system according to claim 1, wherein the third frequency is the same as the maximum speed of the bus master. 3. The arbiter according to claim 1 is usually a third arbiter.
A local bus clock control method in which a frequency is specified to a clock generator and a second frequency is specified only when data is transferred to a CPU bus. 4. An at least one local bus in which an arbiter arbitrates access rights at the request of a bus master, a CPU bus for controlling the entire system, a bus bridge for interfacing the local bus and the CPU bus, a bus bridge, and A clock generator for supplying a high-speed first frequency clock to the CPU and the like, and a clock generator for supplying a low-speed second frequency clock obtained by dividing the first frequency to the bus bridge and the bus master, respectively. In a computer system that transfers data between buses via a bus bridge, the bus master determines whether or not the data is transferred to the CPU bus, notifies the arbiter, and transfers the data to other than the CPU bus. Clock generator by arbiter only if Specified otherwise, the clock control method of the local bus, characterized in that an intermediate speed of the first and second frequencies to provide a third frequency supplied to each device of the local bus system to bus bridge and a bus master or the like.