JPS6476260A - Memory access system - Google Patents

Memory access system

Info

Publication number
JPS6476260A
JPS6476260A JP23259087A JP23259087A JPS6476260A JP S6476260 A JPS6476260 A JP S6476260A JP 23259087 A JP23259087 A JP 23259087A JP 23259087 A JP23259087 A JP 23259087A JP S6476260 A JPS6476260 A JP S6476260A
Authority
JP
Japan
Prior art keywords
memory access
memory
master
basic clock
access request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23259087A
Other languages
Japanese (ja)
Inventor
Masato Shirato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23259087A priority Critical patent/JPS6476260A/en
Publication of JPS6476260A publication Critical patent/JPS6476260A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Abstract

PURPOSE:To rapidly process an access request from all masters by executing a processing by a memory control circuit according to the basic clock of the master requesting the memory access. CONSTITUTION:In a memory access system for making an access to a common memory 4 by the plural masters 1, 2 different in the frequency of the basic clock, the memory control circuit 3 for operating by the basic clock Cm of the main master to the memory access request from the main master 1 and operating by the basic clock Cs of the sub-master to the memory access request from the sub-master 2 is provided. Thereby, it is not required to synchronize the memory access request but the access requests from all the masters can be rapidly processed.
JP23259087A 1987-09-18 1987-09-18 Memory access system Pending JPS6476260A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23259087A JPS6476260A (en) 1987-09-18 1987-09-18 Memory access system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23259087A JPS6476260A (en) 1987-09-18 1987-09-18 Memory access system

Publications (1)

Publication Number Publication Date
JPS6476260A true JPS6476260A (en) 1989-03-22

Family

ID=16941744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23259087A Pending JPS6476260A (en) 1987-09-18 1987-09-18 Memory access system

Country Status (1)

Country Link
JP (1) JPS6476260A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09185582A (en) * 1995-12-29 1997-07-15 Nec Corp Clock control system and its method for local bus
US8747724B2 (en) 2009-07-03 2014-06-10 Krones Ag Blow molding machine and method for producing hollow bodies

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09185582A (en) * 1995-12-29 1997-07-15 Nec Corp Clock control system and its method for local bus
US8747724B2 (en) 2009-07-03 2014-06-10 Krones Ag Blow molding machine and method for producing hollow bodies

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