JPS5532117A - Bus controlling device - Google Patents

Bus controlling device

Info

Publication number
JPS5532117A
JPS5532117A JP10460178A JP10460178A JPS5532117A JP S5532117 A JPS5532117 A JP S5532117A JP 10460178 A JP10460178 A JP 10460178A JP 10460178 A JP10460178 A JP 10460178A JP S5532117 A JPS5532117 A JP S5532117A
Authority
JP
Japan
Prior art keywords
bus
control circuit
master request
bus master
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10460178A
Other languages
Japanese (ja)
Inventor
Masahiro Hata
Shuji Yoshida
Kenji Morosawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10460178A priority Critical patent/JPS5532117A/en
Publication of JPS5532117A publication Critical patent/JPS5532117A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)

Abstract

PURPOSE: To control bus master request signals without alteration of the configulation of a bus priority control circuit even when plural I/O units (MIOs) with the mastering function are used.
CONSTITUTION: Bus master request signal (BSRQ) from each MIO is once entered into bus control unit (BSC), bus master request signals BSRQs from plural I/O units MIOs are regulated and controlled and then controlled signals BSRQs are applied to bus priority control circuit BPC. Bus control circuit BSC equips both flip-flop circuit FF on the input side of bus master request signals and circuit LTC which latches the output of flip-flop circuit FF by means of the responce signal from bus priority control circuit BPC.
COPYRIGHT: (C)1980,JPO&Japio
JP10460178A 1978-08-28 1978-08-28 Bus controlling device Pending JPS5532117A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10460178A JPS5532117A (en) 1978-08-28 1978-08-28 Bus controlling device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10460178A JPS5532117A (en) 1978-08-28 1978-08-28 Bus controlling device

Publications (1)

Publication Number Publication Date
JPS5532117A true JPS5532117A (en) 1980-03-06

Family

ID=14384932

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10460178A Pending JPS5532117A (en) 1978-08-28 1978-08-28 Bus controlling device

Country Status (1)

Country Link
JP (1) JPS5532117A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59101545U (en) * 1982-12-24 1984-07-09 横河電機株式会社 Common bus right management device
JPS61109167A (en) * 1984-11-01 1986-05-27 Nec Corp Multi-micro cpu control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59101545U (en) * 1982-12-24 1984-07-09 横河電機株式会社 Common bus right management device
JPS61109167A (en) * 1984-11-01 1986-05-27 Nec Corp Multi-micro cpu control system

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