JPS59101545U - Common bus right management device - Google Patents

Common bus right management device

Info

Publication number
JPS59101545U
JPS59101545U JP19894582U JP19894582U JPS59101545U JP S59101545 U JPS59101545 U JP S59101545U JP 19894582 U JP19894582 U JP 19894582U JP 19894582 U JP19894582 U JP 19894582U JP S59101545 U JPS59101545 U JP S59101545U
Authority
JP
Japan
Prior art keywords
bus right
management device
common bus
input nand
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19894582U
Other languages
Japanese (ja)
Inventor
敏夫 小川
赤井　創
Original Assignee
横河電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 横河電機株式会社 filed Critical 横河電機株式会社
Priority to JP19894582U priority Critical patent/JPS59101545U/en
Publication of JPS59101545U publication Critical patent/JPS59101545U/en
Pending legal-status Critical Current

Links

Landscapes

  • Arrangements For Transmission Of Measured Signals (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案を用いるシステムの概念構成図、第２図
は本考案の一実施例を示す構成説明図、第３図は本考案
の他の実施例を示す構成説明図、第４図は本考案で用い
るフィルター要素の具体例を示す回路図である。 ＣＴＬ・・・管理装置、ＴＭ・・・バス使用装置、ＬＡ
・・・バス使用権要求信号線、ＬＢ・・・ノ、（ス使用
権承認信号線、ＮＡＮＤ・・・ナントゲート、ＤＬＹ・
・・遅延回路、ＮＯＲ・・ウアゲート、ＩＮＶ・・・イ
ンバータ、Ｃ・・・キャパシタ、Ｂ・・・バッファ。Fig. 1 is a conceptual block diagram of a system using the present invention, Fig. 2 is a structural explanatory diagram showing one embodiment of the present invention, Fig. 3 is a structural explanatory diagram showing another embodiment of the present invention, Fig. 4 is a circuit diagram showing a specific example of a filter element used in the present invention. CTL...Management device, TM...Bus usage device, LA
...Bus use right request signal line, LB...No, (bus use right approval signal line, NAND...Nant Gate, DLY...
・・Delay circuit, NOR・・Urgate, INV・・Inverter, C・・Capacitor, B・・Buffer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ・　システム内の共通バスを共用する複数の装置がバス
使用権要求信号線及びバス使用権承認信号線を介して並
列に接続され、バス使用権要求信号を５　送出した装置
に対してバス使用権承認信号を返送するように構成され
た共通バス使用権管理装置において、各装置毎に多入力
ナンドゲート及びフイ　１ルター要素との直列回路を設
け、各多大カナンドゲートには対応した装置のバス使用
権要求信号及び他の各多入力ナンドゲートの出力信号を
加え、　′各多入カナンドゲートの出力信号を各フィル
タ一手段を介して対応した装置にバス使用権承認信号゛
、　　とじて送出することを特徴とする共通バス使用権
管理装置。- Multiple devices that share a common bus in the system are connected in parallel via the bus right request signal line and the bus right approval signal line, and the bus right is granted to the device that sent the bus right request signal. In a common bus right management device configured to return an approval signal, each device is provided with a series circuit with a multi-input NAND gate and a filter element, and each multi-input NAND gate is configured to send back a bus right request for the corresponding device. signal and the output signals of each of the other multi-input NAND gates, and send the output signal of each multi-input NAND gate to the corresponding device via each filter as a bus usage right approval signal. Common bus right management device.
JP19894582U 1982-12-24 1982-12-24 Common bus right management device Pending JPS59101545U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19894582U JPS59101545U (en) 1982-12-24 1982-12-24 Common bus right management device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19894582U JPS59101545U (en) 1982-12-24 1982-12-24 Common bus right management device

Publications (1)

Publication Number Publication Date
JPS59101545U true JPS59101545U (en) 1984-07-09

Family

ID=30424501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19894582U Pending JPS59101545U (en) 1982-12-24 1982-12-24 Common bus right management device

Country Status (1)

Country Link
JP (1) JPS59101545U (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4917641A (en) * 1972-06-05 1974-02-16
JPS5365034A (en) * 1976-11-22 1978-06-10 Nippon Telegr & Teleph Corp <Ntt> Competitive circuit
JPS5532117A (en) * 1978-08-28 1980-03-06 Fujitsu Ltd Bus controlling device
JPS57168324A (en) * 1981-04-09 1982-10-16 Fujitsu Ltd Bus control circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4917641A (en) * 1972-06-05 1974-02-16
JPS5365034A (en) * 1976-11-22 1978-06-10 Nippon Telegr & Teleph Corp <Ntt> Competitive circuit
JPS5532117A (en) * 1978-08-28 1980-03-06 Fujitsu Ltd Bus controlling device
JPS57168324A (en) * 1981-04-09 1982-10-16 Fujitsu Ltd Bus control circuit

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