JPS6082349U

JPS6082349U - Shared memory access control device

Info

Publication number: JPS6082349U
Application number: JP16978383U
Authority: JP
Inventors: 賢治大西
Original assignee: 株式会社明電舎
Priority date: 1983-11-01
Filing date: 1983-11-01
Publication date: 1985-06-07

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図はマルチプロセッサによるメモリ共有方式構成図
、第２図は本考案の一実施例を示す要部構成図、第３図
は第２図の動作説明のためのタイムチャート、第４図は
本考案の他の実施例を示す構成図である。１１．１□１３９１Ｎ・・・プロセッサ、２・・・共有
バス、３・・・共有メモリ、１１・・・メモリ使用優先
判定回路、１２・・・優先判定データラッチ回路、１３
・・・ラッチタイミングパルス発生回路、１４・・・使
用許可信号発生回路。Fig. 1 is a block diagram of a memory sharing system using a multiprocessor, Fig. 2 is a block diagram of main parts showing an embodiment of the present invention, Fig. 3 is a time chart for explaining the operation of Fig. 2, and Fig. 4 is a block diagram of a main part showing an embodiment of the present invention. FIG. 3 is a configuration diagram showing another embodiment of the present invention. 11.1□1391N...Processor, 2...Shared bus, 3...Shared memory, 11...Memory use priority determination circuit, 12...Priority determination data latch circuit, 13
. . . Latch timing pulse generation circuit, 14 . . . Use permission signal generation circuit.

Claims

[Scope of utility model registration request]

In a multiprocessor system in which one memory is shared and used by a plurality of processors, a shared memory usage right determination circuit is provided on the memory side, and when each processor generates a shared memory usage request signal to the determination circuit,
The determination circuit ignores the request signal when a request signal has already been given from another processor to generate a memory use permission signal in response to the request signal, and gives priority when multiple request signals are given at the same time. 1. A shared memory access control device comprising: control means for providing a memory use permission signal to a processor assignor in response to a determined request signal.