JPS63175249U - - Google Patents
Info
- Publication number
- JPS63175249U JPS63175249U JP6422587U JP6422587U JPS63175249U JP S63175249 U JPS63175249 U JP S63175249U JP 6422587 U JP6422587 U JP 6422587U JP 6422587 U JP6422587 U JP 6422587U JP S63175249 U JPS63175249 U JP S63175249U
- Authority
- JP
- Japan
- Prior art keywords
- accessing
- cpu
- memory modules
- memory
- wait
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の実施例を示すブロツク図、第
２図、第３図は本考案の実施例の動作を説明する
ために引用した図であり、それぞれＣＰＵの基本
タイミング、１ＷＡＩＴサイクル挿入のタイミン
グを示す。
１……ＣＰＵ、２……メモリ、３……アドレス
・データバス、４……出力ポート、６……メモリ
制御回路。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are diagrams cited to explain the operation of the embodiment of the present invention. Indicate timing. 1...CPU, 2...Memory, 3...Address/data bus, 4...Output port, 6...Memory control circuit.
Claims (1)
が実装されて成るコンピユータシステムにおいて
、上記メモリモジユール、ＣＰＵならびに出力ポ
ートとを接続するアドレス・データバスとシステ
ム起動時、上記メモリモジユールをアクセスして
タイミング条件をチエツクし、上記アドレス・デ
ータバスを介して出力ポートをアクセスしてウエ
イト信号生成指示を行なうＣＰＵ中の手段と、上
記ウエイト信号生成指示に基づきＣＰＵに対して
ウエイトサイクル挿入のための制御信号を生成す
ると共に上記メモリモジユールに対しアクセスの
ために所定のタイミング信号を生成出力するメモ
リ制御回路とを具備することを特徴とするコンピ
ユータシステム。 In a computer system in which memory modules with different access times are implemented, the address/data bus that connects the memory modules, CPU, and output ports and the timing conditions are determined by accessing the memory modules at system startup. means in the CPU for checking and accessing the output port via the address/data bus to instruct wait signal generation, and generating a control signal for inserting a wait cycle to the CPU based on the wait signal generation instruction. and a memory control circuit for generating and outputting a predetermined timing signal for accessing the memory module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6422587U JPS63175249U (en) | 1987-04-30 | 1987-04-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6422587U JPS63175249U (en) | 1987-04-30 | 1987-04-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63175249U true JPS63175249U (en) | 1988-11-14 |
Family
ID=30900188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6422587U Pending JPS63175249U (en) | 1987-04-30 | 1987-04-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63175249U (en) |
-
1987
- 1987-04-30 JP JP6422587U patent/JPS63175249U/ja active Pending
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