JPH05282244A - Information processor - Google Patents

Abstract

PURPOSE:To apply the opportunity of the usage of a bus to the other bus master even when a polling is operated. CONSTITUTION:An I/O 5 which receives the polling, returns a state change completion schedule signal indicating the schedule of the completion of the state change to a processor 1. Then, the processor 1 releases a bus usage signal by the state change completion schedule signal, and the other bus masters 2 and 3 can use the bus as necessary at that time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a plurality of bus masters on the same bus and sharing the bus.

[0002]

2. Description of the Related Art Conventionally, when a processor continuously polls I / O, it is necessary to prevent the processor from colliding with another bus master on the bus. Therefore, the processor uses the bus. While doing so, I was trying to prevent other bus masters from colliding with data.

[0003]

However, with such a configuration, other bus masters have to wait until the polling of the processor is completed, and there is no way to execute even if there is important processing.

The present invention has been made in view of such a situation, and it is intended to give another bus master an opportunity to use the bus even when polling is performed.

[0005]

In order to solve such a problem, the present invention provides a completion schedule information signal in which an I / O which receives polling information from a processor sends a schedule timing signal whose status change is completed. A sending means is provided.

[0006]

Since the polled I / O generates the state change completion schedule signal, interrupt processing or the like can be performed when the state change is completed, if necessary.

[0007]

1 is a block diagram showing a system according to an embodiment of the present invention. In FIG. 1, 1 is a processor, 2 and 3 are respective bus masters, and 5 and 6 are I / Os.

An interrupt control unit 4 controls the exchange of interrupts between the processor 1 or bus master 2 or 3 and the I / O 5 or 6. The control signals between the devices shown by 1 to 6 and the address and data signals are shown in FIG.

FIG. 2 shows the operations of the processor 1 and the interrupt controller 4 shown in FIG. In FIG.
Reference numeral 41 denotes a polling detection circuit that sets a flag indicating that the processor 1 has started polling, and 42 indicates that the I / O of the access destination to which the processor 1 has received the polling instruction sends a timing signal for completion of state change This is an information signal transmission circuit. This data is for all I
/ O is managed. 43 receives the interrupt signal a from the I / Os 5 and 6, so that the I / Os 5 and 6
It is a sense register that can see the interrupt status of.

Next, the operation will be described with reference to FIGS. 1 and 2. When the processor 1 tries to poll the I / O 5, first, the bus use signal b indicating that the processor 1 is using the bus is activated, and the processor 1 causes the interrupt control device 4 to operate. A polling start signal c indicating that polling is started is output to the polling detection circuit 41. Further continuously, the processor 1 outputs the address signal d to the sense register 43 of the interrupt control device 4 in order to read whether the I / O 5 has completed the state displacement. This is 1
This is the second poll.

Next, the completion schedule information signal transmission circuit 42
When the polling start signal c is input thereto and it is recognized that the first polling is input as the address signal d, the processor 1 receives the I / O 5, 6 from the address signal d.
Check which one you are accessing. Then, it outputs to the processor 1 a scheduled timing signal e indicating how much of the I / O remains and the state displacement is completed.

Next, the processor 1 makes the I / O of the access destination
When a scheduled timing signal e indicating how much state 5 is left to complete the state displacement is input as the data signal f, the bus use signal b indicating that the processor 1 is using the bus
Negate.

With the above configuration, the bus is released during the period given from the completion schedule information signal sending circuit 42 of the interrupt control device 4, so that the other bus masters 2 and 3 can use the bus. That is, since the processor does not continuously occupy the bus, another bus master can use the bus as needed.

[0014]

As described above, in the information processing apparatus according to the present invention, even when the processor continuously polls, the processor is released from the bus at the timing when the state change of the I / O being accessed is completed. Since this is done, another bus master can make an interrupt at this time if necessary.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing the operation of the apparatus of FIG.

[Explanation of Codes] 1 Processor 2, 3 Bus Master 4 Interrupt Control Device 5, 6 I / O

Claims (1)

[Claims] 1. An information processing apparatus having a plurality of bus masters, in which a processor recognizes a state displacement of I / O by polling, the I / O receiving polling information from the processor.
/ O is an information processing apparatus characterized by comprising a completion schedule information signal transmitting means for transmitting a schedule timing signal for completing the state change.