JPS5858649U

JPS5858649U - information processing equipment

Info

Publication number: JPS5858649U
Application number: JP11152782U
Authority: JP
Inventors: 遠藤一実; 宗像秀直; 丹羽昭男; 土岐田義明; 堀好徳; 矢沢勝彦
Original assignee: 日本電気株式会社
Priority date: 1982-07-22
Filing date: 1982-07-22
Publication date: 1983-04-20
Also published as: JPS5844427Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来の処理システムを示すブロック図、第２図
は本考案の一実施例の構成を示すブロック図、第３図は
第２図をさら番ミ詳細に示したブロック図である。ＳＷ、ＳＷｏ−ｗｓＷｉ・・・・・・通話路装置、ＣＰ
Ｒ・・・・・・メモリを含処理装置、ＮＰｏ〜ＮＰｉ、
　ＣＰｏ〜ＣＰｊ・・・・・・メモリを含む処理装置、
ＢＳｏ、　ＢＳｌ・・・・・・処理装置間バス、ＣＭＳ
・・・・・・共用メモリバス、ＢＣＴＩ、・・・・・・
バス制御装置、ＩＯ・・・・・・入出力装置、ＣＭ・・
・・・・共用メモリ、ＮＣＣｏ−ＮＣＣ１・−−−−−
制御装置、ＣＣｏ〜ｃＣｊ・・・・・・制御装置、ＬＭ
ｏｘＬＭｉ・・・・・・メモリ装置、Ｍ。〜Ｍｊ・・・・・・メモリ装置、ＢＣＴ・・・・・・バ
ス制御回路、ｌ０ＣＴ・・・・・・入出力装置制御回路
、ＭＣＴＬ・・・・・・メモリ制御回路、ＭＣＭ・・・
・・・メモリ装置、１０〜１ｉｊ・・・・・・信号線群
。FIG. 1 is a block diagram showing a conventional processing system, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is a block diagram showing FIG. 2 in more detail. SW, SWo-wsWi...Call path device, CP
R... Processing device including memory, NPo to NPi,
CPo to CPj...processing devices including memory;
BSo, BSl...Bus between processing units, CMS
・・・・・・Shared memory bus, BCTI, ・・・・・・
Bus control device, IO...Input/output device, CM...
...Shared memory, NCCo-NCC1・----
Control device, CCo~cCj...Control device, LM
oxLMi...Memory device, M. ~Mj... Memory device, BCT... Bus control circuit, l0CT... Input/output device control circuit, MCTL... Memory control circuit, MCM...
...Memory device, 10-1ij...Signal line group.

Claims

[Scope of utility model registration request]

In a multiprocessor system composed of a plurality of disparate information processing devices with disparate processing functions, a plurality of input/output processing devices whose main function is control of the communication path system and a plurality of call processing devices whose main function is call control. , a first bus circuit that connects the input/output processing devices, a second bus circuit that connects the call processing devices, and a system that controls the connection of the first and second bus circuits; It has a bus control circuit that connects commonly driven input/output devices and can be accessed simultaneously from the input/output processing device and call processing device, and a common memory that can be accessed simultaneously from multiple call processing devices, realizing an exchange control function. An information processing device characterized by: