JPS58113193U

JPS58113193U - display device

Info

Publication number: JPS58113193U
Application number: JP930782U
Authority: JP
Inventors: 聡中島; 辻田　宏
Original assignee: 日新電機株式会社
Priority date: 1982-01-25
Filing date: 1982-01-25
Publication date: 1983-08-02

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来から実施されてきた表示装置のブロックダ
イヤグラム、第“２図は本案品のブロックダイヤグラム
である。１・・・故障フリッカモードメモリ回路、２・・・選択
フリッカモードメモリ回路、３・・・状態表示モードメ
モリ回路、４・・・優先順位決定回路、５・・・表示部
、６・・・セット入力端子、７・・・リセット入力端子
、８・・・リセット入力端子。FIG. 1 is a block diagram of a conventional display device, and FIG. 2 is a block diagram of the proposed product. 1. Failure flicker mode memory circuit, 2. Selection flicker mode memory circuit, 3. ...Status display mode memory circuit, 4...Priority determining circuit, 5...Display section, 6...Set input terminal, 7...Reset input terminal, 8...Reset input terminal.

Claims

[Scope of utility model registration request]

(1) In a display device used in a central monitoring device, the display device is connected to a plurality of priority order determination circuits and to each of the priority order determination circuits, and the display device is connected to a plurality of priority order determination circuits and is connected to each of the priority order determination circuits, and a plurality of display units to be driven;
A plurality of fault flicker mode memory circuits, a selection flicker mode memory circuit, and a status display mode memory circuit are provided for inputting data corresponding to each of the priority determining circuits, and a reset function for each of the fault flicker mode memory circuits is provided. A display device characterized in that input terminals are commonly connected.

(2) The display device according to claim 1, wherein the display section emits light.