JPS60132060U - Input/output control circuit - Google Patents
Input/output control circuitInfo
- Publication number
- JPS60132060U JPS60132060U JP1857484U JP1857484U JPS60132060U JP S60132060 U JPS60132060 U JP S60132060U JP 1857484 U JP1857484 U JP 1857484U JP 1857484 U JP1857484 U JP 1857484U JP S60132060 U JPS60132060 U JP S60132060U
- Authority
- JP
- Japan
- Prior art keywords
- input
- control circuit
- transmission
- reception control
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Small-Scale Networks (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図および第２図はそれぞれ従来の入出力制御回路の
一例を示すブロック図、第３図は本考案の一実施例を示
すブロック図、第４図はプリンタおよび磁気カートリッ
ジを制御する場合の実施例を示すブロック図、第５図は
上記実施例の選択信号発生回路の構成を示す回路図であ
る。
図において、１：送受信制御回路、２：入出カライン切
替回路、３，４：マルチプレクサ回路、５：選択信号発
生回路、６：デマルチプレクサ回路、７：システムバス
、８：クロック発生回路、１１〜１ｎ：送受信制御回路
、２１〜２ｎニドライバ一／レシーバ回路、３１，３２
ニドライバ一回路、４１，４２：レシーバ回路。
□ ｌ −、ｌｌｒゴー］１１１１罰−−
Ｈ曲 Ｉ ＩＩ−ｍ−４３１１１１１露１゛ ′
示阿 −
２、Ｆ？”ｍ２ −1 and 2 are block diagrams each showing an example of a conventional input/output control circuit, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 is a block diagram showing an example of a conventional input/output control circuit. FIG. 5 is a block diagram showing the embodiment. FIG. 5 is a circuit diagram showing the configuration of the selection signal generation circuit of the above embodiment. In the figure, 1: transmission/reception control circuit, 2: input/output line switching circuit, 3, 4: multiplexer circuit, 5: selection signal generation circuit, 6: demultiplexer circuit, 7: system bus, 8: clock generation circuit, 11 to 1n : Transmission/reception control circuit, 21-2n driver/receiver circuit, 31, 32
2 driver circuit, 41, 42: receiver circuit. □ l-, llr go] 1111 punishment--
H song I II-m-4311111 1゛ ′ show - 2, F? ”m2-
Claims (1)
回路と、入出力機器との信号授受を制御する送受信制御
回路と、該送受信制御回路と複数の前記ドライバー回路
およびレシーバ回路との間に介装された入出カライン切
替回路とを備えて、゛前記送受信制御回路は複数の入出
力機器のうち任意の１つに対して送受信制御を行なうこ
とを特徴とする入出力制御回路。A driver circuit and a receiver circuit connected to the input/output device, a transmission/reception control circuit that controls signal exchange with the input/output device, and a transmission/reception control circuit interposed between the transmission/reception control circuit and the plurality of driver circuits and receiver circuits. An input/output control circuit comprising: an input/output line switching circuit, wherein the transmission/reception control circuit performs transmission/reception control on any one of a plurality of input/output devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1857484U JPS60132060U (en) | 1984-02-10 | 1984-02-10 | Input/output control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1857484U JPS60132060U (en) | 1984-02-10 | 1984-02-10 | Input/output control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60132060U true JPS60132060U (en) | 1985-09-04 |
Family
ID=30507337
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1857484U Pending JPS60132060U (en) | 1984-02-10 | 1984-02-10 | Input/output control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60132060U (en) |
-
1984
- 1984-02-10 JP JP1857484U patent/JPS60132060U/en active Pending
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