JPS58142753U

JPS58142753U - multiple access control device

Info

Publication number: JPS58142753U
Application number: JP3788682U
Authority: JP
Inventors: 北澤　慶司; 邦夫鈴木
Original assignee: 株式会社日立製作所
Priority date: 1982-03-19
Filing date: 1982-03-19
Publication date: 1983-09-26

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来の同一プリント板を複数用いた多重アクセ
ス制御装置のブロック図、第２図は従来の多種プリント
板を用いた多重アクセス制御装置のブロック図、第３図
は本考案の多重アクセス制御装置ブロック図、第４図は
本考案による制御回路内蔵ポートプリント板の内部構成
及び共通回路のブロック図である。１・・−ＣＰＵ、２・・・ポート、３・・・制御回路、
４・・・起動要求信号走査回路、５・・・ポート選択回
路、６・・・接続時間監視回路、７・・・制御回路を含
むプリント板、８・・・ポートのみを持つプリント板、
９・・・ファイル、置、１０・・・共通回路、１１・・
・起動要求信号、１２・・・起動要求信号個別線、１３
・・・故障連絡信号、１４・・・故障検出信号、１５・
・・接続許可個別信号、１６・・・故障検出回路。 ■ ■−上９−　−Figure 1 is a block diagram of a conventional multiple access control device using multiple identical printed boards, Figure 2 is a block diagram of a conventional multiple access control device using multiple types of printed boards, and Figure 3 is a multiple access control device of the present invention. Control Device Block Diagram FIG. 4 is a block diagram of the internal configuration and common circuit of the port printed board with built-in control circuit according to the present invention. 1...-CPU, 2... Port, 3... Control circuit,
4... Start request signal scanning circuit, 5... Port selection circuit, 6... Connection time monitoring circuit, 7... Printed board including control circuit, 8... Printed board with only ports,
9...File, location, 10...Common circuit, 11...
・Start request signal, 12...Start request signal individual line, 13
... Failure notification signal, 14... Failure detection signal, 15.
... Connection permission individual signal, 16... Failure detection circuit. ■ ■−Upper 9− −

Claims

[Scope of utility model registration request]

It is connected between a file device and a plurality of CPUs, and performs an operation of sequentially connecting the file device and the CPU by scanning the activation request signal of the CPU of each prefecture, and the plurality of CPUs connect the file device. In a shared multiple access control device, a plurality of switching devices are connected to a plurality of activation request signal buses, a plurality of persistence permission signal buses, and a common bus that is an interface signal line between the CPU and the file device. each of the switching devices receives the plurality of activation request signals from the plurality of activation request signal buses, sequentially scans the signals, and outputs a corresponding sustaining permission signal to the sustaining permission signal bus; The gate mechanism unit connects individual interface signals from the plurality of CPUs to the common bus. output to the activation request bus of the plurality of CPUs, open a gate circuit in response to the corresponding connection permission signal, and perform an operation of connecting the interface signals from the plurality of CPUs to the common bus, and each switching device connects the scanning circuit 1. A multiple access control device, characterized in that the multiple access control device is configured such that only one scanning circuit among all the switching devices performs the entire scanning.