JPS5992929U - Memory monitoring device for DMA device - Google Patents
Memory monitoring device for DMA deviceInfo
- Publication number
- JPS5992929U JPS5992929U JP18656782U JP18656782U JPS5992929U JP S5992929 U JPS5992929 U JP S5992929U JP 18656782 U JP18656782 U JP 18656782U JP 18656782 U JP18656782 U JP 18656782U JP S5992929 U JPS5992929 U JP S5992929U
- Authority
- JP
- Japan
- Prior art keywords
- dma
- memory
- data
- section
- memory monitoring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のＤＭＡ装置とメモリとの関係を示した構
成図、第２図は本考案の一実施例を示した構成図、第３
図は本考案のメモリ監視装置の機能ブロック図、第４図
は本考案を説明するためのメモリマツプ図、第５図り木
暑案を説明するたやのフローチャート図である。
１はメモリ、２１〜２ｎはＤＭＡ装置、３はメモリ管理
装置、３１はマイクロプロセッサ、３２はμＣＰＵのメ
モリ、３３は入出力インタフェース。Fig. 1 is a block diagram showing the relationship between a conventional DMA device and memory, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is a block diagram showing the relationship between a conventional DMA device and memory.
The figure is a functional block diagram of the memory monitoring device of the present invention, FIG. 4 is a memory map diagram for explaining the present invention, and Figure 5 is a flowchart diagram for explaining the plan. 1 is a memory, 21 to 2n are DMA devices, 3 is a memory management device, 31 is a microprocessor, 32 is a μCPU memory, and 33 is an input/output interface.
Claims (1)
のにおいて、前記各ＤＭＡ装置とメモリとの間にメモリ
監視装置を設け、該メモリ監視装置を、ＤＭＡ装置から
アドレス信号、Ｒ／Ｗ信号、デバイス識別信号とを入力
する入力部と、ブロックデータ、デバイスデータ、Ｒ／
Ｗデータとを記憶する記憶部と、アドレス信号、Ｒ／Ｗ
信号とをデバイス識別信号（千基づいて記憶部の各デー
タにより判定する比較部と、判定の結果Ｒ／Ｗ信号をメ
モリに出力するＲ／Ｗ信号出力部と、判定の結果エラー
信号をＤＭＡ装置に出力するエラー信号出力部とで構成
し備えたことを特徴とするＤＭＡ装置のメモリ監視装置
。In a device that performs DMA transfer between a plurality of DMA devices and a memory, a memory monitoring device is provided between each DMA device and the memory, and the memory monitoring device receives address signals, R/W signals, An input section for inputting device identification signals, block data, device data, R/
A storage section that stores W data, an address signal, and R/W.
a comparison section that determines the device identification signal based on each data in the storage section; an R/W signal output section that outputs the determination result R/W signal to the memory; and an R/W signal output section that outputs the determination result error signal to the DMA device. 1. A memory monitoring device for a DMA device, comprising: an error signal output section for outputting an error signal to a DMA device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18656782U JPS5992929U (en) | 1982-12-09 | 1982-12-09 | Memory monitoring device for DMA device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18656782U JPS5992929U (en) | 1982-12-09 | 1982-12-09 | Memory monitoring device for DMA device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5992929U true JPS5992929U (en) | 1984-06-23 |
Family
ID=30402949
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18656782U Pending JPS5992929U (en) | 1982-12-09 | 1982-12-09 | Memory monitoring device for DMA device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5992929U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018092486A (en) * | 2016-12-06 | 2018-06-14 | 日立オートモティブシステムズ株式会社 | Automobile electronic controller and abnormality detection method of dma controller |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS551675A (en) * | 1978-06-21 | 1980-01-08 | Toshiba Corp | Memory protect control system |
| JPS55119720A (en) * | 1979-03-09 | 1980-09-13 | Tokyo Electric Power Co Inc:The | Operation processing unit |
-
1982
- 1982-12-09 JP JP18656782U patent/JPS5992929U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS551675A (en) * | 1978-06-21 | 1980-01-08 | Toshiba Corp | Memory protect control system |
| JPS55119720A (en) * | 1979-03-09 | 1980-09-13 | Tokyo Electric Power Co Inc:The | Operation processing unit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018092486A (en) * | 2016-12-06 | 2018-06-14 | 日立オートモティブシステムズ株式会社 | Automobile electronic controller and abnormality detection method of dma controller |
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