JPS5953564B2 - data processing equipment - Google Patents

Description

[Detailed description of the invention] The present invention relates to a data processing device.

In a conventional data processing device, as shown in FIG. 1, a main storage device 12, central processing unit 1, first input/output control device 2, second input/output control device 3, etc. Data is being transferred between.

Each bus control circuit 4 has a dedicated bus use request signal line 5.
. and 10, a bus use permission signal is sent to the selected device via bus use permission signal lines 8, 9, and 10. A device given this permission signal becomes capable of data transfer with the main storage device. Although the example in Figure 1 shows the case where there are two input/output control devices, the same applies to the case where there are n input/output control devices.
+1) There is a drawback that a number of bus use request signal lines are required, making it difficult to simplify the circuit.

The object of the present invention is to provide a data processing device that eliminates the above-mentioned drawbacks.

The data processing device of the present invention includes means for sending out a bus use request enable signal; One means for sending a bus use request signal to a corresponding address line of an address bus consisting of a predetermined number of address lines in response to a bus use request, and sending the enable signal. means for continuously transmitting the enable signal in response to a bus use request not being issued to the central processing unit and all of the plurality of input/output devices during a predetermined period of the bus cycle;
When the bus use request signal is sent from the central processing unit and the plurality of input/output devices to the address bus, one of these devices is selected according to a predetermined priority order, and the selected device is sent to the selected device. The device has a configuration including means for sending out a bus use permission signal.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 2a is a diagram showing information on the bus, and FIG. 2b is a diagram showing a bus use request enable signal.

Generally, address information does not occupy the entire period of bus cycle B. Therefore, in the present invention, as shown in FIG. 2a, bus use request information is given during the unused period of bus cycle B, and the bus is used in a time-sharing manner. FIG. 3 is a diagram showing an embodiment of the present invention.

Bus use request signal lines 5, 6 and 7 shown in FIG. 1 are overlapped within bus 11 and therefore do not exist. The bus permission signal encoded by the bus control circuit 4 and applied to the bus permission signal lines 8, 9 and 10 is decoded by the central processing unit 1 and the first and second input/output devices 2 and 3. Ru. Because of this type of system, it is also possible to further reduce the number of signal lines. The operation of this embodiment will be explained using timing charts shown in FIGS. 4a to 4e.

Figures a and b show the bus use request signals of the second and first input/output devices, respectively, C shows the bus use request signal of the central processing unit, and d shows the bus allocation. The figure shown in FIG. The bus usage priority is second input/output device 3>first input/output device 2>central processing unit 1. Immediately before bus cycle B1, bus usage requests from the first and second input/output devices are generated simultaneously, but the second input/output device is selected in bus cycle B1 according to the set usage priority, Data transfer between the second input/output device 3 and the main storage device 12 becomes possible.

The first I/O device's bus use request is suspended until the second I/O device's data transfer is completed, and bus cycle B
If there is no use request from a device with a higher priority when determining the use request for the next cycle performed in the latter half of bus cycle B2, the first input/output device is selected in the next bus cycle B2. After bus cycle B2 is completed, if no bus use request is issued from any device, the bus use request enable signal remains at a high level, that is, it waits in a request acceptance state (see e in the figure).

After this, a bus usage request from the central processing unit occurs,
Bus cycle B3 is occurring. Next, a specific circuit of this embodiment will be explained with reference to FIG. The central processing unit 1 has an address register 24 that holds address information.
, a bus use request register 26, output gates 25 and 27 to the address bus, and a gate 28 that controls opening and closing of the output gates. When it is desired to directly transfer data to and from the main storage device 12 using the bus, the bus use request register 26 is set.

When the bus use request enable signal generated from the bus control circuit goes high at the timing shown in FIG. 2, the output of register 26 is applied to address ADO. In addition, in the first input/output device 2, the output of the bus use request register 30 is given to ADl, and in the same way, in other devices, the outputs of the respective bus use request registers are overlapped with each corresponding address line. It is given to you not to do so. The bus use request signal applied to the address bus is taken into the detection latch 20 of the bus control circuit 4, and when simultaneous requests are received from multiple devices, the priority determination circuit 21
The priority is determined, and a bus use permission signal is sent to the selected device from the bus cycle latch 22 for one cycle.

For example, when the central processing unit 1 is selected, the bus use enable signal 8 becomes high level, and while the bus use request enable signal 29 is low level, the information in the register 24 is sent to the main memory 12 via the address bus. can be accessed.

Bus use request enable signal 29 during the same bus citation
When becomes high level, the address bus enters the bus use request detection mode for the next bus cycle. At this time, bus use request signals from each device are output to the bus, respectively.
The signal is captured by the detection latch 20. As described above, the present invention has the effect that the interface between each device can be simplified by using the bus in a time-sharing manner.

[Brief explanation of the drawing]

FIG. 1 shows a conventional example, FIGS. 2a and 2b show information on the bus and a bus use request enable signal, respectively, and FIG. 3 shows an embodiment of the present invention. 4
Figures a to e are timing charts of the embodiment, and Fig. 5 is a diagram showing a specific circuit of the embodiment. In the figure, 1... central processing unit, 2... first input/output device, 3... second input/output device, 4... bus control circuit, 5, 6, 7... bus Use request signal line, 8, 9
, 10... Bus use permission signal line, 11... Bus, 1
2... Main memory device, 20... Detection latch, 21...
・Priority determination circuit, 22... bus cycle latch,
23... Enable signal generation circuit, 24... Register, 25, 27, 28... Gate, 26, 30...
Bus use request register 29...Bus use request enable signal line.

Claims (1)

[Claims] 1. Sending a bus use request enable signal in a data processing device having a main storage device, a central processing unit, a plurality of input/output devices, and an input/output control device that can directly access the main storage device without going through the central processing unit. and means for responding to a bus use request generated by the central processing unit and at least one of the plurality of input/output devices while the enable signal is being sent during a predetermined period of a bus cycle. means for sending a bus use request signal to the corresponding address line of an address bus consisting of a predetermined number of address lines; and means for continuously transmitting the enable signal in response to a bus use request when none of the plurality of input/output devices has been issued, and a means for continuously sending the enable signal from the central processing unit and the plurality of input/output devices to the address means for selecting one of these devices according to a predetermined priority when the bus use request signal is sent to the bus, and sending a bus use permission signal to the selected device. Characteristic data processing device.