RU2217791C1 - Data input device - Google Patents

Abstract

FIELD: processing in-flight data to estimate aircraft serviceability and in-flight response of crew. SUBSTANCE: proposed data input device noted for reduced time and enhanced quality of processing aircraft in-flight data has forward- channel amplifier-shaper, inversion-channel amplifier-shaper, code converter, channel selector switch, code selection unit, memory unit, ISA bus address decoder, control register, command decoder, interrupt signal shaper, and data control and processing unit. EFFECT: reduced labor consumption and maintenance charges for aircraft equipment. 4 cl, 13 dwg

Description

 The invention relates to information-measuring equipment, namely to measuring information storage devices used to diagnose the condition of an object, for example an aircraft, and to evaluate the actions of maintenance personnel, for example, an aircraft crew.

 The prior art.

 The technical solution of the device for inputting information is known - USSR copyright certificate 1737437 A1, class. G 06 F 3/00, 1992.

 The closest analogue is a device for entering information accumulated by digital magnetic recording means - USSR copyright certificate 1688236 A1, class. G 06 F 3/00, 1991. The known device contains a block of amplifiers-shapers, three shapers, a memory block, a counter, a code register, a block for selecting information, a trigger and a pulse generator.

The disadvantages of this design include
- the inability to process a sequential two-frequency code;
- the lack of the ability to connect to the processing device registration means (sources) of parallel and serial code;
- the inability to convert serial code to parallel;
- the inability to control the registration device in an automated mode.

 SUMMARY OF THE INVENTION

 The basis of the proposed technical solution is the idea of creating a device for inputting information from ground-based devices for reproducing flight information from aircraft on-board recording devices into the memory of a personal computer for its further processing.

 The aim of the invention is to reduce the complexity and cost of maintenance of aircraft by reducing the processing time of flight information and improving the quality (reducing losses, increasing the reliability of the read information) of its processing during operation of the aircraft.

 This is achieved by the fact that the information input device containing two amplifier-shaper, the interrupt signal conditioner and the memory unit further comprises a control and processing unit, an address decoder, a control register, an instruction decoder, a code converter, a channel selector and a code selection unit, the output of which is connected with the first input of the channel selector. The output of the direct channel amplifier-driver is connected by a data bus to the second and through the code converter to the third inputs of the channel selector, the first output of which is connected to the first input of the memory unit, the second output of which is connected to the second inputs of the control and processing unit and control register, and the second input of the unit memory is connected to the second output of the address decoder, the first output of which is connected to the first input of the control register, the first output of which is connected by a data bus through the command decoder to the inputs of the device in playback, and the second output is connected to the second inputs of the amplifier-drivers, the first input of each of which is connected by a data bus with the output of the corresponding playback device. In this case, the second output of the channel selector and the output of the inverse channel amplifier-driver are connected to the third input of the memory unit, and the first and second outputs of the control and processing unit are connected respectively to the first and second inputs of the address decoder, the third output is connected to the third input of the address decoder, the fourth output is connected to the fourth input of the address decoder and the first input of the driver of the interrupt signal, and the fifth output is connected to the second input of the driver of the interrupt signal, the output of which is connected nen to third input control and processing unit, a first input coupled to the first output of the storage unit.

 The code converter includes a reference frequency generator, a frequency divider, a channel selector, an account resolution trigger, a counter, a decoder, a D-trigger, and an exclusive OR element, the output of which is the output of the code converter. The output of the reference frequency generator is connected to the input of the frequency divider, the first output of which is connected to the clock input of the counter, and the second output is connected to the clock input of the channel selector, the second input of which is connected to the first inputs of the exclusive-OR element and the D-trigger code converter input. The output of the channel selector through the counting resolution trigger is connected to the second input of the counter, the outputs of which are connected to the corresponding inputs of the decoder, the first output of which is connected to the second input of the counting trigger, the second output is connected to the second input of the D-trigger, the output of which is connected to the second input of the element exclusive OR. " The third output of the decoder and the output of the exclusive OR element are the output of the code converter.

 The channel selector includes a bit counter, a shift register and a multiplexer, the outputs of which are connected to the corresponding inputs of the shift register, and the second output is also connected to the input of the bit counter. Moreover, the inputs of the multiplexer are the inputs of the channel selector, and the outputs of the bit counter and the shift register are the outputs of the channel selector.

 The memory unit may be made in the form of a dual-port random access memory.

 The list of figures drawings.

Figure 1 is a functional diagram of an information input device;
figure 2 is a functional diagram of a code converter;
figure 3 is a functional diagram of a channel selector;
4 is a timing diagram of the operation of the code Converter;
FIG. 5 are timing diagrams of converting information from two-level code to parallel code.

 The best embodiment of the invention.

 The information input device comprises (Fig. 1) a direct-channel amplifier-driver 1, an inverse channel amplifier-driver 2, a code converter 3, a 4-channel switch, a code selection unit 5, a memory unit 6 based on a dual-port RAM (DOS), a decoder 7 addresses of the ISA bus, control register 8, decoder 9 commands, shaper 10 of the interrupt signal and block 11 control and data processing.

 The code converter 3 includes (Fig. 2) a reference signal generator 12, a frequency divider 13, a channel selector 14, a count resolution trigger 15, a counter 16, a decoder 17, a D-trigger 18, and an exclusive OR element 19.

 The switch 4 channels, includes (Fig. 3) includes a counter 20 bits, shift register 21 and multiplexer 22.

 The information input device operates as follows.

 Only one playback device can be connected to the input of each amplifier-driver 1 or 2, flight information must be read from each of them. At the same time, a playback device 23 is always connected to the driver amplifier 1, in which flight information is always recorded only in a sequential code (two-level - ARINC or two-frequency - GARVARD), and a playback device 24 is always connected to the driver amplifier, in which flight information is always recorded only in parallel inverse code. Amplifiers-shapers 1 and 2 amplify and generate information signals from playback devices and feed them to the switch 4 channels. At one time, information is read from only one of the playback devices 23 or 24. Therefore, using the switch of 4 channels, the corresponding channel is selected for sequentially reading information from each of the playback devices 23 and 24 and receiving it for recording in DOSE 6. The type of playback device from which the information will be read (number of the selected channel) determines the control register 8, the second output of which is connected to the control second inputs of the amplifiers-shapers 1 and 2. The control register 8 determines the operation mode of the playback devices (recording, playback, rewinding, etc. ) The decoder 9 commands receives the mode number from the control register 8, decrypts it and sends it to the playback device.

 If the playback device 24 is included in the playback mode, then the information from it recorded in the parallel code passes through the amplifier-driver 2 directly to the DOSE 6, because in DOSE 6, information is accumulated only in parallel code.

 When the playback device 23 is turned on in the playback mode, the information from it passes through the amplifier-driver 1 and, if it is recorded in a sequential two-level code, it goes directly to the second input of the 4-channel switch, and if it is recorded in a sequential two-frequency (Harvard) code , then through the converter 3 code enters the third input of the switch 4 channels. The determination of the connection of the required input of the 4-channel switch is carried out by the code selection unit 5.

 Code converter 3 converts flight information recorded in a two-frequency code into information recorded in a two-level code. In this case, the logic 1 signal is sent from the code selection unit 5 to the multiplexer 22 and the multiplexer 22 is connected to the output of the code converter 3. The conversion of information from a two-frequency code into a two-level code with gating is as follows. Bits of information are transmitted along the same line with the period T (Fig. 4, Diagram 1). Moreover, if in any period the signal changes its state, then in this period T a "logical 0" is transmitted. Data in a two-frequency (Harvard) code is fed to the inputs of the channel selector 14, the D-flip-flop 18, and the exclusive-OR element 19. The channel selector 14 generates a signal (Fig. 4, Diagram 2) with a duration of 0.1 μs each time, at its input, the logic level changes from "0" to "1" or from "1" to "0". This signal sets to “logical 1” (Fig. 4, Diagram 3) a count resolution trigger 15, which allows the counter 16 to read pulses with a frequency of 1 MHz coming from a frequency divider 13. A frequency divider 13 associated with the reference frequency generator 12 also generates a 20 MHz signal necessary for the operation of the channel selector 14. The counter 16 begins to count and on the first clock cycle, which corresponds to 1 μs, writes the data state to the D-trigger 18. The write signal (Fig. 4, Diagram 4) in the D-trigger 18 is implemented by the decoder 17 from the second output - "1" ( 1 μs). The exclusive-OR element 19 receives data from the amplifier-former 1 and signals from the D-flip-flop 18. If the same signals are received at its inputs, then it has a “logical 0” at the output, otherwise, “logical 1”. If the bit arriving in the period T (Fig. 4, Diagram 1) is equal to 1, then by the time the signal is triggered (Fig. 4, Diagram 5) from the third output - "56" (56 μs) - of the decoder 17 at the inputs of the element 19 "exclusive OR" will be different signals, then its output will be "logical 1". The signal "56" writes the output state of the element 19 "exclusive OR" through the multiplexer 20 to the shift register 21, and the signal (Fig. 4, Fig. 6) from the first output of the decoder 17 - "57" (57 μs) - will reset the trigger trigger 15 account and prohibit the operation of the counter 16 until the arrival of a new bit. If the next bit is also equal to 1, then the processing of this bit will be repeated. If the next bit is 0, then for 56 μs of the next period, the output of the exclusive-OR element 19 will have the same signals, since the signal state has not changed over the period and the signal "56" will write the value of "logical 0" to the shift register 21 (Fig. 4, Diagram 7).

 Thus, information recorded only in a two-level code is supplied to the 4-channel switch.

 Conversion of flight information from a sequential two-level code to a parallel 16-bit code for writing to DOS 6 is carried out using the shift register 21 and the counter 20 bits. In this case, the “logic 0” signal is sent from the code selection unit 5 to the multiplexer 22 and the multiplexer 22 is connected directly to the output of the amplifier-former 1, from which the data (Fig. 5, Diagram 1) and the gating signal (Fig. 5, Diagram . 2) are fed to the inputs of the multiplexer 22. Data is written bitwise with a shift to the shift register 21, and the counter 20 bits generates a write signal after the shift of each 16 bits. Converted to a parallel 16-bit code, the flight information data is recorded in DOSE 6 by the signal "record" (Fig. 5, Diagram 3).

 As DOSE 6 is filled, it generates a DRQ signal for direct memory access to the ISA bus at the first output, notifying the control and processing unit 11 of the need to read data from DOSE 6. In response to the DRQ request, block 11 generates a DACK response signal on the fourth output, which it is converted by the decoder 7 addresses into the signals RDL and RDH, which control the resolution of the outputs of the DOS 6, i.e. when these signals are activated, information is read from DOSE 6 to the memory buffer of the control and processing unit 11. The address decoder 7 also generates a WRcommand signal, which records the commands and the number of the selected channel in the control register 8. The IOWR and IORD signals gate the RDL / RDH and WRcommand signals, respectively. Upon completion of the process of writing information to the memory buffer, the control and processing unit 11 generates a TC signal, which is fed to the first input of the interrupt signal generator 10, which generates an interrupt signal INT. In response to this signal, the control and processing unit 11 retunes the reception of information to the next memory buffer and the process of receiving information continues. This process continues until a command to stop the playback device is received in the control register 8.

 Industrial applicability.

 This device can be manufactured using well-known transistor arrays 125HT1, IC 74HC (HCT, ALS) 14, IC 74CH (HCT, ALS) 245, ALTERA EPM 7128 STC-84-15. As a control and data processing unit, a standard PC / AT computer with an ISA system bus can be used without any additional modifications. Most effectively, the present invention can be used to process flight information in order to assess the technical condition of the aircraft and the actions of the crew during the flight.

Claims (4)

1. An information input device comprising two amplifier-shaper, an interrupt signal conditioner and a memory unit, characterized in that a control and processing unit, an address decoder, a control register, an instruction decoder, a code converter, a channel selector and a code selection unit are introduced into it, the output of which is connected to the first input of the channel selector, the output of the amplifier-driver of the direct channel is connected by a data bus to the second and through the code converter to the third inputs of the channel selector, the first output of which connected to the first input of the memory unit, the second output of which is connected to the second inputs of the control and processing unit and the control register, and the second input of the memory unit is connected to the second output of the address decoder, the first output of which is connected to the first input of the control register, the first output of which is connected by a data bus through a command decoder with inputs of playback devices, and the second output is connected to the second inputs of the amplifier-drivers, the first input of each of which is connected by a data bus to the output of the corresponding playback channels, while the second output of the channel selector and the output of the inverse channel amplifier-driver are connected to the third input of the memory unit, and the first and second outputs of the control and processing unit are connected respectively to the first and second inputs of the address decoder, the third output is connected to the third input by the address bus address decoder, the fourth output is connected to the fourth input of the address decoder and the first input of the chopper, and the fifth output is connected to the second input of the chopper Bani, whose output is connected to the third input control and processing unit, a first input coupled to the first output of the storage unit. 2. The information input device according to claim 1, characterized in that the code converter includes a reference frequency generator, a frequency divider, a channel selector, an account resolution trigger, a counter, a decoder, a D-trigger and an exclusive OR element, the output of which is the output of the converter code, while the output of the reference frequency generator is connected to the input of the frequency divider, the first output of which is connected to the clock input of the counter, and the second output is connected to the clock input of the channel selector, the second input of which is connected to the first inputs The element of the exclusive OR and D-flip-flops is the input of the code converter, the output of the channel selector through the counting trigger is connected to the second input of the counter, the outputs of which are connected to the corresponding inputs of the decoder, the first output of which is connected to the second input of the counting trigger, the second output is connected to the second input of the D-flip-flop, the output of which is connected to the second input of the Exclusive OR element, and the third output of the decoder and the output of the Exclusive OR element are the output of the code converter. 3. The information input device according to claim 1, characterized in that the channel selector includes a bit counter, a shift register and a multiplexer, the outputs of which are connected to the corresponding inputs of the shift register, and the second output is also connected to the input of the bit counter, the inputs of the multiplexer being channel switch inputs, and the bit counter and shift register outputs are channel switch outputs. 4. The information input device according to claim 1, characterized in that the memory unit is made in the form of a dual-port random access memory.

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