JPH05108555A - Bus use right arbitrating device - Google Patents

Abstract

PURPOSE:To preferentially impart the use right of a bus to a specified transmitter. CONSTITUTION:The device number of the transmitter is previously written in a memory 13. When the device number is written in an address having a smaller value of written while overlapping a lot of addresses, the priority of the transmitter is more improved. A counter 40 cyclically counts clocks from an oscillator 2 and applies the counted result through a selector 14 to the memory 13 as an address. As the result, the device number cyclically read from the memory 13 is supplied to a decoder 6, and the decoder 6 outputs a signal at a high level to a signal line corresponding to the device number. When transmission request signals REQ0-REQN at the high level are inputted from the correspondent transmitter to an AND gate 8 receiving the signal at the high level, the AND gate outputs transmission permit signals ACK0- ACKN at the high level to the correspondent transmitter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus use right arbitration device for arbitrating the bus use right of a plurality of transmitters using a data bus.

[0002]

2. Description of the Related Art Conventionally, this type of bus right arbitration device is
Whether or not each transmission device outputs a transmission request is confirmed in the order of the transmission device numbers, and when the transmission request is confirmed, the bus usage right is given to the device.

FIG. 2 shows an example of such a conventional bus right arbitration device. The device 100 includes an oscillator 2, and the processor unit 3 and the counter 4 operate based on a clock CLK output from the oscillator 2. When the processor unit 3 outputs the arbitration start signal START, the gate 5 composed of an AND gate is opened, the high level operation permission signal is input to the counter 4, and the counter 4 starts the counting operation of the clock CLK. The count value of the counter 4 corresponds to the device number of the transmitting device, and the counter 4 is reset when the number of clocks corresponding to the number of transmitting devices is counted, and starts counting from zero again.

When the arbitration start signal is given, the decoder 6 decodes the output of the counter 4 and outputs a high level signal to the signal line corresponding to the count value of the counter 4, and thus to the signal line corresponding to the transmitter. As a result, if the high-level transmission request signals REQ0 to REQN are input from the corresponding transmitter to the AND gate 8 that has received the high-level signal, the AND gate permits the high-level transmission to the corresponding transmitter. The signals ACK0 to ACKN are output. When the transmission device receives the transmission permission signal, it means that the use of the bus is permitted, and the data transfer is performed using the data bus.

Each input of the NOR gate 10 is an AND gate 8.
When one of the AND gates 8 outputs a high level transmission permission signal, it is connected to each output of the NOR gate 10
Outputs a low level signal. As a result, the gate 5 is closed and the operation permission signal is not input to the counter 4, so the counter 4 stops the counting operation.
Therefore, the decoder 6 continuously outputs a high level signal to a specific signal line, and the transmission permission signal is continuously given to the transmitting device to which the transmission permission signal has been once given. After that, the transmission device transmits the transmission request signals REQ0 to REQ.
When the output of the EQN is stopped, the output of the AND gate 8 corresponding to the transmitter becomes low level, and the NOR gate 1
Since the high level output is not input to 0 and the output of the NOR gate 10 returns to the high level, the gate 5 is opened again and the counter 4 restarts the counting operation.
Then, each unit operates in the same manner again, and then the transmission permission signal is output to the transmitting device that has output the transmission request signal.

[0006]

However, in such a conventional bus right-of-use arbitration device, the presence or absence of a transmission request from each transmission device is checked in the order of the number of the transmission device, and the transmission device that has issued the transmission request is checked in order. Only the right to use the bus can be given, and the right to use the bus cannot be given priority to a specific transmitting device.

An object of the present invention is to solve such a problem and to provide a bus right-of-use arbitration apparatus which can give a right to use a bus by giving priority to a specific transmitting apparatus.

[0008]

According to the present invention, when one or more of a plurality of transmitters transmit a transmission request signal, a predetermined transmission is sent to one of the transmitters that transmitted the transmission request signal. In a bus right arbitration device that outputs a permission signal to permit the use of a data bus, storage means in which a device number representing the transmission device is stored, and address generation means for cyclically giving a read address to the storage means. A permission signal transmitting means for transmitting the transmission permission signal to the transmission device indicated by the device number read from the storage means.

[0009]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 shows an example of a bus right arbitration device according to the present invention. This device is different from the device of FIG. 2 in that a memory 13 is provided and the device number written in the memory 13 is stored in the decoder 6
It is a point that is sequentially given to.

The memory 13 has a capacity capable of storing more device numbers than the number of transmitting devices managed by the bus right arbitration device 1. The data DATA output from the processor unit 3 is transferred to the memory 1 through the gate 11.
Address AD supplied to processor 3 and output by processor unit 3
The RS is supplied to the memory 13 through the selector (SEL) 14. The write signal WRITE output from the processor unit 3 is input to the write signal input terminal WR of the memory 13 through the gate 12. The read signal input terminal RD of the memory 13 is an inverted version of the write signal input to the terminal WR. The data read from the memory 13, that is, the device number is given to the decoder 6.

The processor unit 3 and the counter 40 are operated by the clock CLK from the oscillator 2 as in the conventional case. The counter 40 is reset after counting the clock CLK by the number of device numbers stored in the memory 13, and starts counting from zero again. The count output is the selector 14
Has been entered in. A write signal WRITE output from the processor unit 3 is input to the selector 14 through the gate 12 as a selection signal.
When E is low level, the address ADRS is stored in the memory 13
On the other hand, when the write signal WRITE is at high level, the count output of the counter 40 is given to the memory 13 as an address.

The gates 11 and 12 are controlled by the arbitration start signal START output from the processor unit 3. When the arbitration start signal START is low level, the gate 11 outputs the data DATA to the memory 13 and the gate 12 outputs the write signal. WRITE is output to the memory 13. on the other hand,
When the arbitration start signal START is at a high level, the gate 11 sets its output on the memory 13 side to high impedance, and the gate 11 also sets its output to high impedance.

Next, the operation will be described. The processor unit 3 writes the device number to the memory 13 before outputting the arbitration start signal START at a high level to start the arbitration operation of the bus use right. That is, in the state where the processor unit 3 outputs the low-level arbitration start signal START, the selector unit 14 causes the address A from the processor unit 3 to operate.
The DRS is selected, and the data DATA and the write signal WRITE output from the processor unit 3 are supplied to the memory 13 through the gates 11 and 12, respectively. Then, the processor unit 3 sequentially outputs the address ADRS, outputs the device number as the data DATA each time, and further outputs the write signal WRITE to output the memory 1 to the memory 1.
Write the device number in 3. At that time, the processor unit 3
The device number of a transmitting device having a higher priority of bus use is written to an address having a smaller value, and the device number of a transmitting device having a higher priority is redundantly written to a larger number of addresses.

After writing such a device number, the processor unit 3 outputs a high-level arbitration start signal START. As a result, the output of the gate 12 becomes high impedance, and as a result, it becomes high level and the selector 1
4 is a memory 1 using the count output of the counter 40 as an address
3 and a read signal input terminal R of the memory 13
A low level signal is input to D, and the memory 13 is in a read state. On the other hand, the output of the gate 11 on the memory 13 side also becomes high impedance, and the device number read from the memory 13 is given to the decoder 6.

When the processor unit 3 outputs the high level arbitration start signal START, the gate 5 formed of an AND gate is opened, the high level operation permission signal is input to the counter 40, and the counter 40 counts the clock CLK. To start. The count value of the counter 40 is given as an address to the memory 13 through the selector 14, and the memory 13 outputs the device number stored at the address. The counter 40 is reset when counting the clock CLK by the number of device numbers stored in the memory 13 as described above, and starts counting from zero again.
3 cyclically reads and outputs the stored device number.

Since the decoder 6 is supplied with the high level arbitration start signal START, it decodes the device number output from the memory 13 and outputs the signal line corresponding to the device number.
Therefore, a high level signal is output to the signal line corresponding to the transmitter. As a result, if the high-level transmission request signals REQ0 to REQN are input from the corresponding transmitter to the AND gate 8 that has received the high-level signal, the AND gate permits the high-level transmission to the corresponding transmitter. The signals ACK0 to ACKN are output. When the transmission device receives the transmission permission signal, it means that the use of the bus is permitted, and the data transfer is performed using the data bus.

Each input of the NOR gate 10 is an AND gate 8.
When one of the AND gates 8 outputs a high level transmission permission signal, it is connected to each output of the NOR gate 10
Outputs a low level signal. As a result, the gate 5 is closed and the operation permitting signal is not input to the counter 40, so that the counter 40 stops the counting operation. Therefore, the decoder 6 continuously outputs a high level signal to a specific signal line, and the transmission permission signal is continuously given to the transmitting device to which the transmission permission signal has been once given. After that, the transmission device transmits the transmission request signals REQ0 to REQ0.
When the output of REQN is stopped, the output of the AND gate 8 corresponding to the transmitting device becomes low level, the high level signal is not input to the NOR gate 10, and the output of the NOR gate 10 returns to high level. The counter 40 is opened again and the counting operation is restarted. Then, each unit operates in the same manner again, and then the transmission permission signal is output to the transmission device that has output the transmission request signal.

[0018]

As described above, according to the present invention, when one or more of a plurality of transmitters transmit a transmission request signal, one of the transmitters that has transmitted the transmission request signal is predetermined. In a bus right arbitration device that outputs a transmission permission signal to permit the use of a data bus, a storage unit that stores a device number that represents the transmission device, and an address generation unit that cyclically gives a read address to the storage unit. A permission signal transmitting means for transmitting a transmission permission signal to the transmission device indicated by the device number read from the storage means. Therefore, in the bus right arbitration device of the present invention, the priority of each transmitting device can be arbitrarily determined according to the order in which the device numbers are stored in the storage means, and how many times the same device number is stored in duplicate. Can be set.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a bus right arbitration device according to the present invention.

FIG. 2 is a block diagram showing an example of a conventional bus usage right arbitration device.

[Explanation of symbols]

 1 bus right arbitration device 2 oscillator 3 processor unit 5, 11, 12 gate 6 decoder 8 AND gate 10 NOR gate 13 memory 40 counter

Claims (3)

[Claims] 1. When one or more of a plurality of transmitters transmit a transmission request signal, a predetermined transmission permission signal is output to one of the transmitters that transmitted the transmission request signal to output the data bus. In the bus usage right arbitration device that permits the use of the storage device, a storage unit that stores a device number that represents the transmission device, an address generation unit that cyclically gives a read address to the storage unit, And a permission signal transmitting means for transmitting the transmission permission signal to the transmission device indicated by the device number. 2. The address generating means includes an oscillator for generating a clock signal, and a counter for counting the clock signal generated by the oscillator and giving a count result to the storage means as the address. The bus right arbitration device according to claim 1. 3. The permission signal sending means includes a decoder for receiving the device number read from the storage means and outputting a predetermined signal to a signal line corresponding to the device number, and each of the transmitting devices. When the corresponding transmission request signal is received from the corresponding transmission device and the predetermined signal is received from the decoder through the corresponding signal line, the transmission permission signal is output to the corresponding transmission device. 2. The bus right arbitration device according to claim 1, further comprising a plurality of logic circuits that perform the above.