JPS61170142A - Serial data processing unit - Google Patents

Abstract

PURPOSE:To attain ease of processing of a microcomputer by adopting serial form for transmission/reception of a data to/from the microcomputer so as to minimize the number of interfaces in comparison with that of a parallel form and counting a clock signal so as to decode generation of an instruction in the inside of the titled device. CONSTITUTION:An instruction decoding section 2 samples a command signal 3 given from an external part of the device by using a reference pulse signal 4 generated from a clock generating part 1 to generate a command A data storage part 6 consists of a serial register and an address generating circuit. The serial register is shifted by a transfer clock 8 in the unit of one bit, stores the data from an input/output serial register and outputs the data to the external side of the device. The data stored in the data storage section 6 is transferred to a data processing part 9 via an internal bus 10 and a write data is transferred from the data processing section 9 to the data storage part 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device, and more particularly to a processing device that transmits and receives data to and from a microcomputer.

[Conventional technology]

Conventionally, in this type of device, instructions for determining the operating state of the device and data processed within the device are sent and received in such a way that each bit is exchanged in parallel.

[Problem that the invention seeks to solve]

In addition to the above-mentioned conventional device, since the format of data transmission and reception with the microcomputer is in parallel for each bit, the total number of ryAK issues is required for the interface, and the device controlled by the microcomputer Input/output operations were restricted at the time when Isome Hi was introduced.Also, if a device controlled by a microcomputer is placed in a location far from the microcomputer, all operations during these periods are restricted. This requires a large number of interconnecting signal lines, and since these signal lines are provided externally, they are easily affected by noise, etc.Also, all signals are required for decoding instructions, and the number of outputs of the microcomputer increases. The disadvantage was that even more .

[Means for solving problems]

The processing device of the present invention includes a clock signal generation section, an instruction decoding section, a data storage section, and a data processing section. The data storage section consists of a serial register, and the microphone 40
It has means for transmitting and receiving to and from the computer in a serial format, and for generating commands by counting clock signals.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. Reference numeral 1 denotes a clock signal generation section, which is composed of an oscillation circuit, a frequency divider circuit, and a timing generation circuit. The reference clock signal generated by the oscillation circuit is frequency-divided by the frequency divider circuit and supplied to the inside of the processing device. The instruction decoder 2 samples the instruction signal 3 applied to the external device using the reference pulse signal 4 generated from the clock 1g generator 1, and generates an instruction.

The instruction decoder 2 includes an edge detection circuit and a counter circuit. Decoding of the command begins by detecting the rising edge of the command signal 3 by the etch detection circuit and resetting the counter.While the command signal 3 remains at the NOI level, the counter circuit counts based on the reference pulse signal. It is done. The command is determined by the fall of the command signal 3, and the control signal 5 is supplied to the inside of the command decoder 2 device. The control signal 5 completely defines the operating state of the entire device, and also defines the data reading and writing operations for the data storage section 6.

7 is input/output serial data. 8 is a transfer clock. The data storage section 6 is composed of a serial register and an address generation circuit. The serial register is shifted in 1'et units by the transfer clock 8, stores data from the input/output serial data 7, and outputs the data to the outside of the device. I/O Kaserial Cheetah 0
Switching between input and output is performed by control signal 5. The data processing section 9 is composed of an address generation circuit, a data read/write circuit, and an input/output buffer.

The data stored in the data storage section 61C is transferred to the data processing section 9 via the internal bus 10, and data written to the data storage section 61C is transferred from the data processing section 9. The data processing section 9 performs data input/output operations in a time-division manner in accordance with the timing generated by the timing generation 1g signal 11 generated from the clock signal generation section. The data corresponding to the address generated by the timing generation signal 11Vc is input to the input port 12. Out capo) 13 f
Through f&, input/output operations are performed between the data processing section 9 and the outside of the device. - Input boat 12. Data input/output via the output port 13 is processed within the device and interfaced with the microcomputer via all input/output serial data 7.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to send and receive data to and from a microcomputer. Since it is performed in the J full format, the number of interfaces is minimized compared to the parallel format, and the generation of instructions is done by counting clock signals and decoding them inside the device, which has the effect of making microcomputer processing easier. be. Remote processing becomes possible by distributing the present invention as a peripheral device of a microcomputer, for example, as a processing device dedicated to keys and display.

Particularly in cases where there is a physical distance between the microcomputer and the microcomputer, the number of wires is small due to the serial interface, which has the effect of increasing noise resistance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. 1... Clock signal generation section, 2... Instruction decoding section, 3... Command signal, 4... Reference pulse signal, 5......・Control signal, 6...
- Data storage unit, 7... Input/output serial data, 8... Transfer clock, 9... Data processing unit, 16... Internal bus, 11.・・・・・・
・Timing generation signal, 12...Input port,
13...Output boat.

Claims (1)

[Claims] an input section that serially inputs a command signal bit by bit; an oscillation circuit that generates a reference clock signal; and a circuit that determines the bit length of the command signal input at the input section by counting the clock signal. an instruction decoding unit that regenerates an instruction signal; a shift register that inputs or outputs data in synchronization with a transfer clock; and a data processing unit that performs input/output operations of the data in a time-sharing manner using a timing signal based on the clock signal. A serial data processing device comprising: