KR100263670B1 - A dma controller - Google Patents

Abstract

PURPOSE: A direct memory access controller is provided to improve the data transmission speed between systems, by using a clock suitable for characteristics of source and destination systems. CONSTITUTION: A clock divider(340) generates a high frequency clock(hclk) and a low frequency clock(lclk) in response to input clocks(clock1,clock2). A master control part(300) sends period signals(s_period, d_period) to control parts(310,320) in response to the clock(hclk), and outputs a control signal(con) synchronized with the clock(hclk). The control parts(310,320) are responsive to the period signals(s_period, d_period) from the part(300), and thereby generates an address necessary for transmission and a signal for notifying whether the source and destination systems are I/O devices or memories. A synchronization control part(330) outputs a system control signal, which is synchronized with the clock(hclk) or the clock(lclk) so that the system control signal can be suitable for the characteristics of the source and destination systems.

Description

Direct memory access controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computing system, and in particular, a direct storage approach for directly transferring data between an input / output device (Input / Output, hereinafter referred to as I / O) and a main memory (main memory) without being processed by a central processing unit. A controller for controlling direct memory access (hereinafter referred to as DMA).

FIG. 1 is a block diagram illustrating a conventional DMA controller, and includes a master controller 100, a source controller 110, and a destination controller 120 controlled by a unique clock.

The master control unit 100 transmits each section (s_period, d_period) signal to each control unit 110 and 120 to distinguish transmission between the source system and the destination system, and also controls the system control signals (address and data timing, command). Signal) and send it to each system (I / O or memory device). The source and destination controllers 110 and 120 may respond to a period signal input from the master controller 100 and may indicate an address required for transmission and a signal indicating whether the source and destination system is an I / O or a memory ( m / io) and output to the master controller 100.

2 is a control signal timing diagram for a conventional DMA controller. In the source section, the source system reads data of the corresponding address in response to the system control signal (address, read signal) output from the master controller 100, and in the destination section, the destination system is output from the master controller 100. The data of the address is written in response to the control signal (address, write signal).

The conventional DMA controller, which is controlled by such a unique clock, does not consider the performance difference between the source and the destination system at all, and since the unique clock is adapted to a relatively slow system, the source system and the destination system are fast for the fast system. The performance loss is as much as the difference in performance between the two. That is, in general, a memory system has a much faster transfer performance than an I / O system. In the case of DMA, there is almost no transfer between memory and memory, and most transfers between memory and I / O are considered. There is always a problem of loss of performance.

Disclosure of Invention The present invention has been made to solve the above problems, and an object thereof is to provide a direct storage access controller that improves the transmission speed between systems by using a clock suitable for characteristics of a source and destination system.

1 is a block diagram showing a conventional DMA controller.

2 is a control signal timing diagram for a conventional DMA controller.

3 is a block diagram showing a DMA controller of the present invention;

4 is a block diagram illustrating a clock divider.

5 is a block diagram showing a synchronization control unit.

6 is a control signal timing diagram for the DMA controller of the present invention.

* Description of the main parts of the drawing

300: master control unit 310: source control unit

320: destination control unit 330: synchronization control unit

340: Clock divider

The present invention for achieving the above object is a clock division means for generating a high frequency clock and a low frequency clock; Master control means for receiving the high frequency clock and outputting each section signal for transmission division between a source system and a destination system to a source control means and a destination control means, and outputting a first control signal synchronized with the high frequency clock; The source control means for generating an address required for transmission in response to the source interval signal and a second control signal indicating whether the source system is an input / output system or a memory system and outputting the second control signal to the synchronous control means; The destination control means for generating an address required for transmission in response to the destination duration signal and a third control signal indicating whether the destination system is an input / output system or a memory system and outputting the third control signal to the synchronization control means; And receiving the first control signal and outputting a system control signal synchronized with the low frequency clock or the high frequency clock to the source system or the destination system in response to the low frequency clock and the second and third control signals. And a direct storage location access controller comprising said synchronous control means.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

In order to eliminate the performance degradation caused by the system control signal being controlled by a conventional unique clock, the present invention receives a dual clock from the outside, or a single clock input through a frequency divider circuit for a high frequency clock or a low frequency for each system characteristic Use the clock. In other words, the memory system uses the high frequency clock as the synchronous clock of the system control signal, and the I / O system uses the low frequency clock as the synchronous clock of the system control signal.

3 is a block diagram illustrating a DMA controller according to an embodiment of the present invention, in which a single clock is input and a dual clock is input.

A clock divider 340 that receives the clocks clock1 and clock2 to generate a high frequency clock hclk and a low frequency clock lclk, and receives a high frequency clock hclk to receive transmissions between the source system and the destination system. A master control unit which sends the period s_period and d_period signals to each of the control units 310 and 320 and outputs a control signal con (i.e., an address and data timing and a command signal) synchronized with the high frequency clock hclk ( 300, an address required for transmission in response to the source and destination interval signals s_period and d_period input from the master controller 300 and a signal indicating whether the source and destination system is I / O or memory (m / source and destination controllers 310 and 320 and low frequency clocks (lclk) and m / io signals generated and output to the synchronization controller 330 in accordance with the characteristics of the source system and the destination system. Alternatively, the synchronization control unit 330 outputs a system control signal synchronized with the high frequency clock to each system.

The clock divider 340 divides when a single clock is input from the outside, generates and outputs a high frequency clock hclk and a low frequency clock lclk, and when the dual clock is input, does not undergo a division process. The dual clock is used as the high frequency and low frequency clock, respectively. FIG. 4 is a block diagram illustrating a clock divider 340. The clock divider 340 is driven in response to a buffer 400 and a first clock clock1 that receive a first clock clock1 and output a high frequency clock hclk. In response to the flip-flop 410 and the control signal clk_sel, the inverted value of the output is fed back to the input, and among the low frequency clocks divided by the second clock clock 2 and the flip-flop 410. The multiplexer 420 selects one and outputs the low frequency clock lclk. When a single clock is applied from the outside, in response to the control signal clk_sel, the low frequency clock divided by the flip-flop 410 is selected and output as the low frequency clock lclk, and when the dual clock is applied from the outside, the control signal. In response to clk_sel, the input second clock clock2 is output as the low frequency clock lclk.

The high frequency clock hclk applied from the outside and output through the clock divider 340 is used as a main clock of the system control, and is used as a clock of the master controller 300 and each of the system controllers 310 and 320. . The low frequency clock lclk is input to the synchronization controller 330 and used to generate a control signal of a system having a slow transmission rate.

FIG. 5 is a block diagram illustrating the synchronization controller 330. The synchronization controller 330 is synchronized with the high frequency clock hclk output from the master controller 300 in response to the low frequency clock lclk output from the clock divider 340. The flip-flop 500 outputting the control signal con in synchronization with the low-frequency clock lclk and the low-frequency clock output from the flip-flop 500 in response to the m / io signals output from the controllers 310 and 320. The multiplexer 510 selects one of a control signal synchronized with lclk and a control signal con synchronized with a high frequency clock hclk and outputs the system control signal. If the s_m / io signal or d_m / io indicates that the transmission system is a memory, the control signal con synchronized with the high frequency clock hlkl output from the master controller 300 is sent as a system control signal, and the I / O In this case, a control signal synchronized with the low frequency clock lclk output from the flip-flop 500 is output as a system control signal. At this time, the number of flip-flops 500 is equal to the number of system control signals required for the system interface. The s_m / io signal indicates whether the source system is memory or I / O, and the d_m / io signal indicates whether the destination system is memory or I / O.

6 is a control signal timing diagram for the DMA controller of the present invention, which is divided into a source section and a destination section.

It is assumed that the memory system interface is formed in the source section and the I / O system interface is performed in the destination section. In the source section, the memory system is first valid for one cycle of the hclk address synchronized to the high frequency clock hclk. Immediately, the command signal (read signal) synchronized with the high frequency clock hclk is valid to read data. Therefore, the transmission time is shortened by the A period in the entire entire source period.

It can be seen that the I / O system is the same one cycle in the destination period but at least twice as slow as the address and command (write signal) signals in synchronization with the low frequency clock (lclk).

Therefore, when the source interval is applied to the memory system and the destination interval is applied to the I / O system, each of the memory system and the I / O system can transmit data at the maximum performance.

The dual clock control of the present invention can be applied as a bridge between buses as well as DMA, and is applicable to the whole field of system design.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

According to the present invention as described above, the memory system or the I / O system may transmit data at the maximum performance by using a low frequency or high frequency clock suitable for the performance of the source system and the destination system instead of the unique clock.

In addition, since the source or destination control signals are output in synchronization with the selected clock signal, a transmission time equal to the difference between the low frequency clock and the high frequency clock (1/2) for a time (1/2) of one of the source or destination periods is increased. As a result, the overall transmission time can be reduced by about one quarter, which means that the larger the performance difference between the memory system and the I / O system, the shorter the transmission time.

Claims (10)

Clock dividing means for generating a high frequency clock and a low frequency clock; Master control means for receiving the high frequency clock and outputting each section signal for transmission division between a source system and a destination system to a source control means and a destination control means, and outputting a first control signal synchronized with the high frequency clock; The source control means for generating an address required for transmission in response to the source interval signal and a second control signal indicating whether the source system is an input / output system or a memory system and outputting the second control signal to the synchronous control means; The destination control means for generating an address required for transmission in response to the destination duration signal and a third control signal indicating whether the destination system is an input / output system or a memory system and outputting the third control signal to the synchronization control means; And Receiving the first control signal and outputting a system control signal synchronized with the low frequency clock or the high frequency clock to the source system or the destination system in response to the low frequency clock and the second and third control signals; Synchronous control means Direct storage access controller made including. The method of claim 1, The first control signal is And an address timing, a data timing, and a command signal input to the source system or the destination system. The method of claim 1, The clock division means Buffering means for receiving a first clock and directly outputting the high frequency clock; A divider means for receiving the first clock and dividing the first clock to output a divided clock; And Selection means for selecting one of a second clock and a divided clock output from the division means in response to a fourth control signal and outputting the selected low frequency clock; Direct storage access controller made including. The method of claim 3, wherein The dispensing means And a flip-flop that is fed back to the output with an inverted value of the output fed back to the output. The method of claim 3, wherein The means for selecting In response to the fourth control signal when a single clock is applied from the outside, a clock divided by the dividing means is selected and output to the low frequency clock, and in response to the fourth control signal when a double clock is applied from the outside. And the second clock is output as the low frequency clock. The method of claim 1, The synchronous control means A flip-flop, in response to the low frequency clock, for outputting a first control signal synchronized with the low frequency clock synchronized with the high frequency clock output from the master control means; And In response to the second control signal or the third control signal, one of a first control signal synchronized with the low frequency clock output from the flip-flop and a first control signal synchronized with the high frequency clock is selected as a system control signal. Selection means to output Direct storage access controller made including. The method of claim 6, The second control signal is And a direct storage location controller for indicating whether the source system is the memory system or the input / output system. The method of claim 6, The third control signal is And a direct storage access controller indicating whether the destination system is the memory system or the input / output system. The method of claim 6, The means for selecting The first control signal synchronized with the high frequency clock is output as the system control signal when the transmission system is the memory, and the first control signal synchronized with the low frequency clock is output as the system control signal when the input / output system is an input / output system. Memory access controller. The method of claim 6, The synchronous control means And a number of flip flops equal to the number of system control signals.

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