JP4124579B2 - Bus control system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to bus control of a computer system having a bus that operates at a plurality of different frequencies.
[0002]
[Prior art]
In a system that requires a high-speed operating frequency for the processor, a relatively low-speed bus that connects peripheral devices is prepared separately from the high-speed processor bus that connects the processor and storage device, and the number of devices connected to the processor bus There is a method for realizing an increase in the operating frequency of the processor bus by reducing the frequency. The bus connecting multiple devices is generally a clock-synchronous bus, but the devices connected to the low-speed bus are diversified both in terms of function and maximum operating frequency, and have a single frequency. In order to connect a plurality of devices to the clock-synchronous bus, a method is adopted in which the operation clock of the device is the same as the bus clock or a synchronization circuit is provided on the device side. In general, since a connected device can be operated at each maximum frequency, the method of providing a synchronization circuit is considered to have better overall system performance.
[0003]
FIG. 2 shows a configuration example of a system having a bus hierarchical structure in which a synchronization circuit is provided on the device side. In FIG. 2, 101 is a synchronous primary bus, 102 is a synchronous secondary bus that operates at a frequency different from that of the primary bus 101, 103 is a processor connected to the primary bus 101, and 104 is a primary bus 101. , A master device that outputs a transfer request connected to, a target device that receives a transfer request connected to the primary bus 101, and a device that transfers a transfer request generated on the primary bus 101 to a device on the secondary bus 102. , A bus supply unit 107 for supplying a clock to each device, 108 is connected to the secondary bus 102, a target device A operating with the clock A, 109 is connected to the secondary bus 102, and a clock B The operating target device B, 114 is the clock X on which the primary bus 1 operates, and 201 is the secondary bus 102 operating. Lock Y, 115 is a clock A, 116 of target device A108 operates a clock B to the target device B109 operates. Here, it is assumed that the clock X114, the clock Y201, the clock A115, and the clock B116 are independent and have different frequencies, and the clock X114 has the highest frequency among the four types of clocks. Reference numeral 111 denotes a signal synchronized with the clock Y114 that operates the primary bus 101, a clock Y201 that operates the secondary bus 102, and a signal that synchronizes with the clock Y201 that operates the secondary bus 102. A synchronizing circuit for synchronizing with the clock X114, a synchronizing circuit for synchronizing the signal synchronized with the clock Y201 with the clock A115, a synchronizing circuit for synchronizing the signal synchronized with the clock A115 with the clock Y201, and 203 with the clock Y201. This is a synchronization circuit that synchronizes the synchronized signal with the clock B116 and the signal synchronized with the clock B116 with the clock Y201. Devices such as the target device A 108 and the target device B 109 that operate with a clock different from the operation clock of the bus to be connected include synchronization circuits 202 and 203, and signals that operate with the operation clock of each device are bus clocks. The output synchronized with Y201 and the signal synchronized with the input bus clock Y201 must be synchronized with the operation clock of each device.
[0004]
Next, the flow of data transfer from the processor 103 on the primary bus 101 to the target device A 108 on the secondary bus 102 will be described with reference to FIG. The transfer request generated by the processor 103 is issued on the primary bus 101 with the transfer destination specified as the target device A 108. The bus bridge 106 that has received the transfer synchronizes the signal input from the primary bus 101 with the synchronization circuit 111 in order to transmit the transfer to the secondary bus 102. By passing through the synchronization circuit 111, the signal is synchronized with the operation clock Y 201 of the secondary bus 102 and issued on the secondary bus 102. In the secondary bus 102, the synchronization circuit 11 is configured so that the target device A 108 as a transfer destination receives the transfer and operates the received signal with the clock A 115. 1 Synchronize through
[0005]
In the system as shown in FIG. 2, since each target device must have a synchronization circuit, the logic scale and power consumption increase, and it occurs when passing through the synchronization circuits of both the target device and the bus bridge. Latency causes a decrease in transfer efficiency. As a means for solving these problems, a method described in Japanese Patent Laid-Open No. 6-83770 in which devices having different operating frequencies are connected to the same bus can be considered. In the method described in Japanese Patent Laid-Open No. 6-83770, when a plurality of devices having different operating frequencies share an address bus and a data bus, a command generation circuit that generates a command synchronized with the operating frequency of each device is provided as a device. Transfer is performed in a procedure in which a command is sent to each device, a data transmission / reception end signal is received from the device, and the transfer is terminated. If this method is used, when a bus with a simple protocol that transmits and receives only one type of data with a single address output is adopted as the secondary bus, the synchronization circuit on the device side can be deleted. is there.
[0006]
[Problems to be solved by the invention]
In the conventional method, when a bus having a complicated protocol is adopted as a secondary bus, it is necessary to provide a control line synchronization circuit corresponding to the type of clock of the device connected to the secondary bus. Therefore, the number of bus bridge interface signals also increases because one circuit line must be provided for each device. Furthermore, when a bus with a protocol that switches addresses and data at the determined timing using the same signal line is adopted as the secondary bus, the address / data line is also output in synchronization with the clock of each device. Therefore, the bus bridge must have all the signals of the bus as interface signals corresponding to the types of clock frequencies.
[0007]
The object of the present invention is to connect devices operating at different frequencies without increasing the number of interface circuits and the synchronization circuit on the bus bridge side even if a bus having a complicated protocol is selected as the secondary bus. And reducing the logical scale and power consumption to improve the transfer efficiency.
[0008]
[Means for Solving the Problems]
In the present invention, in order to solve the above-described object, a clock selection unit for selecting an operation clock of the secondary bus from operation clocks of several types of devices connected to the secondary bus by a clock selection signal from the bus bridge is provided. And a function of sending a signal synchronized with the clock output from the clock selection unit from the bus bridge. Also, a secondary bus corresponding to multiple masters is provided with a bus arbiter that selects the clock of the secondary bus simultaneously with the arbitration of the transfer request, and enables connection of the target device to the secondary bus without using a synchronization circuit. . Here, the master device other than the bus bridge corresponds to both a master device having no original operation clock and a master device having an original operation clock. By eliminating the synchronization circuit of the target device, the logical scale can be reduced and the transfer efficiency can be improved.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
A first embodiment of the present invention will be described with reference to FIG. In FIG. 1, 110 is an address decoder that decodes an address input from the primary bus 101, 112 is a clock selector that selects a clock A 115 and a clock B 116, and 113 is an operation of a target device specified as a transfer destination by the address decoder 110. A clock selection signal 117 indicating a clock is a synchronizing circuit clock selected by the clock selector 112. In the first embodiment, a bus control system is shown in which two or more target devices operating with clocks having different frequencies are connected to the same bus, and the synchronization is not provided in the target device.
[0010]
As in the conventional example of FIG. 2, two clocks are input from the clock supply unit 107 to the bus bridge 106. In this embodiment, the clock selector 112 selects the operation clock of the secondary bus 102. The synchronized circuit clock 117 is used. Also, the target device connected to the secondary bus 102 is input with only one system operation clock and one system, and the synchronization circuit is deleted. The secondary bus 102 does not have a specified operation clock. When the data transfer destination is the target device A108, a synchronized signal is sent to the clock A115, and when the data transfer destination is the target device B109, a synchronized signal is sent to the clock B116. The output from 106 enables data transfer on the secondary bus 102 without the synchronization circuit of the target device.
[0011]
Since the bus bridge 106 needs to dynamically change the clock for synchronizing the signal output on the secondary bus 102 for each generated transfer, the address decoder 110 decodes the address input from the primary bus 101. Then, the target of the transfer destination is specified, and the result is sent to the clock selector 112 to select which clock the signal is synchronized with.
[0012]
The flow of data transfer from the processor 103 on the primary bus 101 to the target device A 108 on the secondary bus 102 will be described with reference to FIG. The transfer request generated by the processor 103 is issued on the primary bus 101 with the transfer destination specified as the target device A 108. The bus bridge 106 that has received the transfer decodes the address of the received transfer and determines whether the transfer is to the target device A 108 or the target device B 109 on the secondary bus. If it is determined that the transfer from the processor 103 is a transfer to the target device A 108, the determination result is output to the clock selector 112 as the clock selection signal 113 in order to synchronize the signal output from the bus bridge 106 with the clock A 115. To do. The clock selector 112 selects the clock A 115 as the synchronization circuit clock 117 according to the value of the clock selection signal 113. The clock selection signal 113 is kept at a constant value until the transfer on the secondary bus 102 is completed. In the bus bridge 106, the determination result of the address decoder 110 is output to the clock selector 112, while the signal input from the primary bus 101 is synchronized by the synchronization circuit 111 in order to transmit the transfer to the secondary bus 102. With the above flow, a signal synchronized with the clock A is output to the secondary bus 102, and the target device A 108 designated as the transfer destination receives the transfer. The same transfer procedure is performed when the transfer destination is the target device B109.
[0013]
The relationship between the clock switching timing in the clock selector 112 and the synchronization of the signal input from the primary bus 101 will be described with reference to FIGS. FIG. 3 is a block diagram of the periphery of the synchronization circuit 111 that synchronizes signals input from the primary bus 101 of the bus bridge 106, and FIG. 4 is a timing chart thereof. In FIG. 3, 301 is a flip-flop that operates at the rising edge of the clock X114, 302 and 303 are flip-flops that operate at the rising edge of the clock A115, and 304 is the primary bus 101 synchronized with the clock X114 to the bus bridge 106. Input signals 1 (X) and 305 are signals 2 (X) output from the flip-flop 301, 306 is a signal 3 (A) output from the flip-flop 302, and 307 is input from the flip-flop 303 to the secondary bus 102. This is the output signal 4 (A). In FIG. 4, X1 to X9 are times of the clock X114, and A1 to A6 are times of the clock A115. Here, it is assumed that the clock X114, the clock A115, and the clock B116 are clocks having different frequencies and phases.
[0014]
In the time chart of FIG. 4, the signal 2 (X) 305 changed at X4 is taken into the flip-flop 302 at the rising edge of the clock A115 of A3. In A3, since the occurrence time of the state change of the signal 2 (X) 305 and the rising edge occurrence time of the clock A115 are very close to each other, the flip-flop 302 cannot take in the state change of the signal 2 (X) 305 and outputs it. The signal 3 (A) 306 thus obtained is in an indeterminate state (metastable state) at A4. In order to eliminate this metastable state, time is taken for one clock, and the signal 3 (A) 306 is input to the flip-flop 304 in the other stage at the rising edge of the clock A115 of A5 and synchronized with the clock A116. Signal 4 (A) 307 is generated.
[0015]
In the first embodiment, the clock used in the synchronization circuit 111 of the bus bridge 106 is the synchronization circuit clock 117 selected from the clock A 115 and the clock B 116. The switching timing of the synchronizing circuit clock 117 is the timing of the state change of the clock selection signal 113 obtained as a result of decoding the address synchronized with the clock X114. The clock X114, the clock A115, and the clock B11 6 Since these are clocks having different frequencies and phases, the time between rising edges of the synchronization circuit clock 117 before and after the switching timing is not guaranteed.
[0016]
If the address is input to the bus bridge at the same timing X3 as the signal 1 (X) 304, the clock selection signal 113 generated through the address decoder 110 is delayed in the state change from the signal 1 (X) 304. If synchronization is started with respect to the signal 1 (X) 304, the state-changed value is the flip-flop 302 at X 3 at which the rising edge of the synchronization circuit clock 117 selected by the clock selection signal 113 is generated. Is taken in. Here, if it is assumed that the output signal of the flip-flop 302 is in a metastable state, the flip-flop 302 must be released from the metastable state during Tck for the time until A3 which is the next rising edge of the clock 117 for the synchronization circuit. In step 303, the metastable state cannot be removed. As described above, before and after the switching timing of the synchronization circuit clock 117, the time between the rising edges of the clock is not guaranteed. Therefore, Tck becomes very short, and the output signal of the flip-flop 302 leaves the metastable state. May not be possible.
[0017]
Therefore, in order to perform normal synchronization, it is necessary to input a signal to be synchronized to the synchronization circuit at a timing later than the clock selection signal 113. In the example of FIGS. 3 and 4, the input signal 1 (X) 304 Is input to the flip-flop 301 operating with the clock X114, and the state change is delayed by one clock before being input to the synchronization circuit 111.
[0018]
In the conventional method in which the clock input to the synchronization circuit 111 is not selected, the flip-flop 301 is not necessary, and thus becomes large considering the latency of only the bus bridge 106. However, since the clock X114 is considered to have a higher operating frequency than the clock A115 and the clock B116 in the whole system, the delay time shortened by deleting the synchronization circuit of the target device A108 and the target device B109. However, it can be said that it is sufficiently longer than the passing time of the flip-flop 301 operated by the clock X114, and there is no influence on the effect of adopting this method.
[0019]
Next, a second embodiment in which a master device other than the bus bridge 106 is connected to the secondary bus 102 will be described with reference to FIG. The master device newly connected to the secondary bus 102 in the second embodiment is assumed to be a device that operates with a single clock and can dynamically change the clock. An example of such a device is a DMA controller that issues a transfer request by setting a register. In FIG. 5, 501 is a master device that issues a transfer request connected to the secondary bus 102, 502 is a bus arbiter that arbitrates a plurality of bus users, and 503 is a bus bridge transfer request that is output from the bus bridge 106 to the bus arbiter 502. 504, a bus bridge transfer permission signal output from the bus arbiter 502 to the bus bridge 106, 505, a master transfer request output from the master device 501 to the bus arbiter 502, and 506, a master transfer permission output from the bus arbiter 502 to the master device 501. A signal 507 is a clock selection signal. Here, it is assumed that the transfer request signals 503 and 504 are simultaneously output to the bus arbiter 502 at the same time.
[0020]
A bus that can connect a plurality of masters requires a mechanism for arbitrating the bus user. In the second embodiment, the bus arbiter 502 not only arbitrates the bus user but also outputs a clock selection signal. In FIG. 5, the bus bridge 106 and the master device 501, which are two devices that issue a transfer request connected to the secondary bus 102, specify not only the transfer request but also which clock to operate on the bus arbiter 502. The clock selection signal to be output is output.
[0021]
The bus arbiter 502 selects a device that can start transfer on the secondary bus 102 and transmits transfer permission signals 504 and 506 to the device. At the same time, the bus arbiter 502 outputs a clock selection signal issued by the selected device to the clock selector 112. And select the clock with the frequency required by the device that has acquired the bus. In the bus arbiter 502, since the clock is also switched at the timing of switching the bus usage right, it is necessary to prevent the occurrence of bus collision and metastable by some method before and after the switching. Therefore, in the second embodiment, a system that introduces a mechanism for operating the clock switching timing by the bus arbiter 502 and a system that operates the clock by the bus bridge 106 are adopted.
[0022]
First, a method of operating the clock switching timing in the bus arbiter 502 will be described with reference to a detailed diagram of the bus arbiter 502 in FIG. 6 and a bus arbitration timing chart in FIG. In FIG. 6, reference numeral 601 denotes a bus bridge clock selection signal output for the bus bridge 106 to select the synchronization circuit clock 117, and reference numeral 602 denotes a master device that the master device 501 outputs to select the synchronization circuit clock 117. A clock selection signal, 603 is a clock selection signal selector for selecting a clock selection signal of a device to which a bus right is given, and 604 is a bus arbiter for a bus bridge transfer request 503 which is a signal output in synchronization with the clock X114 of the primary bus 101. A synchronization circuit that synchronizes to the synchronization circuit clock 117, which is an operation clock of 502, 605 is a bus bridge transfer request after synchronization synchronized by the synchronization circuit 604, and 606 is a bus bridge transfer request 605 after synchronization. Receives master transfer request 505 and determines arbitrary priority Priority is a priority determination unit that determines which device is given the bus right by law, 607 is a bus bridge selection signal that is a result determined by the priority determination unit 606, 608 is a control signal for the secondary bus 102, and 609 is A bus idle detection unit that detects that the secondary bus 102 is not in use by using the control signal 606, a bus right switching timing signal 610 as a result of the bus idle detection unit 607, and a bus bridge selection signal 607 as a bus right switching timing Fetched when the signal 610 is asserted, 611 is a flip-flop that generates a bus bridge transfer permission signal, 612 is an inverter, 613 is a signal inverted by the inverter 612, 614 is a master transfer permission signal 506 requested by the master device 501 It is a synchronization circuit that synchronizes at a clock frequency. In FIG. 7, A1 to A5 are clock A115 times, B1 to B6 are clock B116 times, 701 is an internal signal of the synchronization circuit 610 of FIG. This is the output signal of the first-stage flip-flop.
[0023]
A procedure for bus arbitration by the bus arbiter 502 will be described. The transfer request signal 503 from the bus bridge 106 is already synchronized with the synchronization circuit clock 117 in the synchronization circuit 604, and is already synchronized with the synchronization circuit clock 117. 117 Synchronized to Ru The transfer request signal 505 from the star device 501 is directly input to the priority determination unit 606. The priority determination unit 606 determines which transfer request has the higher priority by an arbitrary priority determination algorithm, and outputs a bus bridge selection signal 607 that is asserted when the bus bridge 106 is selected.
[0024]
At the same time, the bus idle detection unit 607 monitors the control signal 608 of the secondary bus 102, monitors whether the secondary bus 102 is in use, and asserts the bus right switching timing signal 610 if it is not in use. The bus bridge selection signal 607 is taken into the flip-flop 611 at the rising edge of the clock when the bus right switching timing signal 610 is asserted, and the bus bridge transfer permission signal 504 is generated. The master transfer permission signal 506 is an inversion of the bus bridge transfer permission signal 504.
[0025]
As a premise of the second embodiment, it is assumed that the master device 501 is a device that generates a transfer request by setting a register. Since such a device issues a transfer request after it is ready to transfer normal data, when the master device 501 receives the transfer permission signal 506 for the transfer request, the master device 501 passes the next synchronization without passing through the synchronization circuit. The bus output operation can be started at the rising edge of the circuit clock 117. Therefore, the bus arbiter 502 must output the master transfer permission signal 506 to the master device 501 without the synchronization circuit in synchronization with the clock requested by the master device 501. On the other hand, since the bus bridge 106 issues a transfer request 503 and acquires the bus right, the signal passes through the synchronization circuit 111 and is output to the secondary bus 102. Therefore, the bus bridge transfer permission signal 504 is synchronized with the clock. However, if the bus bridge transfer permission signal 504 is synchronized by the bus arbiter 502, the synchronization is doubled. Therefore, as shown in FIG. 6, the bus bridge transfer permission signal 504 uses the output of the flip-flop 611 as it is, and the master transfer permission signal 506 inverts the output of the flip-flop 611 by the inverter 612 and then synchronizes the signal 612. The circuit 614 synchronizes and outputs to the synchronization circuit clock 117 after clock switching, thereby avoiding duplication of synchronization.
[0026]
Details of the timing for switching the bus right from the bus bridge 106 to the master device 501 are shown in the timing chart of FIG. At A1, the master device 501 issues a transfer request 503 while the bus bridge 106 is transferring on the secondary bus 102 in synchronization with the clock A115. Here, it is assumed that the master device 501 requests transfer to the target device B 109 and desires to operate with the clock B 116. The transfer of the bus bridge 106 is completed at A1, and the bus bridge 106 lowers the transfer request 503 at the rising edge of the clock A115 of A2. At the same time, since the secondary bus 102 becomes unused, the bus right switching timing signal 610 is asserted. At the rise of the clock A115 of A3, the bus bridge transfer permission signal 504 is negated, and the master device clock selection signal 602 output from the master device 501 is selected as the clock selection signal 507. After the clock selection signal 507 is switched, the synchronization circuit clock 117 is switched from the clock A115 to the clock B116. Since the bus bridge transfer permission signal 504 is negated at the rising edge of the clock A115 of A3 which is the clock switching timing, if the inverted signal is used as it is as the transfer permission signal 506 to the master device 501, the master device 501 is used. Becomes an asynchronous signal with respect to the clock B116, which is the operation clock required by. Therefore, the value of the inverted signal 613 of the bus bridge transfer permission signal 504 is taken into the synchronized first stage flip-flop at the rise of the clock B116 of B4, and the synchronized first stage flip-flop at the rise of the clock B116 of B5. The value of the output signal 701 is taken into the synchronized second-stage flip-flop, so that the master transfer permission signal 506 synchronized with the clock B116 is generated.
[0027]
Next, a method of operating the clock with the bus bridge 106 will be described. Since the master device 501 used in the second embodiment issues a transfer request 505 when a register is set by the processor 103, to which target the master device 501 issues the transfer request 505, a transfer request issuance is issued. The processor 103 should have grasped before. Therefore, in this method, a mechanism that can be set in the bus bridge 106 so as to select and transfer a clock that is scheduled to be selected when the transfer request 505 is issued as a clock for accessing the master device 501 for register access. Provide. Some examples of such a mechanism are conceivable. One is to provide a dedicated register for setting the operation clock of the transfer issued inside the bus bridge 106 and set it before issuing the transfer for setting the register of the master device 501, and set the value of the dedicated register to the clock selection signal. As the output method. The other is that when setting the address when the transfer request 503 of the master device 501 is issued in the register in the master device 501, a mechanism for decoding the set value of the address is provided in the bus bridge 106, and the clock selection signal is sent. It is a method of determination. If the clock is selected in this way when the master device 501 accesses the register, the clock switching does not occur when the master device 501 issues the transfer request 505. Therefore, when the bus arbiter 502 outputs the master transfer permission signal 506, There is no need to provide a synchronization circuit, and the time required for bus arbitration can be shortened.
[0028]
Further, as a third embodiment, a case where a device connected to the secondary bus 102 has its own operation clock because it is connected to an external I / O or another bus will be described with reference to FIG. To do. In FIG. 8, 801 is a master device having an interface with the outside in addition to the interface with the secondary bus 102, 802 is an external I / O connected to the master device 801, and 803 is an address decoder from the external I / O 802. , 804 is a synchronization circuit that synchronizes the input signal from the external I / O 802 with the clock 117 for the synchronization circuit and the input signal from the secondary bus 102 to the operation clock of the external I / O 802, and 805 is the master device 801. Clocks C and 806 for operating the external I / O 802 are bus arbiters that receive transfer requests from the bus bridge 106 and the master device 801 and arbitrate the bus.
[0029]
In the third embodiment, since the master device 801 has a clock C805 that is a unique operation clock, it is necessary to provide a function similar to that of the bus bridge 106 in the first embodiment. That is, the address input from the external I / O 802 is decoded by the address decoder 803, output to the bus arbiter 806 together with the master transfer request 505, and when the master transfer permission signal 506 is received, the synchronization circuit 804 receives the clock C 805. Is synchronized with the clock 117 for the synchronization circuit.
[0030]
FIG. 9 shows an internal configuration of the bus arbiter 806 according to the third embodiment. In FIG. 9, reference numeral 901 denotes synchronization for synchronizing a master transfer request 505, which is a signal output in synchronization with the clock C 805, which is the operation clock of the master device 801, with the synchronization circuit clock 117, which is the operation clock of the bus arbiter 502. Reference numeral 902 denotes a master transfer request after synchronization synchronized by the synchronization circuit 901. Since the synchronization circuit 804 exists in the master device 801, the master transfer permission signal 506 is output only by inverting the bus bridge transfer permission signal 504 generated by the flip-flop 611. Even if the master device 801 operates with its own clock, the two types of target devices do not require a synchronization circuit.
[0031]
【The invention's effect】
According to the present invention, in a system having a hierarchical bus structure, a bus bridge that connects a primary bus (high-speed processor bus) and a secondary bus (a relatively low-speed bus that connects peripheral devices and the like) is a secondary data link. By providing a mechanism that allows you to select the clock that synchronizes the output signal depending on the transfer destination on the bus, you can eliminate the synchronization circuit of the target device that is the transfer destination, reduce the logic scale and power consumption, and transfer efficiency Will also improve. In addition to arbitration of the bus on the secondary bus, a bus arbiter that selects a clock for synchronizing data output from each master is provided, so that the target device can be connected to the secondary bus without having a synchronization circuit. Allows multiple master connections. Further, when a master device other than the bus bridge connected on the secondary bus does not have a unique operation clock, the synchronization circuit in the master device can also be deleted.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a first embodiment of the present invention.
FIG. 2 is a configuration diagram of a conventional embodiment.
FIG. 3 is a configuration diagram of a synchronization circuit inside a bus bridge.
4 is a timing chart showing timings of signal lines in FIG. 3;
FIG. 5 is a configuration diagram of a second embodiment of the present invention.
FIG. 6 is a configuration diagram of a bus arbiter in the second embodiment.
7 is a timing chart of bus arbitration in the bus arbiter of FIG. 6. FIG.
FIG. 8 is a configuration diagram of a third embodiment of the present invention.
FIG. 9 is a configuration diagram of a bus arbiter in the third embodiment.
[Explanation of symbols]
101 ... Synchronous primary bus, 102 ... Synchronous secondary bus operating at a frequency different from that of the primary bus, 103 ... Processor connected to the primary bus, 104 ... Transfer request connected to the primary bus , 105... Target device that receives a transfer request connected to the primary bus, 106... Bus bridge that transmits the transfer request generated on the primary bus to the device on the secondary bus 102, 107. Clock supply unit for supplying a clock to the target device A 108 connected to the secondary bus and operating on the clock A 109 109 connected to the secondary bus target device B operating on the clock B 110 110 primary bus An address decoder for decoding an address inputted from 112, a clock selector for selecting clock A and clock B, 13: Clock selection signal indicating whether clock A or clock B is selected, 117: Clock for synchronization circuit selected by clock selector, 114: Clock X on which primary bus operates, 115: Target device A Operating clock A, 116... Clock B operating target device B, 111. Synchronizing circuit inside bus bridge, 201... Clock Y operating secondary bus, 202... Synchronizing circuit inside target A, 203. B internal synchronization circuit 301... Flip-flop operating at the rising edge of clock X 302, 303... Flip-flop operating at the rising edge of clock A 304 synchronizing with clock X input to the bus bridge Signal 1 (X), 305... Output from flip-flop 301 Signals 2 (X), 306... Signal 3 (A) output from flip-flop 302, 307... Signal 4 (A) output from flip-flop 303 to the secondary bus, 501. A master device that issues a transfer request 502, a bus arbiter that arbitrates a plurality of bus users, 503 a bus bridge transfer request that is output from the bus bridge to the bus arbiter 502, 504 a bus that is output from the bus arbiter 502 to the bus bridge Bridge transfer permission signal, 505... Master transfer request output from master device 501 to bus arbiter 502, 506... Master transfer permission signal output from bus arbiter 502 to master device 501, 507... Clock selection signal, 601. Output to select the clock for the control circuit A bridge clock selection signal, 602... A master device clock selection signal output for the master device 501 to select a clock for a synchronization circuit, 603... A clock selection signal selector for selecting a clock selection signal of a device to which a bus right is given, 604... Synchronizing circuit for synchronizing a bus bridge transfer request, which is a signal output in synchronization with the clock X, with the synchronizing circuit clock, 605... Synchronized bus bridge transfer request synchronized with the synchronizing circuit 604 606: a priority determination unit that receives a bus bridge transfer request and a master transfer request after synchronization and determines which device is given the bus right by an arbitrary priority determination method; 607: a determination by a priority determination unit Bus bridge selection signal, 608... Secondary bus control signal, 609. A bus idle detection unit that detects that the secondary bus is not in use, 610... Bus right switching timing signal that is a result of the bus idle detection unit, 611... Flip-flop that generates a bus bridge transfer permission signal, 612. 613: Signal after being inverted by the inverter, 614: Synchronization circuit for synchronizing the master transfer permission signal at the clock frequency required by the master device 501, 701: Internal signal of the synchronization circuit 614, two stages for synchronization Of the prepared flip-flops, the output signal of the first-stage flip-flop, 801... Master device having an interface with the outside in addition to the interface with the secondary bus, 802... External I connected to the master device 801 / O, 803 ... Address decoder from external I / O, 804 ... Master Synchronizing circuit in the device 801, 805... Clock C for operating the master device 801, 806... Bus arbiter that receives a transfer request from the bus bridge and the master device 801 and arbitrates the bus, 901. A synchronization circuit that synchronizes a master transfer request 505 that is a signal to be synchronized with the clock 117 for the synchronization circuit, 902... Master transfer request after synchronization synchronized by the synchronization circuit 901, X1 to X9. A1 to A6: time of clock A115, B1 to B6: time of clock B116.

Claims (4)

  At least two types of clock synchronous buses, which are a primary bus and a secondary bus, a bus bridge that connects the two types of buses, and at least one clock synchronous type that outputs a transfer request connected to the primary bus A master device 1; at least two types of clock synchronous target devices that operate on clocks having different frequencies or periods connected to the secondary bus and receive transfer requests; the master device 1, the target device, and the bus In a system including a clock supply unit that supplies a clock to a bridge, an address decoder that detects a transfer destination of a transfer request from the master device in the bus bridge, and the target device of the transfer destination detected by the address decoder Means for outputting a clock selection signal indicating the operation clock of the primary bus, and a clock for the primary bus. And a synchronizing circuit that synchronizes a signal that operates on the clock of the secondary bus with a clock of the secondary bus, and a signal that operates on the clock of the secondary bus with the clock of the primary bus. By providing a clock selection unit that selects the operation clock of the target device of the transfer destination detected by the address decoder from the operation clock of the target device and inputs it to the synchronization circuit as the clock of the secondary bus, A bus control system, wherein a signal output to the secondary bus is synchronized with a different clock depending on the target device to which data is transferred.   2. The bus control system according to claim 1, wherein the bus bridge inputs a signal input from the primary bus to the bus bridge to the synchronization circuit at a timing later than a timing of a state change of the clock selection signal. And synchronizing with the clock of the secondary bus. 2. The bus control system according to claim 1, comprising at least one type of master device 2 connected to the secondary bus, wherein the bus bridge and a transfer request output from the master device 2 are granted permission to use the bus with the bus bridge. At the same time that the master device 2 is alternately supplied, the operation clock of the target device of the transfer destination desired by the bus bridge or the master device 2 to which the bus use permission is given is selected as the operation clock of the secondary bus. a function of outputting a clock selection signal to said clock selecting portion so that, a signal synchronized with a different clock, characterized in that it comprises a Luba Suabita to arbitrate transfer requested not to collide on the secondary bus Bus control system. Is connected to the secondary bus, comprising at least one master device 2 to operate only in the operation clock of the second bus, the bus control system of claim 1, said bus bridge and said master device 2 outputs As for the transfer request, the bus bridge and the master device 2 are alternately given a bus use permission, and at the same time, the operation of the target device of the transfer destination desired by the bus bridge or the master device 2 to which the bus use is granted. A function of outputting a clock selection signal to the clock selection unit so that a clock is selected as an operation clock of the secondary bus is provided, and a transfer request is made so that signals synchronized with different clocks do not collide on the secondary bus. a bus arbiter for arbitrating the transfer permission signal to the master device 2 which is output from the bus arbiter Bus control system with the features and to Luba Suabita that the master device 2 is output in synchronization with the operation clock of the secondary buses desired.

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