JPH0215357A - Data processor - Google Patents

Abstract

PURPOSE:To easily synchronize bus cycle operation by providing the title data processor with a switch means for selectively adopting a clock signal from an oscillation circuit or a clock signal supplied from the external as an operation clock signal. CONSTITUTION:Clock signals CLK1 to CLK3 generated from an internal clock generator 14 are supplied to an interface 11 and an I/O port 12 included in microprocessors 1 to 3 independently of the clock selecting operation of a clock selecting switch 16. On the other hand, a clock signal selected by the switch 16 is supplied to a CPU 10 as an operation clock signal. At the time of accessing a system bus, the switch 16 supplies a system clock signal SCLK supplied from the external to the CPU 10 as an operation clock. Thereby, the bus cycle of the system bus based upon the processors 1 to 3 can be simply synchronized by the signal SCLK.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to data processing devices such as microprocessors and microcomputers, as well as switching control technology for operating clock signals therein. It relates to technology that is effective when applied to microcomputers.

[Prior art]

In a multiprocessor system in which multiple processors share a system bus, shared resources such as memory and input/output circuits are coupled to the system bus. When such a system allows these processors to perform independent processing, a processor that attempts to access a shared resource acquires bus ownership and activates a bus cycle on the system bus. In order to simplify the system configuration, it is desirable to synchronize the bus cycle of the system bus with an operating clock signal common to each processor, that is, a system clock signal. If synchronized operation with the system clock signal is not possible, a circuit for inserting a way 1-state depending on the operating clock signal frequency of the processor is required.

By the way, some processors include a timer, memory, serial input/output circuit, etc. in addition to a central processing unit. Focusing on the serial input/output circuit in such a processor, the maximum baud rate of this serial input/output circuit is determined by the operating clock signal frequency of the processor.

The operating clock signal in conventional processors has been limited to the use of either an oscillation output from a built-in oscillation circuit or a clock signal supplied from an external source. For example, rI (D64180 User's Manual J P104 published by Hitachi, Ltd. in March 1984)
~As described on page 106, the EXTAL terminal and XT
When a vibrator is coupled to the AL terminal, an operating clock signal having a frequency specified by the frequency of the vibrator is obtained.

Further, when the XTAL terminal is oven-baked and an external clock signal is supplied to the EXTAL terminal, an operating clock signal having a frequency defined by the clock frequency can be obtained.

For this reason, for example, when the maximum baud rate of a serial input/output circuit built into a processor is determined by system operation, it is necessary to obtain an operating clock signal that satisfies the frequency conditions using the built-in oscillation circuit or an external clock. Become.

In this way, in a multiprocessor system, there is a demand to synchronize the bus cycle of the system bus with the system clock signal common to each processor, but when focusing on individual processors, This may create a constraint that an operating clock signal with a frequency desired for the operation of the built-in functional module must be adopted.

[Problem to be solved by the invention]

However, since the operating frequency of a processor is fixedly determined by either the oscillation output of the built-in oscillation circuit or the external clock frequency, in a multiprocessor system, the bus cycle of the system bus is determined by the system clock signal common to each processor. If an attempt is made to operate the built-in functional module such as a serial input/output circuit in a particular processor in synchronization with the system operation frequency, it may not be possible to operate the built-in functional module such as a serial input/output circuit in a particular processor at a frequency desired for system operation.

Such a situation may also occur if special consideration is given to the operating frequency of a serial input/output circuit coupled to a local bus of a particular processor.

For this reason, if the operating clock signal frequencies required for the operation of individual processors are different, it becomes impossible to commonly operate each processor included in the multiprocessor system using the system clock signal. As a result, each processor requires an individual wait state insertion circuit to make shared resources accessible from the system bus, which increases the system scale and further increases data processing latency due to wait state insertion. As a result, the overall data processing efficiency of the system decreases. Regarding this point, it is possible to deal with this by adding a new lock system equipped with an oscillation circuit to a specific function module such as a serial input/output circuit, but this increases the number of oscillation modules and is particularly In the case of a processor that includes the serial input/output circuit etc. on a single semiconductor substrate, the chip area and the number of external terminals increase.
Furthermore, the processor operating clock signal output from the oscillation circuit, the output clock signal of the oscillation circuit specially provided for a specific function module such as a serial input/output circuit, and the clock signal supplied from the outside are adjusted as necessary. A new configuration for selective switching control has also become necessary.
As a whole, the configuration becomes significantly complicated.

An object of the present invention is to simplify the configuration for synchronizing bus cycle operations of a system bus by the data processing device when configuring a system including a data processing device that requires a plurality of independent operating frequencies. The object of the present invention is to provide a data processing device that can contribute to reducing processing time for synchronization.

The above and other objects and novel features of the present invention are as follows:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, an oscillation circuit for obtaining an operating clock signal of the data processing device and a switch means for selectively employing a clock signal output from the oscillation circuit or a clock signal supplied from an external source as the operating clock signal are provided. This constitutes a data processing device.

For example, in addition to the central processing unit, if the data processing device includes an input/output circuit that must be operated at an independently determined frequency to obtain the baud rate required for operation, the input/output circuit built into the data processing device The clock signal output from the built-in oscillation circuit is supplied regardless of the clock selection operation by the switch means, and the clock signal selected by the switch means can be supplied to the central processing unit as an operating clock. There is a need to synchronize the bus cycle of the system bus with a common clock signal for each data processing device, and it is also necessary to adopt an operating clock signal with a frequency that is desirable for the operation of specific built-in function modules such as serial input/output circuits. Item 7 is preferable as it satisfies both constraints. Therefore, in such a case, when the central processing unit initiates a bus cycle to the outside, the switching means is controlled so that the clock signal supplied from the outside is adopted as the operating clock signal of the central processing unit. It is desirable to provide a switch control means.

Considering the case where the output of the oscillation circuit built in the data processing device is used as the system clock signal, in response to the switch means selecting the output clock signal of the built-in oscillation circuit as the operating clock signal, the selection switch Accordingly, the clock signal can be configured to be outputtable to the outside.

[For production]

According to the above-mentioned means, when the data processing device is required to operate at independent frequencies, the switching means operates to select an operating clock having a frequency compatible with the individual operations output from the oscillator circuit. However, when accessing the system bus, the switching means operates to select an externally supplied system clock signal as the operating clock. A configuration for synchronizing bus cycle operations of a system bus by each data processing device in a system including data processing devices that require a plurality of independent operating frequencies by using such an operating clock signal selection function of the data processing device itself. This achieves the simplification of the synchronization as well as the reduction of special processing time for synchronization.

[Embodiment 1] FIG. 2 shows an example of a multiprocessor system to which a microprocessor, which is an embodiment of the present invention, is applied.

The multiprocessor system shown in the figure includes, but is not limited to, three microprocessors 1 to 3,
Each of the microprocessors 1 to 3 shares a system bus consisting of a system data bus 5DRUS, a system address bus 5ABUS, and a system control bus (not shown).

A memory 4 and a disk controller 5 are coupled to this system bus as examples of shared resources that can be commonly used by the microprocessors 1 to 3.

In the multiprocessor system of this embodiment, for example, three microprocessors 1 to 3 can perform mutually independent processing according to a program, and when a specific microprocessor accesses a shared resource,
The bus right to the system bus is acquired via the bus arbiter 6.

The bus arbiter 6 includes respective microprocessors 1 to 3.
bus request signals BREQ, -BREQ are supplied from the microprocessors 1-3, and pass acknowledgment signals BACK1-BACK are supplied to the respective microprocessors 1-3. The bus arbiter 6 arbitrates requests for use of the system bus from the microprocessors 1 to 3 according to priority and timing of assertion of the bus request signals BREQ to BREQ, although this is not particularly limited. That is, when the system bus is in an open state, a pass acknowledge signal corresponding to the microprocessor requesting bus ownership is asserted to approve use of the system bus. When a plurality of bus use requests conflict with each other, the bus right is given to one predetermined microprocessor according to the earlyness of the bus use request and the priority assigned to each of the microprocessors 1 to 3 in advance.

Although not particularly limited, 5 microprocessors 1 to 3 each
The bus cycle of the system bus activated by the system bus is operated in synchronization with the system clock signal 5CLK supplied from the system clock generator 21.

FIG. 1 shows a detailed example of the microprocessor 1. As shown in FIG.

The microprocessor 1 shown in the figure is formed on a single semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique, although this is not particularly limited.

This microprocessor 1 includes, but is not particularly limited to, a central processing unit 10, an asynchronous serial communication interface 11 for asynchronous communication, a clock synchronous serial I10 port 12, a memory 13, etc., and these functional modules. is connected to the system data bus 5DR via a data input/output cover sofa (not shown).
Internal data bus IDBUS interfaced with US
It is also coupled to an internal address bus IABUS that interfaces with the system address bus 5ABUS via an address output buffer (not shown).

The central processing unit 10 includes, but is not particularly limited to, a general-purpose register, a program counter, a condition code register, an arithmetic and logic unit, etc. (not shown), and mainly processes data by sequentially reading instructions from a program memory (not shown).

Next, the central processing unit 10. Asynchronous serial communication interface 11. The operating clocks of the synchronous serial port 12 and the synchronous serial port 12 will be explained.

The microprocessor 1 has a built-in clock generator 14. Although this clock generator 14 is not particularly limited, the external clock generator 14 generates an operating clock CLK□ which is obtained by dividing the frequency of the vibrator 20 by a constant frequency. This operating clock C
LK□ is directly supplied to predetermined internal function modules such as the asynchronous serial communication interface 11 and the synchronous serial I10 board 12.

The central processing unit 10 receives an external clock supplied from the operation clock CLK or the clock input/output terminal 15, that is, a system clock signal SCLK according to this embodiment.
is selectively enabled to be supplied according to the switch state of the clock selection switch 16. When this clock selection switch 16 adopts a switch state in which the operating clock CLK generated by the built-in clock generator 14 is supplied to the central processing unit 10, the operating clock CLK can be outputted to the outside as a system clock, etc. A clock output selection switch 17 is provided.

The clock selection switch 16 is a switch control logic 18
The operating clock of the central processing unit 10 is selected by the selection signal 5EL1 output from the CPU 10.

Further, the clock output selection switch 17 is switch-controlled by the selection signal 5EL2 output from the switch control logic 18. This switch control logic 18 is
Although not particularly limited, the operating clock signal C is output from the built-in clock generator 14 in response to power-on.
It instructs the clock selection switch 16 to set an initial state in which the LK signal is supplied to the central processing unit 10, and also instructs the clock output selection switch 17 to enter an OFF state.

This switch control logic 18 includes a clock selection switch 1
6 and a control register 19 for specifying the operation mode of the clock output selection switch 17. This control register 19 includes a first control bit CB1 for instructing to change the initial state of the clock selection switch 16 to a state in which an externally supplied clock signal can be supplied to the central processing unit 10;
The clock signal supplied from the outside is sent to the central processing unit 1 only when the central processing unit 10 accesses the system bus.
a second control bit CB for instructing an operation mode in which clock output can be supplied to clock output selection switch 1;
The control bit CB3 includes a third control bit CB3 for instructing to change the bit 7 from the initial state to the on state. These control bits CB, CBZ, and C84 are not particularly limited, but desired bits are changed from a disable level to an enable level by a power-on reset.

The switch control logic 18 has a pass acknowledge signal BACK.
1 is supplied. When the second control bit CB2 is set to the enable level, the switch control logic 18 controls the operation of the clock selection switch 16 that enables the central processing unit 10 to be supplied with an externally supplied clock signal, although this is not particularly limited. , its path acceptance signal B
Synchronous control is performed during the assertion period of ACK1.

Note that the other microprocessor 2 shown in FIG.
, 3 are configured similarly to the microprocessor 1 shown in FIG. 1, although not particularly limited thereto.

Here, the maximum baud rate of the asynchronous serial communication interface 11 and the synchronous serial I10 port 12 included in each microprocessor 1 to 3 is defined by the operating clock frequency supplied thereto.

Therefore, for example, in system operation, the asynchronous serial communication interface 11 and the synchronous serial communication interface 11
0 port 12 maximum baud rate is microprocessor 1
Assuming that the baud rate is different for each microprocessor 1 to 3, the oscillator 20 is selected for each microprocessor 1 to 3 so that the built-in clock generator 14 can output an operation clock sufficient to obtain the optimum maximum baud rate for each individual microprocessor. adopt. Therefore, inside each microprocessor 1 to 3, the operating clock signal adopted in this way is supplied to the asynchronous serial communication interface 11 and the synchronous serial I10 port 12, and the operating clock signal adopted in this way is supplied to the asynchronous serial communication interface 11 and the synchronous serial I10 port 12. The maximum baud rate that can be used is satisfied.

On the other hand, the bus cycles of the system bus are
In response to a request to operate in synchronization with a common system clock signal 5CLK, each microprocessor 1 to
In the control register 19 of No. 3, only the second control bit CB is set to the enable level. As a result, the central processing unit 10 built in the microprocessors 1 to 3 is supplied with the system clock signal 5CLK from the outside when starting a bus access cycle, and is otherwise outputted from the respective clock generators 14. Operation clock signals CLK1, CLK2 . C.L.
K3 is supplied.

When the system is operated after the built-in control registers 19 in each of the microprocessors 1 to 3 have been set as described above by power-on reset, each microprocessor 1 to 3 has the built-in asynchronous When operating the serial communication interface 11 and the synchronous serial board 12, the asynchronous serial communication interface 11 and the synchronous serial board 1-12 in the individual microprocessors 1 to 3 are constantly supplied with a unique operating clock CLK1. ~CLK, is supplied.

Therefore, the asynchronous serial communication interface 11 and the synchronous serial I10 port 12 inside each of the microprocessors 1 to 3 operate at the maximum baud rate required for system operation.

For example, when the microprocessor 1 accesses the disk controller 5 via the system bus, the path access signal BAC output from the path arbiter 6
When K1 is asserted and the microprocessor 1 is authorized to use the system bus, the switch control logic 1 included in the microprocessor 1 is activated in response.
8 controls the clock selection switch 16 so that the system clock signal 5CLK supplied from the outside can be supplied to the central processing bag [10].This allows the central processing unit 10 of the microprocessor 1 to Bus cycles can be performed in synchronization with system clock signal 5CLK. The same applies when the microprocessors 2, 3 initiate a bus cycle for the system bus.

Note that if the operating clock signal CLKl of one of the microprocessors 1 to 3, for example, the microprocessor 1, can be used as the system clock signal SCL, the third control Only bit CB is set to the enable level. This allows microprocessor 1
The output operating clock signal CLK of the Glock generator 14 built into the microprocessor 1 is used as an operating reference clock for the entire microprocessor 1, and is also supplied to the other microprocessors 2.3 as a system clock.

According to the above embodiment, the following effects can be obtained.

(]) Regardless of the clock selection operation by the clock selection switch 16, the asynchronous serial communication interface 11 and synchronous serial communication interface 11 and synchronous serial communication interface 12 included in each of the microprocessors 1 to 3 are outputted from the built-in clock generator 14, regardless of the clock selection operation by the clock selection switch 16. The clock signal CL K□, CLK,.

CLK3 is supplied, and the clock signal selected by the clock selection switch 16 is supplied to the central processing unit 10 as an operating clock signal.

Therefore, each of the microprocessors 1 to 3 has a built-in asynchronous serial communication interface 11 or a synchronous serial I1 as required for system operation.
When operating the 0 port 12, the asynchronous serial communication interface 11 and the synchronous serial I10 port 12 in the individual microprocessors 1 to 3
Since a unique operating clock CLK is constantly supplied to the microprocessors 1 to 3, each of the microprocessors 1 to 3
The asynchronous serial communication interface 11 and the synchronous serial I10 port 12 inside the
It is possible to operate the system while satisfying the maximum baud rate required for each system operation.

(2) When accessing the system bus, clock selection switch 1 included in each microprocessor 1 to 3
6 is a system clock signal 5CL supplied from the outside.
K can be supplied to the central processing unit 10 as an operating clock. Therefore, the bus cycles of the system bus by the individual microprocessors 1-3 can be easily synchronized by the system clock signal 5CLK.

(3) From the above effects (1) and (2), multiple microprocessors 1 that require multiple independent operating frequencies
In a system including microprocessors 1 to 3, even if the oscillation frequencies of the built-in clock generators 14 in the individual microprocessors 1 to 3 are different, a wait state insertion circuit or the like is used to enable the microprocessors 1 to 3 to access shared resources. Since no special circuit is individually required, the configuration for synchronizing the bus cycles of the system bus by each microprocessor can be simplified, and special processing time is not required for such synchronization. is not required. In other words, there is a need to synchronize the bus cycles of the system bus to a common clock signal for each microprocessor, and a need to provide each microprocessor with an operating clock signal at a frequency that is desirable for the operation of built-in functional modules such as serial input/output circuits. Both of the constraints that must be adopted can be easily satisfied.

(4) System clock signal 5 supplied externally when a given microprocessor starts a bus cycle.
When controlling the clock selection switch 16 to enable CLK to be supplied to the central processing unit 10, the switching is performed in accordance with the switching operation mode set in the control register 19 in response to the acquisition of bus ownership. This makes its control relatively easy.

(5) In response to the clock selection switch 16 selecting the output clock signal of the built-in clock generator 14 as the operating clock signal, the clock output selection switch 17 is configured to output the clock signal to the outside. By.

The output of an oscillation circuit built into a specific microprocessor can be used as a system clock signal.

[Embodiment 2] FIG. 4 shows an example of a multiprocessor system to which a microprocessor is applied, which is another embodiment of the present invention.

The multiprocessor system shown in FIG. 3 includes, but is not limited to, the microprocessor 25 shown in FIG.
and other microprocessors 26. In FIGS. 3 and 4, the same components as those in the above embodiment are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In the multiprocessor system of this embodiment, the two microprocessors 25 and 26 can perform mutually independent processing according to a program, and when a specific microprocessor accesses a shared resource, bus arbitration is carried out by the third microprocessor. As shown in the figure, a central processing unit 27 built in a microprocessor 25 performs the processing.

When the microprocessor 26 requests the bus right, it asserts the bus refresh 1-signals BR, EQ to the central processing module W27. At this time, if the central processing unit 27 is not accessing the shared resource via the system bus, it asserts the pass acknowledge signal BACK to the microprocessor 26 to give it bus authority.

One microprocessor 25 shown in FIG. 3, like the microprocessors 1 to 3 of the above embodiments, has a central processing unit 27, an asynchronous serial communication interface 11 for asynchronous communication, and a clock synchronous serial I10. It is equipped with a port 12 and the like. The central processing unit 27, the asynchronous serial communication interface 11. and synchronous serial I10 boat 12
The operating clock systems are also configured in the same manner as in the above embodiment.

That is, the operating clock CLK output from the clock generator 14 is constantly connected to the asynchronous serial communication interface 11 or the synchronous serial I10.
It is directly supplied to a predetermined internal functional module such as the boat 12. The operating clock CLK or the system clock signal 5CLK supplied from the clock input/output terminal 15 can be selectively supplied to the central processing unit 27 according to the switch state of the clock selection switch 16.

The other microprocessor 26 has a configuration similar to the conventional one in which its operating frequency is fixedly determined by either the oscillation output from the built-in oscillation circuit or the clock signal supplied from the outside, although this is not particularly limited. . In particular, according to this embodiment, its operating frequency is determined by the system clock signal 5CLK supplied from the outside.

Here, the maximum baud rate of the asynchronous serial communication interface 11 and the synchronous serial I10 port 12 included in the microprocessor 25 is defined by the operating clock frequency supplied to these.
If the frequency of CLK cannot be obtained, the oscillator 20 of the microprocessor 25 is selected so that the built-in clock generator 14 can output an operating clock sufficient to obtain the optimum maximum baud rate. therefore,
Inside the microprocessor 25, the operating clock signal thus adopted is transmitted to the asynchronous serial communication interface 11 and the synchronous serial interface 11.
○The maximum baud rate required for system operation is satisfied.

On the other hand, in response to a request to synchronize the bus cycle of the system bus by the microprocessor 25 with the system clock signal 5CLK, the microprocessor 25
In the control register 19, only the second control bit CB2 is set to the enable level.

As a result, the clock selection switch 16 included in the microprocessor 25 supplies the operating clock signal CLK output from the clock generator 14 to the central processing unit 27 except for activating the bus access cycle, and also supplies the operating clock signal CLK output from the clock generator 14 to the central processing unit 27 during the bus access cycle. A clock signal 5CLK is received from the outside and supplied to the central processing unit 27.

Therefore, when the system is operated after the built-in control register 19 in the microprocessor 25 has been changed as described above by power-on reset,
Microprocessor 25 provides asynchronous serial communication interface 11 as required for system operation.
When operating synchronous serial E/○ port 12,
Asynchronous serial communication interface 11 and synchronous serial communication in microprocessor 25
○Since the unique operating clock CLK is constantly supplied to the boat 12, the asynchronous serial communication interface 11 and the synchronous serial I10 boat 12 inside the microprocessor 25 can satisfy the maximum baud rate required for system operation. and it works. When the microprocessor 25 accesses a shared resource such as the memory 4, the clock selection switch 16 included in the microprocessor 25 is used.

Since the system clock signal 5CLK is supplied to the central processing unit 27 as an operating clock, the microprocessor 2
The bus cycle of the system bus 5 is operated in synchronization with the system clock signal 5CLK.

As a result, as in the above embodiment, even in a multiprocessor system including microprocessors 25 that require multiple independent operating frequencies, it is desirable to synchronize the bus cycle of the system bus with a common clock signal for each microprocessor. Both this requirement and the constraint that a specific microprocessor must employ an operating clock signal of a frequency desirable for the operation of built-in functional modules such as serial input/output circuits can be easily satisfied.

Although the invention made by the present inventor has been specifically described above based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

For example, a microprocessor that requires multiple independent operating frequencies includes an asynchronous serial communication interface and a synchronous serial I10 port.

Although the case where the frequency of the internal oscillation circuit is selected in relation to the maximum baud rate has been described, the present invention is not limited thereto, and the microprocessor can be used with peripheral circuit modules other than an asynchronous serial communication interface or a synchronous serial I10 port. It may also have a built-in

Furthermore, a multiprocessor system including multiple microprocessors may include multiple multi-chip computers or single-chip computers.

In the above description, the invention made by the present inventor was mainly applied to a microprocessor constituting a multiprocessor system, which is the background field of application, but the present invention is not limited thereto. It can also be applied to a dedicated processor such as a protocol processor for communication control. The present invention
It can be applied at least to conditions where data processing is performed in synchronization with an operating clock.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, since the clock signal output from the built-in oscillator circuit and the clock signal supplied from the outside can be selectively used as the operating clock, the bus cycle of the system bus can be used as the clock signal common to each data processing device. The effect is that it is possible to realize a system that satisfies both the request to synchronize with the clock signal and the request that an operating clock signal with a frequency different from the above clock signal is required due to operational constraints of the built-in function module. . In this case, a special external circuit such as a wait state insertion circuit is not required in order to synchronize bus cycle operations of the system bus by data processing devices that require multiple independent operating frequencies. Moreover, since no special processing time is required for synchronization, it is possible to prevent the overall data processing efficiency from decreasing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microprocessor that is an embodiment of the present invention, FIG. 2 is a block diagram of a multiprocessor system to which the microprocessor shown in FIG. 1 is applied, and FIG. 3 is another embodiment of the present invention. Block Diagram of an Example Microprocessor FIG. 4 is a block diagram of a multiprocessor system to which the microprocessor shown in FIG. 3 is applied. 1-3...Microprocessor, 4...Memory, 5
...Disk controller, 6...Bus arbiter. 5CLK...System clock signal, CLK~CL
K3...Operating clock signal, BREQ~BREQ・
...Bus request signal, BACK□~BACK. ...Pass Acknowledge Signal, 10...Central Processing Unit,
11...Asynchronous serial communication interface, 12...Synchronous serial interface/○ port, 14
... Clock generator, 15... Clock input/output terminal, 16... Clock selection switch, 17...
Clock output selection switch, 18... Switch control logic, 19... Control register, 20... Oscillator, 21... System clock generator, 25° 26... Microprocessor, 27... Central processing Device. Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. In a data processing device that performs data processing in synchronization with an operating clock signal, an oscillating circuit for obtaining an operating clock signal, and a clock signal output from the oscillating circuit or supplied from the outside. 1. A data processing device comprising switch means for selectively employing a clock signal as an operating clock signal. 2. It has a built-in input/output circuit that receives a clock signal output from the built-in oscillation circuit as an operating clock signal regardless of the clock selection operation by the switch means, and receives the clock signal selected by the switch means as an operating clock signal. 2. A data processing device according to claim 1, comprising a central processing unit. 3. A switch control means is provided which can control the switching means so that when the central processing unit activates a bus cycle to the outside, a clock signal supplied from the outside is adopted as an operation clock signal of the central processing unit. 3. A data processing device according to claim 2, characterized in that the data processing device comprises: 4. The switch means includes a selection switch that enables output of the clock signal to the outside in response to selection of the output clock signal of the built-in oscillation circuit as the operating clock signal based on the control of the switch control means. A data processing device according to any one of claims 1 to 3, characterized in that the data processing device is a data processing device.