WO2002093392A1

WO2002093392A1 - Data processor

Info

Publication number: WO2002093392A1
Application number: PCT/JP2002/004526
Authority: WO
Inventors: Michihiro Horiuchi; Katsumi Iwata
Original assignee: Renesas Technology Corp.; Renesas Northern Japan Semiconductor, Inc.
Priority date: 2001-05-14
Filing date: 2002-05-09
Publication date: 2002-11-21
Also published as: JP2002342266A

Abstract

A data processor (1) comprises a central processing unit (2), a memory (5) accessible by the central processing unit, input/output circuits (12, 13), and a FIFO control circuit (6) for operating the memory as a FIFO buffer for the input/output circuits. The FIFO control circuit specifies memory areas used as a FIFO buffer by using area specifying means, holds address information for read and write accesses for each specified memory area in address pointer means, and includes control means for FIFO-operating a predetermined area in response to a request of the input/output circuit by means of the address pointer means. Therefore, any FIFO buffer for only the input/output circuits is not required because the buffer composed of an on-chip memory and the FIFO control circuit is provided, the chip area is small, the cost is low, and the increase of the chip area caused by providing a FIFO buffer for the input/output circuits is suppressed.

Description

Technical Data Processor

The present invention relates to a FIFO (First-In First-Out) buffer function for an on-chip peripheral circuit or an input / output circuit of a data processor called a microcomputer or a microprocessor. It functions as an effective technology when applied to a single-chip microcomputer equipped with an input / output circuit for communication or high-speed data input / output control or peripheral circuits. Background art

In a data processor for device control, SCI (Serial Communication Bus) represented by Universal Serial Bus (USB), Multimedia Card (MMC), Infrared Data Association (IrDA), Universal Asynchronous Receive-Transceiver (UART) Interface controllers such as Interface) and IIC (Inter IC Bus) are becoming more and more on-chip. In order for these interface controllers to support high-speed, large-capacity data transfer, an FIF 0 buffer must be installed. For example, the interface controller inputs data from an external device sequentially at a predetermined transfer rate, and a buffer for input data and data so that the input data is not lost. Use a FIFO buffer. Since the storage capacity of the FI FO buffer is finite and relatively small, if there is a relatively large gap between the data processing capacity of the CPU and the data input rate, a buffer such as the FIF 0 buffer is used. Evening buffers alone cannot fill that gap. Therefore, the data captured in the FIF 0 buffer Evening: The CPU may have to process the data transferred to AM and stored in RAM. In particular, in recent years, data transmission and reception speeds with other system devices have been increased, and the amount of transferred data has been increasing. FIFII is becoming necessary.

Incidentally, Japanese Patent Application Laid-Open No. 2-168318 is an example of a document describing a peripheral circuit employing a FIFO buffer.

However, as the number of input / output interface circuits on-chip in the data processor increases, it is necessary to mount a dedicated FIF 0 buffer for each input / output interface circuit. It leads to an increase.

When inputting data from the first input / output interface module and processing the input data and supplying it to the outside from the second input / output interface module, The data received by the input / output interface module is sequentially transferred from the FIFO buffer to the RAM, the CPU reads the transferred data from the RAM, performs arithmetic processing, and writes the arithmetic result to the RAM. Wit. The data written to the RAM is transferred to the FIF0 buffer of the second interface module and transmitted to other devices. At this time, data transfer between the FIF0 buffer and the RAM must be performed using a CPU or a DMAC. This transfer process is a memory access operation different from the RAM access for the CPU to process the reception data. If the CPU or DMAC also uses the bus to perform such data transfer processing, the time occupied by the CPU or DMAC for such data transfer will be prolonged, and the data transfer processing of the system as a whole will take place. Speed decreases.

An object of the present invention is to provide a FIF 0 buffer for an input / output circuit or a peripheral circuit. Another object of the present invention is to provide a data processor which can suppress an increase in the chip area due to hardware.

Another object of the present invention is to provide a data processor capable of suppressing a decrease in data processing capability due to data transfer processing between an FIF buffer of an input / output circuit and an on-chip memory such as a RAM. Nime

Still another object of the present invention is to provide a data processor which can eliminate the need for a data transfer process between a FIFO buffer of an input / output circuit and an on-chip memory such as a RAM.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

The following is a brief description of an outline of typical inventions disclosed in the present application.

[1] << RFU area designation >> The data processor according to the present invention comprises a central processing unit, a memory accessible by the central processing unit (5), and a plurality of input / output circuits (12, 22, 13, 17). ) And an FIF 0 control circuit (6) for operating the memory as FIF 0 buffers of the plurality of input / output circuits in one semiconductor chip.

The FIF 0 control circuit includes: an area designating unit (BAR, DTCR FIFI size designating field) for defining a plurality of memory areas used as the FIF 0 buffer; and a memory area defined by the area designating unit. Address means for holding address information for read access and write access, for example, address pointer means (RAR, WAR); and a predetermined response to a request from one of the plurality of input / output circuits. Memory area And a control unit for performing a FIFO operation using the addressless connection unit.

As the input / output circuit, for example, a plurality selected from a serial communication interface controller, a universal serial bus controller, a noise-width modulation circuit, a timer circuit, an analog / digital converter, and a digital / analog converter. Circuit.

As described above, the RAM buffer realized by the on-chip memory and the F0 control circuit eliminates the need for a FIFO buffer dedicated to the input / output circuit. By eliminating the need for a dedicated FIFO, the chip area can be reduced and costs can be reduced. Since this RAM buffer operates in FIFO with respect to the memory area specified by the error designation means, CPU access operation or data transfer control operation by DMAC for data transfer between the I / O circuit and the memory area. Does not require

[2] << Programmer specification >> The specification by the area specifying means may be fixed or variable. For example, the area designation means is a storage means capable of programmably designating the plurality of memory areas. If the specified contents can be changed, the FIFO capacity according to the transfer data structure can be set as desired within the range of the memory capacity. Alternatively, it becomes easy to optimally allocate the memory area of the RAM buffer according to the state of use of the memory by the CPU.

The FIFO control circuit may further include input / output circuit designating means for designating, for each of the plurality of input / output circuits, the use of each of the plurality of memory areas defined by the area designating means. The designation by the input / output circuit designation means may be fixed or variable. If it is variable, it can be used as the FIF 0 buffer specified by the above-mentioned error designation means. A very small number of memory areas can be shared by many input / output circuits. For example, the input / output circuit designating means is a storage means capable of programmably designating the input / output circuit.

In particular, the input / output circuit may be specified programmatically for each of read access and write access to the memory area of the RAM buffer. For example, the input / output circuit specification means can separately and programmably set input / output circuit specification information used in a read operation and input / output circuit specification information used in a write operation for each memory area. It is a storage means. Thus, the data of one input / output circuit is written to one memory area defined by the area designating means, and the central processing unit reads the write data and performs arithmetic processing. In addition, it is possible to write the result of the arithmetic processing to the memory area and read the written result of the arithmetic processing by another input / output circuit. In short, one memory area can be used for separate I / O circuits for read and write. Since one memory area can be used as a read / write separate FIF 0 buffer for multiple input / output circuits, the FIFO buffer of one memory area is shared by multiple input / output circuits. It becomes possible. As a result, data can be transferred between the input / output circuits without performing processing by the central processing unit, and high-speed continuous transfer of data between the input / output circuits becomes possible.

The area designating means and the input / output circuit designating means can be constituted by register means accessible by the central processing unit.

[3] A more specific mode relating to the above-mentioned programmable designation will be described. As the area designating means, a register means (BAR, DTCR) for defining the memory area according to a base address and size information may be employed.

The addressless bus means includes a read for the pace address. A read address register (RAR) for holding offset address information for writing and a write address pointer (WAR) for holding offset address information for writing with respect to the base address may be employed.

For the CPU, the memory area of the RAM buffer is a memory area where random access is possible. Consider allowing the CPU to easily recognize the memory area as FIF0. For example, in the FIFO control circuit, a memory address obtained by adding the read offset address information to the base address is held as a read start address, and a memory address obtained by adding write offset address information to the base address is stored. A memory address register means (NRA, NWA) for holding a dress as a write head address is provided, and the memory address register means is accessible by the central processing unit. When accessing the memory area in the FIF II format, the CPU can directly obtain the read start address and the write start address of FIF 0 by accessing the memory address register means, and the base address and the read address can be obtained. It is not necessary to access the offset address information for writing and the offset address information for writing, and to perform arithmetic processing one by one.

Further, the FIFO control circuit is provided with data number register means (DAT AN, F RE EN) indicating the number of valid data that can be read and the number of empty areas that can be written, and the data number less register means. Are accessible by the central processing unit. Thus, when the CPU accesses the memory area in the FIF〇 format, the calculation for obtaining the number of data that can be read until reaching the empty state and the number of writable data until reaching the full state can be performed. No action is required.

[4] << Competition control >> The memory may be dedicated to the FIFO or may be arranged in an address space of the central processing unit like a main memory. You may. In the latter case, the central processing unit, FIFO control circuit and memory are connected to a common bus.

When a plurality of FIFO operation requests compete, the control means can arbitrate the competition of the requests by accepting a request having a higher priority according to a priority order.

The FIF 0 control circuit responds to a request for FIF 0 operation from one of the plurality of input / output circuits by requesting a bus control unit to acquire a bus right, and by activating the FIFO operation after acquiring the bus right. Arbitrate bus rights for common buses.

[5] << CPU clock control >> In order for the FIF 0 control circuit to start the FIF 0 operation in response to a request from the input / output circuit, the FIF 0 control circuit must acquire the bus right from the CPU. Before that, the CPU needs to finish the intermediate processing. If this bus cycle wait time is long, the FIFO operation cannot be performed in response to the periodic request from the input / output circuit. For example, assuming a communication I / O circuit that receives data overnight at 12 Mbps, data is received overnight at 667 ns per byte, which is a data processor operating at 2 MHZ. Is equivalent to processing one byte of data every 13 cycles. When the operating clock frequency of the CPU is reduced in an operation mode such as the low power consumption mode, the number of CPU operation cycles permitted as the bus cycle waiting time is smaller than the above 13 cycles, and the CPU operation speed is reduced. If is left as it is, there is a possibility that the received data may be missed. Therefore, as a clock control circuit for controlling the operation clock signal of the central processing unit, the FIFO control circuit selects the operation clock signal of the central processing unit when controlling the FIFO operation in response to a request from the input / output circuit. A configuration that can be changed to a high-speed operation clock signal as far as possible is adopted. Thus, when the FIFO control circuit performs the FIFO operation in response to a request from the input / output circuit, the CPU operates at a high speed, so that the amount of arithmetic processing that can be performed by the CPU before acquiring the bus right increases, and the bus cycle waiting time increases. Can be shortened. As a result, it is possible to prevent a delay in following the FIFO operation, which is typified by the loss of data over the reception.

As a specific aspect, the clock control circuit includes a clock generation circuit capable of outputting a first clock signal of a first frequency and a second clock signal of a second frequency lower than the first frequency. The first clock signal or the second clock signal can be selected as an operation clock signal to be supplied to the central processing unit, and the FIFO control circuit is input when the second clock signal is selected. When performing the FIF 0 operation in response to a request from the output circuit, the second clock signal is changed to the first clock signal. The FIFO control circuit is best operated in synchronization with the first clock signal or a third clock signal having a third frequency higher than the first frequency of the first clock signal.

[6] The CPU clock control described above can be applied not only when the FIF 0 control circuit is used as the bus master, but also when acquiring the bus right by other bus master means. That is, the data processor includes a central processing unit, a control circuit for controlling an operation clock signal of the central processing unit, and a bus control unit for acquiring a bus right in place of the central processing unit. Wherein the clock control circuit performs control to change the operation clock signal of the central processing unit to a high-speed operation clock signal within a selectable range in response to the possibility of acquiring the bus right by the bus mass means. <When the data processor having this configuration further includes a memory accessible by the central processing unit and a plurality of peripheral circuits of the central processing unit, the data processor is connected to the memory and the peripheral circuits as the bus mass unit. , An FI FO control circuit that operates the memory as a FI FO buffer of the peripheral circuit can be employed. The FIFO control circuit includes an area specifying means for specifying a plurality of memory areas to be used as the FIF 0 buffer, and address information for read access and write access for each memory area specified by the area specifying means. And a control means for performing a FIF operation using a predetermined memory area in response to a request from the peripheral circuit, using a predetermined address area.

The FIFO control circuit includes an input / output circuit designating unit that designates a peripheral circuit that uses the plurality of memory areas specified by the area designating unit. In response to a request from the input / output circuit specified in the above, a function of causing the memory area used by the input / output circuit to perform the FIF 0 operation using the address binding means may be realized. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram illustrating a data processor according to the present invention.

FIG. 2 is a block diagram showing an example of the RFU.

FIG. 3 is a flowchart illustrating the initial setting of the RFU and the FIFO operation control based on the initial setting.

FIG. 4 is a block diagram mainly showing the data processor of FIG. 1: RFU.

FIG. 5 is a block diagram showing an operation example when data is transferred from the SCI to the MC IFC using one FIFO channel under the control of the RFU. FIG. 6 is an explanatory diagram exemplifying an assignment state of a boyfriend to an ID number.

FIG. 7 is a flowchart illustrating an example of a data transfer operation from SCI to MCIFC using one FIFO channel shown in FIG.

FIG. 8 is a block diagram illustrating a data processor according to the comparative example of FIG.

FIG. 9 is a flowchart showing an operation example when transmitting the SCI reception data from the MCIFC using the configuration of FIG.

FIG. 10 is an explanatory diagram schematically showing the operation using the FRU described in FIGS. 5 and 7.

FIG. 11 is an explanatory diagram schematically showing an operation using the FIF0 buffer unique to the peripheral circuit described with reference to FIGS. 8 and 9.

FIG. 12 is a timing chart illustrating the operation timing of the above-described mouth control.

FIG. 13 shows still another operation example. 9 is a timing chart for explaining the effect of the exclusive use of the bus by the FIFO buffer control processing by the RFU.

FIG. 14 is a timing chart illustrating an operation example for eliminating the influence of FIG.

FIG. 15 is a block diagram illustrating an audio system using a data processor. BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 shows an example of a data processor 1 according to the present invention. The data processor 1 shown in FIG. It is formed on one semiconductor substrate (semiconductor chip) such as single crystal silicon.

The processor 1 has a central processing unit (CPU) 2, a DMA controller (DMAC) 3, a read-only memory (ROM) 4, which is a program memory for storing processing programs for the CPU 2, and a CPU 2 Random access memory (RAM) 5, FIFO control circuit (RFU) 6, bus controller 7, clock generation circuit (CPG) 8, clock control circuit (RAM) C CNT) 9, Interrupt controller 10, Evening counter (TMR) 11, Serial communication interface, Evening controller (SCI) 12, Universal serial bus controller (USB) 13, 〇1 ^ 0 arithmetic unit 14, digital analog converter (D / A) 15, analog digital converter (AZD) 16, memory card controller (MC IFC) 17, pulse Wise Modulation Night (PWM) 18 Fakonto roller 1 9, watchdog evening timer (WDT) 20, a free-running evening timer (FRT) 2 1, the cryptographic computing units (DE S) 22 and the output port 2 3-2 5. The CPU 2, DMAC 3, M4, RAM 5, RFU 6, and bus controller 7 are connected to a CPU bus 28. The CPU bus 28 is connected to a peripheral bus 29 via a path controller 夕, and the peripheral bus 29 is connected to the interrupt controller 10, TMR 11, and SCI 12 as peripheral circuits. , USB 13, CRC calculator 14, D / A 15, A / D 16, MC IFC 17, PWM 18, keyboard buffer controller 19, WDT 20, FRT 21, and encryption Arithmetic unit 22 is connected. The CPU bus 28 and the peripheral bus 29 include a data bus, an address bus, and a control signal bus, respectively. The peripheral bus 29 is connected to an external bus (not shown) via the input / output port 23. The CPU bus 28 is interfaced with a peripheral bus 29 via a bus controller and an external bus via an input / output port 23. I / O ports 24 and 25 function as external interface buffers for peripheral circuits. For example, a data reception terminal and a data transmission terminal in a predetermined communication channel of the SCI 12 are assigned to a predetermined port of the input / output port 25.

In the data processor 1, the bus modules are the CPU 2, DMA C3, and RFU 6. For example, the CPU 2 fetches an instruction from R0M4 and decodes the fetched instruction.The CPU 2 performs an arithmetic operation using a general-purpose register, an arithmetic logic unit, or the like according to the instruction decoding result by the instruction control unit. An execution unit for performing processing. The DMAC 3 is initialized by the CPU 2 for data transfer conditions, and performs data transfer control in response to a data transfer request from a peripheral circuit or the like.

The RFU 6 is a control circuit capable of operating the RAM 5 as a FIFO buffer of peripheral circuits, for example, SCI 12, USB 13, MC IFC 17, and DES 22 according to the initial setting by the CPU 2. It is. From the peripheral circuits SCI 12, USB 13, MC IFC 17 s and DES 22 to R FU 6, a start signal (request signal) for operating RAM 5 as a FIFO buffer and an acknowledgment signal (acknowledge signal) for it are Collectively referred to as signal group 30. When the RFU 6 requests the FIFO buffer operation, the RFU 6 requests the bus controller 7 for the bus right with the bus request signal 31 and receives an approval for the bus right with the bus acknowledge signal 32. For the circuit, control the RAM 5 to operate as a FIF 0 buffer and perform direct memory access control. In short, the RFU 6 operates as a function program in which the DMA transfer control function and the FIF 0 point control function are combined. About the details Will be described later.

The operating speed of the peripheral circuits SCI 12, USB 13, MCI FC 17, and DES 22 is directly or indirectly affected by the speed of the information interface with the outside. For example, in the case of SCI 12, USB 13, and MC IFC 17, the received data must be accumulated so as not to miss the data for the data reception baud rate. In the case of DE S22, it is necessary to perform an encryption operation or the like for the transmission data in time to meet the transmission speed.

The bus controller 7 arbitrates for contention of a bus request between the bus master module CPU 2, RFU 6, DMAC 7, and the external bus master. The arbitration logic is, for example, arbitration control based on priority. As a result of the arbitration, the bus master module to which the bus right is granted outputs a bus command, and the bus controller 7 controls the bus based on the bus command. The bus controller 7 outputs an address signal and an access strobe signal to the outside via the input / output port 23 when the address signal output from the bus master module indicates the external address space of the data processor 1.

The interrupt controller 10 receives an interrupt request signal (not shown) output from a circuit module such as the SCI 12 connected to the peripheral bus 29, and performs priority control and mask control on the input interrupt request signal. To accept the interrupt request. Upon receiving the interrupt, the interrupt controller 10 outputs an interrupt request signal (not shown) to the CPU 2. When an interrupt request signal is given to the CPU 2, the CPU 2 interrupts the processing being executed and branches to a predetermined processing routine according to the interrupt factor. At the end of the processing routine at the branch destination, a return instruction is executed, and by executing this instruction, the interrupted processing can be restarted. In addition, data processor 1 has external terminals such as ground level (V ss) and power supply voltage level (Vc c) as power supply terminals, and reset control (RES), standby (input) STBY), mode control input (MD0, MD1), and clock input (EXTAL, XTAL).

The CPG 8 is, although not particularly limited, a clock signal ø1 (first clock signal) based on a crystal oscillator connected to the terminals EXTAL and XTAL or an external clock signal input to the EXTAL terminal. Generates cycle signal 2 (second clock signal). The clock control circuit 9 selects a clock signal 11 or 2 according to the operation mode and the internal operation state of the data processor 1 and uses it as a reference clock (system clock). give. Although not particularly limited, the SCI 12, USB 13, MC I FC 17, and DE S 22 connected to the RFU 6 via the signal group 30 are expected to perform high-speed operation. The clock signal 01 is supplied as the synchronous operation clock signal, and accordingly, the clock signal 1 is supplied to the RFU 6 as the operation clock signal. A low-speed clock signal 02 is supplied to the keyboard buffer controller 19, D / A 15, and A / D 16 as a synchronous clock signal.

When the reset signal RES is supplied to the data processor 1, the on-chip circuit modules such as the CPU 2 are reset. When the reset state by the reset signal RES is released, the CPU 2 reads the instruction from the predetermined address, starts the program execution, and accordingly fetches the data from the RAM 5, for example. Then, it performs arithmetic processing on the fetched data, and based on the processing results, performs signal input / output with external devices using USB 13 or SCI 12 to control various devices. FIG. 2 shows an example of the RFU6. : The RFU 6 has eight FI F0 channels CH0 to CH7, though not particularly limited. Each FIF channel has a base address register BAR, a read address pointer: RAR, a write address pointer WAR, a temporary pointer TMR, a valid data byte register DATAN, and a read start address register. It has NRA, Head of Writer Dress Register NWA, Data Transfer Control Register DT CR, Data Transfer Status Register DTS TR C, Data Transfer ID Register DTI DR.

B AR _S R AR WAR, the value of the four registers evening / pointer TM 0 is converted into RAM Adoresu when R FU bus cycle. These registers / pointers can be read-Z-written by the cpu instruction. In addition, the calculation results based on the contents of the REG, BAR, RAR, and WAR are reflected in the values of the four registers, DATAN, FREEN, NRA, and NWA, which can be read by CPU instructions. It is possible.

The RFU 6 has a control circuit 40 for controlling the entire system. As a register for setting control information for overall control, a data transfer ID read / write selection register DTIDSR, a data transfer ID register, etc. It has an evening transfer status register DTST, a data transfer register selection register DTRSR, and other registers DTIER and DTCRD.

The register BAR is set with a base address in a memory area of the RAM 5 which can be operated as a FIFO buffer.

The above-mentioned register RAR is a register read cycle for specifying a RAM address to be read in a RAM read cycle. The RAM address when operating RAM5 as a FIFO buffer is calculated by BAR + RAR ₍ this value is the FIFO address when peripheral circuits such as SCI 12 read RAM5 as FI F0 buffer). Address. The value is also held in the register NAR, and is read and used when CPU2 accesses RAM5 as a FIFO buffer. The value of the RAR is: The control circuit 40 increments the value by the number of read bytes every RAM read cycle. However, it is not incremented beyond the size of the selected FIF 0 buffer, and is cleared to 0 when it is incremented up to the FIFO buffer size.

The pointer WAI or RFU 6 is a pointer for specifying a RAM address to be written in an AM write cycle. The RAM address when operating RAM5 as a FIF0 buffer is calculated as BAR + WAR. This value is used as a FIFO write address when a peripheral circuit such as SCI12 writes RAM5 as a FIFO buffer. The value is also held in the register NWA, and is read and used when the CPU 2 accesses the RAM 5 as a FIFO buffer. The value of the pointer WAR is incremented by the number of write bytes in each RAM write cycle, but is not incremented beyond the selected FIFO buffer size, and the value is cleared to 0 at that time. Pointer TMP is a temporary address bus available when using USB 13 as a source or destination.

The register DATA indicates the number of valid data bytes that can be read in the FIFO buffer in the pointer set of each FIFO channel. The register evening FREE N indicates the number of free area bytes that can be written to the FIF buffer in the evening set of each FIFO channel. The register NRA has a value of BAR + RAR. The calculation is performed by the control circuit 40. The Registrar NWA holds the value of BAR + WAR. The calculation is performed by the control circuit 40. These four registers D AT AN, FREEN, NR A, NWA use Read and use when accessing as FO buffer.

The register DTCR includes the size of a memory area as a FIFO buffer (FIFO buffer size), the data size of a bus cycle started by a peripheral circuit such as CSI12, the use of a temporary rebuffer, the FIF 0 Select whether or not to detect the detection of full (war RAR status by write bus cycle) in the full flag of the register DTSTR. FI FOempty (RAR = WAR status by read bus cycle) Is used to specify whether or not to reflect the detection of occurrence) in the empty flag of the DTSTC register.

Register DTSTRC is FIF0 full (depending on write bus cycle)

A flag that indicates the detection of WAR2 RAR status occurrence), a flag that indicates the detection of FIFO empty (the occurrence of RAR = WAR status due to a read bus cycle), and the like are set. The control circuit 40 detects the FIF0 full and the FIF0 empty.

Register DT IDR is a register that selects peripheral functions that can request activation of the FIF 0 channel. Peripheral functions are assigned 4-bit ID numbers in advance. For example, a unique ID number is assigned to the USB 13 separately for each communication channel, and for each of the transfer direction from the RAM 5 to the USB 13 and the transfer direction from the USB 13 to the RAM 5. Similarly, a unique ID number is assigned to the SCI 12 for each communication channel and for each of the transfer direction from the RAM 5 to the SCI 12 and the transfer direction from the SCI 12 to the RAM 5. The MC IFC 17 is assigned a unique ID number for each of the transfer direction from the RAM 5 to the MC IFC 17 and the transfer direction from the MC IFC 17 to the RAM 5. A unique ID number is assigned to the DES 22 for each of the transfer direction from the RAM 5 to the DE S 22 and the transfer direction from the DES 22 to the RAM 5. 2 for the DTI DR for each FIF 0 channel ID numbers are set. When an ID number is set in one register DTI DR, the data transfer direction is read (the data transfer direction from RAM to peripheral circuits) and write (the data transfer direction from peripheral circuits to RAM). Combine so that At this time, the types of peripheral circuits need not be the same. For example, by setting the write direction ID number of USB 13 and the read direction ID number of MC IFC 17 in one FIF 0 channel, the reception of USB 13 using one FIFO buffer Processing that transfers the data to MC IFC 17 is also possible.

The register DTIDSR sets the transfer direction indicated by the ID number. However, since the ID number is assigned to the peripheral function in advance, the transfer direction is fixed.

In the register DTSTR, interrupt enable information for selecting whether to output an interrupt signal when a full flag empty flag or the like is set is set.

The register evening D TR SR is connected to CPU 2

This register is used to specify R, RAR, WAR, TMP, DATA, FREEN, NRA, and NWA that can be accessed by CPU 2. As a result, the designated register can be directly accessed by the CPU 2 via the internal module data bus 41 and the internal data bus bus 42. It is not necessary to always place all registry evenings in the CPU 2 address space. Incidentally, 28 D is a data bus constituting the bus 28.

The control circuit 40, § Dress Boyne evening control for Pointasedzu bets for each FI FO channels, Basuin evening face control between the bus controller I, from the peripheral circuit DES 22, SCI 1 2, USB 1 3 3 MC IFC 1 7 It performs start control and the like in response to the start request. The activation factor that can activate the operation of each FIF 0 channel of the RFU 6 is determined in advance for each ID number. For example, if the ID number 7 indicates the transfer direction from the USB 13 to the RAM 5 for a predetermined communication channel of the USB 13, the FIB output by the USB 13 in response to the request for the reception operation for the communication channel. The activation of the activation request signal for the FO operation becomes an activation factor of the FI FO channel corresponding to the communication channel of the USB 13 concerned. The control circuit 40 assigns priorities to the activation factors, although not particularly limited, in order to eliminate the competition for the activation factors for each ID number, and accepts the activation factors with a higher priority for the competition. The control circuit 40 requests the bus controller 7 for the bus right with a signal 31 to perform the FIFO operation corresponding to the received activation factor, and uses the RAM 5 after the bus right is approved by the response signal 32. : FIF 0 operation can be started. After obtaining the bus approval, the control circuit 40 returns the FIFOI operable state to the requesting source of the FIF0 operation by an acknowledge signal. FIG. 2 shows the FIF 0 activation request signal 12 eq from the SCI 12 and the FIF 0 acknowledgment signal 12 ack to the SCI 12, and the FIF from the MCI FC 17 〇 the activation request signal 17 req and the MC I FC 17 The FIF 0 acknowledgment signal 17 ack to is representatively shown.

The control circuit 40 outputs the RAM addresses sequentially generated by the address bus control to the address bus 28A included in the bus 28. In addition, as part of the addressless control of the control circuit 40, the full state and the empty state can be detected in the operating FIFO channel, and the full detection signal and the empty detection signal can be supplied to the corresponding peripheral circuits. It has become. FIG. 2 exemplarily shows a full detection signal 12 fu 1 and an empty detection signal 12 ept for the SCI 12 and a full detection signal 17 fu 1 and an empty detection signal 17 ept for the MC IFC 17. Generally, in the full state, it is necessary to stop the receiving operation by the peripheral circuit, and in the empty state, it is necessary to restart the receiving operation by the peripheral circuit. In some cases, a function is provided to output the interrupt request signal 6 irq to the interrupt controller 10 according to the full state detection or the empty state detection according to the setting value of the register.

FIG. 3 shows an example of the initial setting of the RFU 6 and the FIFO operation control based on the initial setting. First, select the channel to be set in the register DTR SR, set the base address of RAjVI in the register BAR of the selected channel (S l), and set the transfer size, FI FO size, etc. in the register DTCR. Set (S2). In addition to setting the ID number to be activated in the register DTI DR, the register DTIDSR is set for each ID number to indicate which of RAR and WAR the pointer updated at the time of transfer execution (S3). Then, the interrupt enable is set in the register DTIER (S4), the ID number set in each channel is enabled in the register DTCR (S5), and the enable setting for each channel is set in the register DT CRD. Perform (S6). As a result, the enabled FIF0 channel is placed in a transfer request (FIFO operation activation request) wait state (S7). When there is a transfer request, a bus right acquisition process is performed on the bus controller 7 (S8). If the transfer request is FIF 0 read, an empty detection is performed (S 9). If it is empty, an empty interrupt (or a notification by an empty detection signal) is generated (S 10). If not, read transfer is performed. Execute (S ll) and increment the read pointer (RAR) (S 12). Even after the increment, the empty detection is performed (S13), and if it is empty, an empty interrupt (or notification by the empty detection signal) is generated (S14). In decision step S 4 If not, the process returns to step S7. If the transfer request is a FIFO write, full detection is performed (S15). If full, a full interrupt (or notification by full detection signal) is generated (S16). If not, write transfer is performed. Is executed (S17), and the write pointer (WAR) is incremented (S18). After the increment, full detection is performed (S19), and if full, a full interrupt (or notification by a full detection signal) is generated (S20). Judgment Step S 19: If it is not empty, return to step S 7

FIG. 4 shows the data processor 1 mainly with the RFU 6. The overall function of RFU 6 will be explained based on the figure. For example, when a reception request is input to a predetermined communication channel of SCI 12 via input / output port 25, SCI 12 sends FIF 0 to RFU 6 by FIF 0 request signal 1 2 req assigned to the communication channel. Request action. The RFU 6 asserts the bus request signal 31 to request the bus right from the bus controller 7, waits for the bus acknowledge signal 32 to acknowledge the bus right, and then sends the FIFO acknowledge signal to the SCI 12 1 thereby _c a 2 ack to veers Bok, SCI 1 2 receives the input and output ports 2 5 Karade Isseki, speed intermittently data bus in response to reception de Isseki the baud rate one bets received data Output to 2 9 D. The data output to the data bus 29 D is transmitted to the data bus 28 D via the bus controller 7. The RFU 6 operates the FIFI channel assigned to the communication channel of the SCI 12 in synchronization with the reception operation, calculates the RAM address corresponding to the FIF 0 push operation using the address book set, Output to address bus 28 A. At this time, the bus controller 7 generates the RAM access strobe signal. As a result, the data received on the predetermined communication channel of the SCI 12 is stored in the FIF 0 area of the RAM allocated to the communication channel. Stored sequentially in FIF 0 format.

In FIG. 4, for example, when a transmission request is input to the MC IFC 17 via the input / output port 24, the MC IFC 17 requests the RFU 6 to perform the FIF 0 operation by the FIF 0 request signal 17 req. The RFU 6 asserts the bus request signal 31 to request the bus right from the bus controller 7 and waits for the bus acknowledge signal 32 to acknowledge the occupation of the bus right. Assert ack. As a result, the RFU 6 operates the FIFI channel assigned to the MC IFC 17 in synchronization with the transmission operation of the MC IFC 17, and sets the RAM address for the FIF 0 pop operation to the address pointer set. And output to address bus 28 A. : The AM access strobe signal is generated by the bus controller 7. The data responding to the RAM address is sequentially read out to the data bus 28D, and propagated to the data bus 29D via the bus controller 7. In parallel with this, the MCIF 17 sequentially takes in the data on the data bus 29D and outputs the data from the input / output port 24 to the outside according to a predetermined protocol.

FIG. 5 shows an operation example when data is transferred from the SCI 12 to the MC IFC 17 using one FIF 0 channel of the RFU 6. In the figure, the bus controller 7 is not shown. Also, buses 28 and 29 are grouped together, and their overnight buses are collectively referred to as D AT and the address buses are collectively referred to as ADR.

At this time, different ID numbers are set for read and write to one FIFO channel of: FU6. For example, as the activation request ID number, ID = 8 meaning FIFO write from SCI 12 and ID = 0 meaning FIFO read from MC IFC 17 are set. A light point WAR is assigned to the operation started by ID = 8, The action activated by ID = 0 is assigned a lead-boin RAR.

The assignment state of the boyne to the ID number is as illustrated in FIG. In FIG. 6, reference numeral 50 denotes a memory area indicated by the register address BAR, ie, based on the address (H, E 800), ie, the address of the start of the FO: the memory area indicated by the buffer size of FIF 0, The end address is, for example, H'EFFF.

FIG. 7 illustrates a flowchart of a data transfer operation from the SCI 12 to the MC IFC 17 using one FIF0 channel shown in FIG. The SCI 112 stores the input data (reception data) from the outside in the data register 12Reg, and then requests the RFU 6 to start the FIFO operation with the signal 12req (S30). Upon receiving this, the RFU 6 acquires the internal bus right, and then transfers the data in the data register 12Reg to a predetermined area (FIFO buffer area) of the RAM 5 (S31). Then, the MCIF 17 on the receiving side waits until the built-in register 17Reg becomes empty, and requests the RFU 6 to start the FIFO operation with the signal 17Req (S32). As a result, the RFU 6 acquires the bus right of the internal bus, and then transfers the data in the FIF0 buffer area of the RAM 5 to the data register 17Reg (S33).

FIG. 8 illustrates a data processor according to the comparative example of FIG. No.

In the configuration shown in Fig. 8, SCI and MC IFC each have dedicated FIFI buffers. FIG. 9 exemplifies an operation flowchart when transmitting the SCI reception data from the MC IFC using the configuration of FIG. The SCI stores the received data in the FIFO buffer (S34). When several bytes of data are stored in the FI F0 buffer, the SCI issues an interrupt request (S35). The interrupt request is processed by the interrupt controller and the CPU In response, the CPU reads the received data from the SCI FIF 0 buffer and transfers it to the RAM in accordance with the interrupt processing routine (S36). MC IFC issues an interrupt request when the FIFO buffer has enough free space (S37). The interrupt request is processed by the interrupt controller, and an interrupt signal is output to the CPU. In response to this, the CPU writes the data in the RAM to the FIFO buffer of the MCIFC according to the interrupt processing routine (S38). The MC I FC transmits the data stored in the FIFO buffer at any time (S39). FIG. 10 schematically shows the operation using the FRU 6 described in FIGS. 5 and 7. FIG. 11 schematically shows the operation using the FIF〇 buffer unique to the peripheral circuit described with reference to FIGS. 8 and 9. As is clear from a comparison between the two, the buffer realized by the meon-chip RAM 5 and the FU 6 eliminates the need for a dedicated FIF 0 buffer for peripheral circuits. Since the dedicated FIF 0 buffer becomes unnecessary, the chip area of the data processor 1 can be reduced, and the cost of the data processor 1 can be reduced. Since the RFU 6 performs a FIFO operation on the memory area defined by the base address register BAR and the FFO size, the data between the peripheral circuits such as the SCI 12 and the MC IFC 17 and the RAM memory area is used. The evening transfer does not require the CPU 2 access operation or the DMA C 13 overnight transfer control operation. In this regard, the situation in which data processing by the CPU 2 is spent for FIF 0 access control can be suppressed, and it becomes easy to keep the data processing capability of the data processor 1 high.

Base address register The memory area defined by the BAR and FIF〇 size can be changed according to the set value, so it depends on the transfer data structure; the FIFO capacity is desirably within the range of the memory capacity. It can be set. Or RFU 6 depending on the memory usage by CPU 2 FI; It is easy to optimally allocate the RAM memory area for F0.

The RFU 6 registers a peripheral circuit which can be a request source of a FIFO operation with respect to the plurality of memory areas which can be used as an FIFO buffer as defined by the base address register BAR and the FIFO size. Since the data can be variably designated by the DTI DR, a small number of memory areas that can be used as the FIF 0 buffer can be shared by many input / output circuits.

In particular, with the register DTI DR: Regarding the designation of the source of the FIFO operation activation request, the peripheral circuits can be variably designated for each of the read access and the write access to the memory area functioning as the FIF buffer. The CPU 2 reads the data from one peripheral circuit for one memory area, and the CPU 2 reads the data from the write circuit and performs arithmetic processing, and writes the result of the arithmetic processing to that memory area. In addition, it becomes possible to use the written operation processing result read by another peripheral circuit. In short, one memory area can be used for separate peripheral circuits for read and write. One memory area can be used as a FIFO buffer for multiple peripheral circuits separately for read / write, so FIF 0 data in one memory area can be shared by multiple peripheral circuits. . As a result, data can be transferred between peripheral circuits without performing direct data transfer processing by the CPU 2, and high-speed continuous data transfer between peripheral circuits becomes possible.

Next, a technique for improving the time margin of the FIF 0 operation by the RFU 6 will be described. As described with reference to FIG. 4, in order for the RFU 6 to start the FIF 0 operation in response to the start request from the peripheral circuit, the RFU 6 must acquire the bus right from the CPU 2, By then CP It is necessary for U2 to end the arithmetic processing in the middle. If this bus cycle wait time is long, the FIF operation cannot be performed in response to an intermittent start request from peripheral circuits. For example, assuming a communication input / output circuit that receives data overnight at 12 Mb ps, data is received at 667 ns per byte. This is equivalent to processing one byte every three cycles. When the operating frequency of CPU 2 is low in an operation mode such as low power consumption mode, the number of operation cycles of CPU 2 allowed as the bus cycle wait time is the above 13 cycles. If the operation speed of the CPU 2 is kept as it is, the reception data may be missed. Therefore, the CPU control circuit 9 for controlling the operation clock signal of the CPU 2 operates when the RFU 6 performs the FIF 0 operation in response to the activation request from the peripheral circuit. Control to forcibly change to high-speed operation clock signal ø1. For this control, a bus right request signal 31 given from the RFU 6 to the bus controller 7 is used. In short, if the bus right quest signal 31 is enabled, it is guaranteed that the RFU 6 will acquire the bus right and perform FIFO control at the timing after the path contention is avoided. It is. At this time, the RFU 6 is preferably operated in synchronization with the clock signal ø1 or another clock signal (third clock signal) having a higher frequency than the frequency of the clock signal ø1. The case where the CPU 2 operates synchronously with the slow clock signal 02 is, for example, a case where a low power consumption mode or the like is set by the mode signals MD0 and MD1.

Thus, when the RFU 6 performs the FIFO operation in response to the start request from the peripheral circuit, the CPU 2 operates at a high speed, so that the amount of arithmetic processing that the CPU 2 can process before acquiring the bus right increases, and the bus cycle wait time Save time it can. Therefore, it is possible to prevent a delay in following the FIFO operation, which is typified by the loss of the reception data.

The operation timing of the clock control will be described based on FIG. For example, CPU 2 is operated in synchronization with clock signal ø2 in response to a low power consumption mode or the like. Two cycles of the clock signal 1 are regarded as one state of the CPU, and in the states ST 1 to ST 3, the CPU clock is the low-speed clock signal φ2. At time t0 in the state ST3, the bus request signal 31 is activated to a high level. That is, the RFU 6 accepts the operation start request by the time t0, and sets the bus request signal 31 to the high level in response to the request. The clock control circuit 9 selects the clock signal 01 as the CPU clock signal ø while the bus request signal 31 is at the high level. Accordingly, one cycle of the clock signal 01 forms one state after the state ST4. During this time, CPU 2 executes the necessary arithmetic processing at high speed up to the relinquishment of the bus right in synchronization with clock signal ø1.c This causes CPU 2 to relinquish the bus right in three cycles of clock signal ø1. Instead, RFU 6 acquires the bus right and is required in state ST7: Perform FIF 0 operation by RAM access. When the processing of the FIF0 operation is completed, the RFU 6 deactivates the bus request signal 31 and relinquishes the bus right. When the clock control circuit 9 detects the relinquishment of the bus right by the bus request signal 31 in the state ST8, the clock control circuit 9 switches the CPU clock ø to the original low-speed clock ø2 in the next state ST9, thereby performing the low power consumption operation. Make it continuable.

FIG. 13 shows still another operation example. Since the FIF 0 buffer control processing by the RFU 6 requires the occupation of the bus right, the bus occupancy by the CPU 2 and the like is reduced accordingly. For example, as shown in Fig. 13, both CPU 2 and RFU 6 operate with two cycles of clock signal 1 as one state. When an RFU cycle is inserted, CPU 2 cannot occupy the bus during that time, and the data processing performance of CPU 2 is reduced.

The example in Fig. 14 is an example to solve this problem.For example, both CPU2 and RFU6 operate with two cycles of clock signal ø1 as one state, but actually operate with one cycle of clock signal ø1. Have been completed. In short, one cycle of the clock signal 01 in the latter half is not substantially used. If this assumption holds, then when RFU 6 acquires the bus, the clock signal

Execute RAM access for FIF buffer. As a result, it is possible to suppress the apparent decrease in system performance. FIG. 15 illustrates an audio system 55 using the data processor 1 described above. This audio system is not particularly limited, but is positioned as an MPS player. A DSP 56 for digital signal processing calculation for audio reproduction is connected to the bus controller 7. The digital audio signal is converted to an analog signal by DAC 57, amplified by amplifier 58, and made available for sound from headphone 59 or the like. This audio system can be connected to a mobile phone 60 via SCI 12 as an input means of MP3 data, and can interface with a memory card 61 such as a multimedia card via MC IFC 17. It can be interfaced with a host PC 62 such as a personal computer via the USB 13. For example, the RFU 6 is used for transfer control and pointer control for both data storage and reading between the USB-connected host PC 62 and the memory card 61 connected to the MC IFC 17. It can be realized by processing by the FIF 0 operation using the built-in RAM 5 as a buffer area. Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the gist of the invention.

For example, peripheral circuits such as SCI, USB, and DES are positioned as input / output circuits. An input / output circuit is a circuit that inputs information from the outside and outputs it to the outside.In a narrow sense, it may be called a peripheral interface circuit, a peripheral interface controller, a peripheral input / output circuit, etc. A variety of circuits meeting such a definition can be employed for the input / output circuit.

The area specifying means for specifying the memory area used as the FIF 0 buffer is not limited to the means for specifying the head memory address and the size, but may be given by the start memory address and the end memory address. As necessary, the CPU does not have a register that holds the read start address, the write start address, the number of valid data that can be read, and the number of valid data that can be written, so that the CPU can easily access the memory area. (The memory used for the FIF 0 buffer is not limited to RAM such as the main memory of the CPU. For example, a RAM dedicated to the FIFO buffer may be used. It does not mean that the operating clock is limited to only two types, and that the operating speed of the CPU during low-speed operation is increased. The control is not limited to the method using the bus control signal output from the RFU 6. The CPU clock may be switched at high speed in response to a request for starting the FIF0 buffer operation for the RFU.

It is needless to say that the clock switching control is applicable not only when the RFU acquires the bus right, but also when the other bus modules such as DMAC and DTC acquire the bus right. As described in detail above, effects obtained by typical ones of the inventions Is briefly described as follows.

That is, by using the built-in memory such as RAM in the FIFO format, it becomes unnecessary to provide a dedicated FIFO buffer in the input / output circuit such as the input / output interface module.

Since the built-in memory can be used as a FIF0 buffer of a plurality of interface modules, FIF0 data can be shared by a plurality of modules. As a result, data can be transferred between the input / output circuits without performing CPU processing, and high-speed continuous data transfer between the input / output circuits becomes possible.

By eliminating the need for a dedicated FIF 0 buffer, the chip area can be reduced and the manufacturing cost of the data processor can be reduced.Data processing using multiple input / output circuits can be accelerated, and the processing power of the system can be increased. We can expect improvement. Industrial applicability

INDUSTRIAL APPLICABILITY The present invention can be widely applied to a data processor such as a single-chip microcomputer equipped with an input / output circuit for high-speed data communication or high-speed data input / output control or a peripheral circuit.

Claims

The scope of the claims

1. A central processing unit, a memory accessible by the central processing unit, a plurality of input / output circuits, and a FIFO control circuit for operating the memory as a FIF buffer of the plurality of input / output circuits. Included in semiconductor chips,

The FIFO control circuit includes an area designating unit that defines a plurality of memory areas used as the FIFO buffer;

Address means for holding address information for read access and write access for each memory area;

Control means for causing a predetermined memory area to perform FIF 0 operation using the address means in response to a request from one of the plurality of input / output circuits. Data processor.

2. The FIFO control circuit includes input / output circuit designating means for designating each of the plurality of memory areas specified by the area designating means for each of the plurality of input / output circuits,

The control means, in response to a request from one of the plurality of input / output circuits, stores a predetermined memory area to be used by one of the plurality of input / output circuits using a FIFO operation using the address means. 3. The data processor according to claim 2, wherein

3. The data processor according to claim 1, wherein said area designating means is storage means capable of programmably designating said plurality of memory areas.

4. The data processor according to claim 2, wherein said input / output circuit designating means is storage means capable of programmatically designating said plurality of input / output circuits.

5. The input / output circuit designating means can separately and programmably set, for each memory area, the designation information of the input / output circuit used in the read operation and the designation information of the input / output circuit used in the write operation. 3. The data processor according to claim 2, wherein said data processor is a simple storage means.

6. The data processor according to claim 2, wherein said area designating means and input / output circuit designating means are register means accessible by a central processing unit.

7. The data processor according to claim 3, wherein said area designating means is a register means for defining said memory area by a base address and size information.

8. The address means includes a read address pointer for holding read offset address information for the base address, and a write address register for holding write offset address information for the base address. 8. The data processor according to claim 7, wherein:

9. The FIFO control circuit holds a memory address obtained by adding the read offset address information to the base address as a read start address, and stores the memory address obtained by adding the write offset address information to the base address. 9. The data processor according to claim 8, further comprising memory address register means for holding as a write head address, wherein said memory address register means is accessible by said central processing unit. .

10. The FIFO control circuit has data register means for indicating the number of valid data that can be read and the number of free areas that can be written, and the data number register means includes a central processing unit. 10. The data processor according to claim 9, wherein the processor is accessible by:

11. The memory, wherein the memory is arranged in an address space of the central processing unit, and has a common bus connected to the central processing unit, a FIFO control circuit, and a memory. 3. The data processor according to paragraph 1 or 2.

12. The control unit according to claim 11, wherein said control means receives a request having a higher priority according to a priority when said requests from said plurality of input / output circuits compete. De overnight processor.

13. A bus control means for arbitrating a bus right, wherein the FIFO control circuit responds to the request for the FIF 0 operation from one of the plurality of input / output circuits to the bus control means. 12. The data processor according to claim 11, wherein an acquisition request is issued, and said FIFO operation is started after acquiring said bus right.

14. The data processor according to claim 1, wherein the memory is a main memory of the central processing unit.

15. The plurality of input / output circuits include a serial communication interface controller, a universal serial bus controller, a pulse width modulation circuit, a timer circuit, an analog digital converter, and a digital / analog converter. 3. The data processor according to claim 1, wherein the data processor is a plurality of circuits selected from the group consisting of:

16. A central processing unit, a clock control circuit for controlling an operation clock signal of the central processing unit, a memory accessible by the central processing unit, a plurality of input / output circuits, and the memory FIF of output circuit F FIF 0 control circuit to operate as buffer included in one semiconductor chip,

The FIFO control circuit includes a plurality of FIFO control circuits used as the FIF 0 buffer. Area designation means for defining a memory area of

Address pointer means for holding address information for read access and write access for each memory area defined by the error designating means;

Control means for causing a predetermined memory area to perform a FIFO operation using the address pointer means in response to a request from one of the plurality of input / output circuits,

When the FIFO control circuit performs a FIFO operation in response to a request from one of the plurality of input / output circuits, the clock control circuit can select an operation clock signal of the central processing unit. A data processor _c , which controls to change to a high-speed operation signal at

17.The clock generation circuit is capable of outputting a first clock signal of a first frequency and a second clock signal of a second frequency lower than the first frequency,

The cook control circuit can select the first clock signal or the second clock signal as an operation clock signal to be supplied to the central processing unit, and in a state where the second clock signal is selected, When the IF0 control circuit performs an FIF0 operation in response to a request from one of the plurality of input / output circuits, the second clock signal is changed to the first clock signal. The data processor according to claim 16.

18. The said: The FIFO control circuit is operated in synchronization with the first clock signal or a third clock signal of a third frequency higher than the first frequency of the first clock signal. A data processor according to claim 17, characterized in that:

1 9. The FIFO control circuit is configured to control the Including an input / output circuit specification means for specifying an input / output circuit that uses a plurality of memory areas,

In response to a request from the input / output circuit designated by the input / output circuit designation means, the control means causes the memory area used by the input / output circuit to operate as a FIFO using the address pin means. The data processor according to claim 16 or 17, wherein the data processor is a data processor.

20. A single semiconductor chip includes a central processing unit, a clock control circuit for controlling an operation clock signal of the central processing unit, and bus master means for acquiring a bus right in place of the central processing unit.

The clock control circuit controls the operation clock signal of the central processing unit to be changed to a high-speed operation clock signal within a selectable range in response to the possibility of acquiring the bus right by the bus master means. It is a processor that is characterized by its existence.

2 1.The clock generation circuit is capable of outputting a first clock signal of the first frequency and a second clock signal of a second frequency lower than the first frequency,

The cook control circuit can select the first cook signal or the second clock signal as an operation clock signal to be supplied to the central processing unit, and selects the second clock signal. 20. The apparatus according to claim 20, wherein the second clock signal is changed to the first clock signal in response to a possibility of acquiring the bus right by the bus masking means in a state where the bus right is received. Data processor.

22. The bus master means is operated in synchronization with the first clock signal or a third clock signal having a third frequency higher than the first frequency of the first clock signal. A data processor according to claim 21.

23. The apparatus further comprises a memory accessible by the central processing unit, and a plurality of peripheral circuits.

The bus mass means is a FIFO control circuit that is connected to the memory and the peripheral circuit and operates the memory as a buffer of the peripheral circuit.

Address binding means for holding address information for read access and write access for each memory area;

Control means for operating a predetermined memory area in FIF 0 operation using the address pointer means in response to a request from the peripheral circuit;

20. The data processor according to claim 20, wherein the data processor comprises:

24.The FIFO control circuit includes input / output circuit designating means for designating a peripheral circuit using the plurality of memory areas defined by the area designating means,

The control means responds to a request from the input / output circuit designated by the input / output circuit designation means, and stores a memory area used by the input / output circuit in a FIFO operation using the address binding means. 24. The data processor according to claim 23, wherein the data processor is configured to cause the data processor to execute the processing.