JP2000276436A - Dma control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a DMA control device which is switched to the low-power consumption mode in accordance with the bus use proportion of plural devices. SOLUTION: A bus occupation rate S of a bus 5 is calculated in a bus monitor part 5 on the basis of bus use permission signals ack1 to ack3. If the calculated bus occupation rate S is lower than preliminarily determined decision value '10', a mode switching signal LWS is outputted to a CPU 14 by a low- power consumption mode switching decision part in a bus arbitration part 6. Thus, a DMA control device 10 is surely switched to the low-power consumption mode when DMA control parts 1 to 3 are scarcely operated. Consequently, the power consumption is effectively suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct memory access control (hereinafter, also referred to as "DMA control") device for reducing power consumption. More specifically, a transition to the low power consumption mode is performed according to the usage ratio of the shared bus by a plurality of devices connected to the shared bus.
The present invention relates to an MA control device. For example, like a copying machine, a CPU and other devices (scanner, printer, etc.)
This is suitable for use in devices that share a bus.

[0002]

2. Description of the Related Art A known DMA control device includes a bus arbitration unit for arbitrating a bus access when a plurality of devices request a bus access. FIG. 7 shows an example of the system. FIG.
Basically, the system shown in FIG.
DMA control units 101 to 103 and the access control unit 104 perform data transfer by accessing the memory 107 via the shared bus 105, having A control units 101, 102, 103 and an access control unit 104. It is. A bus arbitration unit 106 for arbitrating access to the bus 105 from each of the DMA control units 101 to 103 and the access control unit 104 is provided. Also, DMA
A printer 111 is connected to the control unit 101,
A scanner unit 112 is connected to the A control unit 102,
A hard disk 113 is connected to the MA control unit 103, and a CPU 114 is connected to the access control unit 104.

As shown in FIG. 8, a request signal re of each of the DMA control units 101 to 103 is transmitted to a bus arbitration unit 106.
Request input register 115 to which q1 to req3 are input
, A priority table T in which priorities for accessing the bus 105 are stored, a bus response control unit 117 for returning a bus use permission signal ack, and a time when the request signals req1 to req3 are not input to the request input register 115. And a low power consumption mode transition determination unit 118 that issues a mode transition signal LWS for transitioning to the low power consumption mode based on the timer value measured by the monitoring timer 116.

[0004] This system operates as follows. That is, for example, when the DMA control unit 101 needs to access the bus 105, the DMA control unit 101 outputs a request signal req1 to the bus arbitration unit 106. This request signal req1 is transmitted to the request input register 11
5 and the bus response control unit 117 returns a bus use permission signal ack1 if possible. While the permission signal ack1 is active, the printer device 111 can access the bus 105 via the DMA control unit 101. The same applies to other control units (devices).

[0005] Here, when there is a request from a plurality of control units at the same time, the bus arbitration unit 106 returns a bus use permission signal according to a predetermined priority table T. FIG. 9 shows an example of the priority table T. In the case of this priority order table, the bus arbitration unit 106
When the request signals req1, req2, req3, and req4 are output simultaneously, the bus arbitration unit 106 returns only the bus use permission signal ack1 having the highest priority. As a result, the DMA control unit 101 makes the other control units 102 to 10
Access to the bus 105 is given priority over the access to the bus 105. Similarly,
When the request signals req2, req3, and req4 are simultaneously output, the bus arbitration unit 106 returns only the bus use permission signal ack2 having the highest priority among them. Therefore, DM
The A control unit 102 accesses the bus 105 with priority over the other control units 103 and 104.

The monitoring timer 116 measures the time during which the request signals req1 to req3 of the DMA controllers 101 to 103 are not input to the request input register 115. When the timer value of the monitoring timer 116 exceeds a predetermined value, the low power consumption mode shift determination unit 1
18 to the CPU 114 from the low power consumption mode signal L.
WS is issued. When the CPU 114 receives the low power consumption mode signal LWS, the DMA control device 100 shifts to the low power consumption mode. As a result, power consumption is kept low.

[0007]

However, in the above-described conventional DMA control device 100, when the request signals req1 to req3 of the DMA control units 101 to 103 are not input to the request input register 115 within a predetermined time. Only the low power consumption mode had been shifted. For this reason, even if the request signal is not input at all since the last input of the request signal, if the request signal is input immediately before the end of the counting of the monitoring timer 116, that is, immediately before the predetermined time elapses, , Does not shift to the low power consumption mode. In addition, when such an input pattern of the request signal is repeated, the mode does not shift to the low power consumption mode even though the DMA control units 101 to 103 are hardly operated. That is, the conventional DMA control device 100 has a problem that power consumption cannot be effectively reduced.

Accordingly, the present invention has been made to solve the above-described problem, and a DM which shifts to a low power consumption mode in accordance with a bus usage ratio of a plurality of devices is provided.
It is an object to provide an A control device.

[0009]

According to the present invention, there is provided a DMA control apparatus, comprising: a CPU; a memory; a shared bus connected to the memory; and a shared bus connected to the shared bus. A plurality of devices that access the memory, and a bus monitoring unit that calculates a usage ratio of the shared bus for each predetermined time by each device;
And a mode shifting unit for shifting to a low power consumption mode based on a calculation result of the bus monitoring unit.

[0010] In this DMA control device, the bus monitor means calculates the usage ratio of the shared bus for each predetermined time by each device. And, by the mode shifting means,
The operation mode is shifted from the normal mode to the low power consumption mode according to the calculation result of the bus monitor. As a result, when the device is hardly operated, the transition to the low power consumption mode is reliably performed. Therefore, it is possible to effectively reduce power consumption.

Further, in the DMA control device according to the present invention, the mode shifting means may be a clock reducing means for lowering the frequency of a system clock.

Also in this DMA control device, the bus monitor means calculates the ratio of use of the shared bus by each device every predetermined time. Then, the frequency of the system clock is reduced by the clock reducing unit according to the calculation result of the bus monitoring unit. That is, high speed processing of data is not required when the device is hardly operating. Therefore, the operating speed of the entire system can be reduced. By delaying the system clock in this way, the power consumption of the entire system is reduced. Therefore, power consumption can be effectively reduced.

Further, in the DMA control device according to the present invention, it is preferable that the clock reducing means lowers the operating frequency of the control signal of the CPU.

Also in this DMA control device, the bus monitor means calculates the ratio of use of the shared bus by each device every predetermined time. Then, the operating frequency of the control signal of the CPU is reduced by the clock reducing means according to the calculation result of the bus monitoring means. That is, high speed processing of data is not required when the device is hardly operating. Therefore, the operation speed of the CPU can be reduced. By reducing the operating frequency of the control signal of the CPU in this manner, the power consumption of the CPU is reduced. Therefore, power consumption can be effectively reduced. Note that the control signal of the CPU here is C
It means a control signal input to the PU.

Further, in the DMA control device according to the present invention, it is preferable that the memory includes a storage unit that can be written and read at any time, and the clock reduction unit lowers an operating frequency of a control signal of the storage unit.

This DMA control device has a storage means (for example, DRAM or the like) capable of writing and reading data to and from the memory at any time. Therefore, it is necessary to perform a refresh operation to hold data in the memory. However, when the device is hardly operating, data writing and reading are not performed frequently. Therefore, high-speed operation is not required for the memory (storage means). Therefore,
In this DMA control device, the operating frequency of the control signal of the storage unit is reduced by the clock reduction unit in accordance with the usage ratio of the shared bus calculated by the bus monitor unit. That is, when the device is hardly operating, the operating frequency of the control signal of the storage means is lowered. Thereby, the power consumption of the storage unit is reduced. Therefore, power consumption can be effectively reduced.

Further, in the DMA control device according to the present invention, the memory includes a storage unit that can be written and read at any time, and the mode transition unit sets the operation mode of the storage unit to a self-refresh mode. It is also preferred.

This DMA control device is also provided with storage means (for example, DRAM or the like) capable of writing and reading data to and from the memory at any time, and it is necessary to perform a refresh operation to retain data in the memory. By the way, when the device is hardly operated, data writing and reading are not frequently performed. Therefore, even in such a case, performing refresh (auto-refresh) in the normal mode wastes power. Therefore, in this DMA control device, the operation mode of the storage means is switched to the self-refresh mode by the mode transition means according to the usage ratio of the shared bus calculated by the bus monitor means. That is, when the device is hardly operated, the operation mode of the storage means is the self-refresh mode. Thereby, the power consumption of the storage unit is reduced. Therefore, power consumption can be effectively reduced.

The self-refresh mode refers to a mode in which a refresh operation is automatically performed inside the storage means upon command input. Command input is also required to return from the self-refresh mode to the normal mode. On the other hand, the auto-refresh mode refers to a mode in which a normal operation is automatically restored after a refresh operation is performed by a command input.

[0020]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a DMA controller according to the present invention; The present embodiment relates to a DMA control device that controls access of each device to a bus in a copying machine.

(First Embodiment) First, a first embodiment will be described. As shown in FIG. 1, the DMA controller 10 includes a memory 7 having a DRAM,
A control units 1, 2, 3, and an access control unit 4; and a bus monitor unit 8. The DMA control units 1 to 3 and the access control unit 4 access the memory 7 via the shared bus 5. Things. Further, there are provided DMA control units 1 to 3 and a bus arbitration unit 6 which arbitrates access from the access control unit 4 to the bus 5 according to the usage ratio of the bus 5 calculated by the bus monitor unit 8. DMA control unit 1
Is connected to the printer device 11, the DMA control unit 2 is connected to the scanner device 12, the DMA control unit 3 is connected to the hard disk 13, and the access control unit 4 is connected to the CP.
U14 is connected. The CPU 14 controls the control of the entire copying machine including this system. The printer device 11, the scanner device 12, and the hard disk 13 can directly access the memory 7 without the intervention of the CPU 14 by the DMA controllers 1, 2, and 3, respectively.

The bus arbitration unit 6, as shown in FIG.
Request signals req1 and req from MA control units 1 to 3, respectively.
When 2, req3 is output, bus use permission signals ack1, ack2, ack3 are returned to the DMA control units 1 to 3 as appropriate. The bus arbitration unit 6 also issues a mode shift signal LWS to the CPU 14 for shifting to the low power consumption mode in accordance with the usage ratio of the bus 5.

As shown in FIG. 3, request signals req1 to req3 of each of the DMA control units 1 to 3 are provided in the bus arbitration unit 6.
And a priority table T storing the priority of accessing the bus 5.
Response control unit 1 for returning a bus use permission signal ack
7 and a low power consumption mode transition determination unit 18 that issues a mode transition signal LWS for transitioning to the low power consumption mode based on the occupancy S of the bus 5 calculated by the bus monitor unit 8 described below. . The control unit to which the bus use permission signal is returned can access the bus 5 only during a period in which the bus use permission signal issued from the bus arbitration unit 6 is active. When each of the DMA control units 1 to 3 and the access control unit 4 simultaneously output the request signals req1, req2, req3, and req4, a priority table T (see FIG. 9) in which predetermined priorities are recorded. ), The access to the bus 5 is arbitrated.

Subsequently, as shown in FIG. 4, the bus monitor unit 8 outputs a bus use permission signal ack output from the bus arbitration unit 6.
The active periods of 1, ack2, and ack3 are counted, and the bus occupancy S is calculated.
Is to be entered. And this bus monitor section 8
Is a counter 21, 22, 23 and a delay flip-flop (Delay Flip-Flop, hereinafter also referred to as "DFF") 3.
1, 32, 33, an adder 25, and a comparator 26. The terminal EN of the counter 21 has a bus use permission signal ack1
, A clock signal CS is input to a terminal CLK, and a counter clear signal CCS is input to a terminal CLR. On the other hand, the count value C1 of the counter 21 is output from the terminal Q, which is the terminal IN of the DFF 31.
Has been entered. The occupancy rate set signal SSS is input to the terminal CLK of the DFF 31, and the occupancy rate S 1 is output from the terminal OUT, which is input to the adder 25.

If the bus use permission signal ack1 input to the terminal EN is active at the rising of the clock signal CS input to the terminal CLK, the counter 21 counts up and counts the count value C1 to the terminal EN. The signal is output from Q and input to the terminal IN of the DFF 31. Then, when a counter clear signal CCS transmitted every predetermined period is input to the terminal CLK, the count value C1 is reset. The counters 22 and 23 have the same function.

When the occupancy ratio set signal SSS transmitted every predetermined period is input to the terminal CLK, the DFF 31
The count value C1 input from the counter 21 is output from the terminal OUT. That is, the DFF 31
Calculates the generation rate of the bus use permission signal ack1 in the input cycle of the occupancy rate set signal SSS, that is, the bus use rate of the DMA control unit 1. DFF32,
33 has the same effect, and the DFF 32
A bus use ratio of the A control unit 2 is calculated, and the DFF 33
The bus use ratio of the A control unit 3 is calculated. The adder 25 calculates the sum of the bus occupancies S1 to S3 calculated by the DFFs 31 to 33, that is, the bus occupancy S, and inputs the calculated bus occupancy S to the low power consumption mode shift determination unit 18. Note that the clock signal CS and the counter clear signal C
The CS and the occupancy rate set signal SSS are all generated inside the bus monitor 8.

The DMA controller 1 configured as described above
0 operates as follows. First, the bus occupancy S of the bus 5 is calculated by the bus monitor 8 based on the bus use permission signals ack1 to ack3. The bus occupancy S is input to the low power consumption mode shift determination unit 18. Then, the low power consumption mode shift determination unit 18 determines whether or not the bus occupancy S is smaller than the determination value “10 (%)”.
When the bus occupancy S is smaller than the determination value “10 (%)”, the mode shift signal LWS is output to the CPU 14.

When the CPU 14 receives the mode transition signal LWS output from the low power consumption mode transition determination unit 18, the CPU 14 transitions to the low power consumption mode. Also,
The CPU 14 sends a memory control signal MCS to the memory 7.
Is output. By this memory control signal MCS, the memory 7 also shifts to the low power consumption mode. Specifically, the mode shifts to the self-refresh mode. Alternatively, if the data can be erased, the mode may be shifted to the power down mode (no refresh). As a result, the power consumption is reduced to about 1/50 as compared with the normal mode. When the bus occupancy S calculated by the bus monitor 8 is larger than the determination value “10 (%)”,
The mode transition signal LWS is not output, and the DMA controller 1
0 does not shift to the low power consumption mode.

If the bus occupancy S exceeds the judgment value "10 (%)" after the transition to the self-refresh mode, the mode returns to the normal mode. Here, an external command input is required to return from the self-refresh mode to the normal mode. For this reason, the processing speed is slightly reduced when shifting to the self-refresh mode as compared with the auto-refresh mode. But,
This mode transition does not affect the data processing in the memory 7. Thereafter, such transition of the operation mode is performed according to the bus occupancy S, so that power consumption can be effectively reduced.

As described above in detail, according to the DMA control device 10 of the first embodiment, the bus occupancy S of the bus 5 in the bus monitor 8 is determined based on the bus use permission signals ack1 to ack3. Is calculated. When the calculated bus occupancy S is smaller than the predetermined determination value “10”, the low power consumption mode transition determination unit 18 outputs a mode transition signal LWS to the CPU 14. As a result, when the DMA controllers 1 to 3 are hardly operating, the DMA controller 10 reliably shifts to the low power consumption mode. Therefore, power consumption can be effectively reduced.

(Second Embodiment) Next, a second embodiment will be described. DMA according to the second embodiment
The control device has substantially the same configuration as that of the DMA control device according to the first embodiment, except that the bus arbitration unit uses a clock reduction determination unit 3 instead of the low power consumption mode transition determination unit 18.
18 in that a clock reduction unit 310 is newly provided. That is, as shown in FIG. 5, the bus arbitration unit 6 arbitrates access to the bus 5 and generates a clock reduction signal LCS for reducing the frequency of the system clock in accordance with the bus occupancy S of the bus 5. It is issued to the reduction unit 310. Further, the clock reducing section 310 lowers the frequency of the system clock generated by the clock generating section 320 and supplies it to the CPU 14 and the memory 7 respectively. Note that CP
The frequency of the clock supplied to U14 and the memory 7 may be the same or different.

As shown in FIG. 6, request signals req1 to req1 of the DMA control units 1 to 3 are transmitted to the bus arbitration unit 6.
a request input register 15 to which q3 is input, and a bus 5
Table T storing the priority order for accessing the bus, the bus response control unit 17 for returning the bus use permission signal ack, and the occupancy S of the bus 5 calculated by the bus monitor unit 8.
And a clock reduction determination unit 318 that generates a clock reduction signal LCS based on the Here, in the clock reduction determining section 318, when the occupation ratio S of the bus 5 is smaller than the determination value “10 (%)”, the clock reduction signal LCS is issued to the clock reducing section 310. .

The DMA controller configured as described above has
It works as follows. First, the bus occupancy S of the bus 5 is calculated by the bus monitor 8 based on the bus use permission signals ack1 to ack3. This bus occupancy S is input to the clock reduction determining unit 318. Then, the clock reduction determining unit 18 determines whether or not the bus occupancy S is smaller than the determination value “10 (%)”. And the bus occupancy S
Is smaller than the determination value “10 (%)”, the clock reduction signal LCS is output to the clock reduction unit 310.

When the clock reduction unit 310 receives the clock reduction signal LCS output from the clock reduction determination unit 318, the clock reduction unit 310
, The frequency of the system clock input from is reduced, and the frequency is input to the CPU 14 and the memory 7 as respective clocks. The reason that the frequency of the system clock can be reduced in this way is that high-speed data processing is not required when the DMA control units 1 to 3 are hardly operated, so that the processing speed of the CPU 14 and the memory 7 can be reduced. Because. Thereby, the CPU 1
4 and the memory 7 are reduced in power consumption.
Low power consumption is achieved. When the bus occupancy S calculated by the bus monitor 8 is larger than the determination value “10 (%)”, the clock reduction signal LCS is not output, and the frequency of the system clock is not reduced.

If the bus occupancy S exceeds the determination value “10 (%)” after the frequency of the system clock is once reduced by the clock reduction unit 310, the clock reduction unit 310 sends the data to the CPU 14 and the memory 7. for,
A normal frequency system clock is supplied. Such a reduction in the frequency of the system clock causes the bus occupancy S
, Power consumption can be effectively reduced.

As described above in detail, according to the DMA control device of the second embodiment, the bus monitor 8 calculates the bus occupancy S of the bus 5 based on the bus use permission signals ack1 to ack3. Is done. When the calculated bus occupancy S is smaller than the predetermined determination value “10”, the clock reduction determination unit 318 outputs the clock reduction signal LCS to the clock reduction unit 310. Then, the frequency of the system clock is lowered by the clock reduction unit 310, and this low-frequency clock is
4 and the memory 7. Thereby, when the DMA control units 1 to 3 are hardly operated, the CPU
The power consumption of the memory 14 and the memory 7 is kept low.

The above embodiment is merely an example, and does not limit the present invention. Therefore, of course, the present invention provides various improvements without departing from the gist thereof.
Deformation is possible. As the first and second embodiments described above, the DMA control device in the copying machine has been exemplified.
The present invention is not limited to this, and the present invention can be applied to any apparatus that performs DMA control. Further, the bus monitor 8 may detect the bus occupancy S by detecting information on the bus 5 instead of the bus use permission signals ack1 to ack3.

Further, in the second embodiment, the CP
Although the case where both the frequency of the clock supplied to the U14 and the memory 7 are reduced is illustrated, only the frequency of the clock supplied to the CPU 14 or only the frequency of the clock supplied to the memory 7 can be reduced. Further, the frequency of the clock supplied to the DMA controllers 1 to 3 may be reduced. As a result, power consumption is further reduced. In the first embodiment described above, the low power consumption mode shift determination unit 18 is provided in the bus arbitration unit 6, but may be provided independently. Similarly, in the second embodiment, the clock reduction determining unit 318 may be provided independently instead of being provided in the bus arbitration unit 306.

[0039]

As described above, according to the DMA controller of the present invention, the mode shifts to the low power consumption mode based on the usage ratio of the shared bus by each device connected to the shared bus. As a result, when the device is hardly operated, the mode reliably shifts to the low power consumption mode. Therefore, power consumption can be effectively reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a DMA control device according to a first embodiment.

FIG. 2 is an explanatory diagram for describing operations of a bus arbitration unit and a bus monitoring unit of FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of a bus arbitration unit in FIG. 1;

FIG. 4 is a block diagram illustrating a configuration of a bus monitor unit of FIG. 1;

FIG. 5 is a block diagram illustrating a schematic configuration of a DMA control device according to a second embodiment.

FIG. 6 is a block diagram illustrating a configuration of a bus arbitration unit in FIG. 5;

FIG. 7 is a block diagram showing a schematic configuration of a conventional DMA control device.

FIG. 8 is a block diagram illustrating a configuration of a bus arbitration unit of FIG. 7;

FIG. 9 is an explanatory diagram for explaining priorities of bus arbitration control in a conventional bus arbitration unit.

[Explanation of symbols]

 1, 2, 3 DMA control unit 4 access control unit 5 bus 6,306 bus arbitration unit 7 memory 8 bus monitor unit 10 DMA control device 14 CPU req request signal ack bus use permission signal LWS mode transition signal LCS clock reduction signal SSS occupation Rate set signal CCS Counter clear signal CS Clock signal C Count value S Bus occupancy

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takeshi Minami 2-3-13 Azuchicho, Chuo-ku, Osaka-shi, Osaka Inside Osaka International Building Minolta Co., Ltd. (72) Inventor Nobuo Kamei Azuchi-cho, Chuo-ku, Osaka-shi, Osaka 2-3-1-3 Osaka International Building Minolta Co., Ltd. F-term (reference) 5B011 EB00 EB01 EB06 LL13 5B061 BA01 BA03 BB01 DD11 SS03 5B079 BA01 BB02 BB04 BC01

Claims (5)

[Claims] 1. A CPU, a memory, a shared bus connected to the memory, a plurality of devices connected to the shared bus and accessing the memory, and the shared bus at predetermined time intervals by the devices. A DMA control device, comprising: a bus monitor for calculating a usage ratio of a bus; and a mode shifter for shifting to a low power consumption mode based on a calculation result of the bus monitor. 2. The DMA controller according to claim 1, wherein said mode transition means is a clock reduction means for lowering a frequency of a system clock.
Control device. 3. The DMA control device according to claim 2, wherein said clock reducing means lowers an operating frequency of a control signal of said CPU. 4. The DMA control device according to claim 2, wherein the memory includes a storage unit that can be written and read at any time, and the clock reduction unit lowers an operation frequency of a control signal of the storage unit. DMA controller. 5. The DMA control device according to claim 1, wherein the memory includes a storage unit that can be written and read at any time, and the mode transition unit sets an operation mode of the storage unit to a self-refresh mode. DMA
Control device.