JP3830438B2 - Memory access arbiter, memory control device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory access arbiter (memory access arbitration / control circuit) and a memory control device including the memory access arbiter, and in particular, arbitration of access to a memory system including a DDR-SDRAM (Double Data Rate Synchronous DRAM). The present invention relates to a memory access arbiter and a memory control device.
[0002]
[Prior art]
As a technology related to memory access control, there is a technology that can execute self-refresh setting / cancellation for a memory system composed of SDRAM (Synchronous DRAM) without using a CPU and perform DMA transfer quickly. (See, for example, Patent Document 1).
[0003]
As is well known, because of its structure, a DRAM is a memory whose stored contents disappear if no charge is applied at predetermined time intervals. Generally, a memory controller reads data from the memory or replenishes charge. A refreshing operation is required every certain time. In particular, the function that the internal circuit of the DRAM itself performs a refresh operation is called self-refresh.
[0004]
The technique referred to in Patent Document 1 relates to a control device for an SDRAM in an SDR (Single Data Rate) mode. That is, data transfer is performed once during one cycle of the clock signal.
[0005]
On the other hand, DDR SDRAM (Double Data Rate Synchronous DRAM) exists as an improvement of SDRAM. This is an SDRAM that has a DDR (Double Data Rate) mode and that reads and writes data at both the rising and falling timings of the clock in one clock cycle. (Hereinafter referred to as “DDR-SDRAM”).
[0006]
The DDR-SDRAM is a memory that cannot be read for a predetermined clock interval (200 clock cycles in the current standard) after the self-refresh is canceled, and there is room for improvement in processing efficiency accordingly.
[0007]
[Patent Document 1]
Japanese Patent Laid-Open No. 2001-202777
[Problems to be solved by the invention]
The present invention has been made in view of such problems, and self-refresh cancellation is used as a mechanism for performing arbitration of memory access to a memory system composed of DDR-SDRAM having the above-described properties. It is an object of the present invention to provide a memory access arbiter that can quickly process memory access (CPU access and DMA transfer) even during a period in which reading cannot be performed between predetermined clocks later, and a memory control device including the arbiter.
[0009]
As a memory access arbiter and a memory control device for a memory system constituted by DDR-SDRAM, in particular, in the invention according to claim 1, it is constituted by DDR-SDRAM in which read access is impossible for a predetermined clock after releasing self-refresh. Instead of interrupting (rejecting) a request for memory access to a memory system that has been requested and received from each DMAC (DMA controller) or CPU during a predetermined clock after the self-refresh is released, An object of the present invention is to provide a memory access arbiter and a memory control device capable of improving processing of memory access by responding only to a write request regardless of priority.
[0010]
In particular, in the second aspect of the invention, the address and data relating to the write request that has been responded are stored in the buffer, and then the same address as that previously stored in the buffer during a predetermined clock after the self-refresh is canceled. An object of the present invention is to provide a memory access arbiter and a memory control device capable of improving the processing of memory access by returning and responding to data stored in the buffer when a read request is made. .
[0011]
[Means for Solving the Problems]
In order to achieve this object, the invention according to claim 1 is capable of accepting read requests and write requests from a plurality of DMA controllers and control means to a memory system that reads and writes data using memory as storage means. A memory access arbiter that allows the memory control unit to execute this request, accepts a self-refresh request and a release request, and causes the memory control unit to execute the request. It is characterized by responding only to a write request when a read request and a write request are received.
[0012]
According to a second aspect of the present invention, in the first aspect of the present invention, the address and data in the write request executed during the self-refresh release operation are stored in the buffer, and then the DMA is executed for the same address as that address. When a read request is received from the controller or the control means, the data stored in the buffer is returned and responded.
[0013]
The invention according to claim 3 is capable of accepting read requests and write requests from a plurality of DMA controllers and control means, and accepting self-refresh requests and release requests for a memory system that reads and writes data using memory as a memory means. A memory access arbiter capable of executing the above request to the memory system based on arbitration by the memory access arbiter, and the memory access arbiter has a buffer therein and performs a self-refresh release operation. When a read request and a write request are received, the memory control unit is caused to execute only in response to the write request.
[0014]
According to a fourth aspect of the present invention, in the third aspect of the invention, the memory access arbiter stores the address and data in the write request executed during the self-refresh cancel operation in the buffer, and thereafter, for the same address as that address. When the read request is received from the DMA controller or the control means, the data stored in the buffer is returned and responded.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Components are distinguished by adding symbols. FIG. 1 is a diagram showing an overall system configuration including a memory access arbiter (20) and a memory control device (100) including the memory access arbiter (20) according to an embodiment of the present invention.
[0016]
In particular, the present invention performs arbitration (arbitration / control) of memory access to a memory system that reads and writes data using “DDR SDRAM” (Double Data Rate Synchronous DRAM) (hereinafter “DDR-SDRAM”) as a storage means. Is.
[0017]
In FIG. 1, a memory control device (memory control circuit) 100 according to the present embodiment includes a memory access arbiter 20 and a memory control unit 30 according to the present embodiment, and a memory system 40 is connected to the memory control unit 30. Is done. The memory control device 100 includes a semiconductor integrated circuit, a plurality of DMACs and CPUs, and interface (request acceptance / response) units (11 to 17) with a self-refresh control device (self-refresh control unit), a memory access arbiter 20, a memory control The circuit such as the unit 30 is provided in an integrated form, typically in the form of an ASIC. The memory system 40 connected to the memory control unit 30 includes DDR-SDRAM as storage means.
[0018]
The DDR-SDRAM constituting the memory system 40 has a self-refresh function for performing self-refresh based on a self-refresh request, and reading (reading) is impossible during a predetermined clock (200 clocks) after the self-refresh canceling operation. It is a memory of the nature.
[0019]
The memory access arbiter 20 receives an access request to the memory system 40 from each of a plurality of DMACs (Direct Memory Access Controllers (DMA controllers)) (11 to 15) and the CPU (16) by an RREQ signal (Read Request) or a WREQ signal (Write Request). If it responds, it responds with an ACK signal (Acknowledge). When responding to a request, the request is issued to the memory control unit 30 to allow memory access. In normal times, the memory access arbiter 20 performs memory access arbitration based on the normal priority. Further, the memory access arbiter 20 receives a request (REQ) for setting / canceling self-refresh from the self-refresh control device (self-refresh control unit) 17 and issues a request to the memory control unit 30. The memory access arbiter 20 of this embodiment includes an address storage buffer 21 and a data storage buffer 22 inside.
[0020]
The memory control unit 30 makes a memory access or a self-refresh setting / cancellation request to the memory system 40 based on an access request via the memory access arbiter 20 and a self-refresh setting / cancellation request.
[0021]
In the access request signals from the DMACs 11 to 15 and the CPU 16, RREQ indicates a read request (data read request), and WREQ indicates a write request (data write request). In FIG. 1, they are collectively shown as “W / R REQ”. The REQ signal from the self-refresh control device 17 indicates a request signal for setting / releasing self-refresh.
[0022]
Hereinafter, two embodiments of the present invention having different operations in the memory control device 100 and the memory access arbiter 20 configured as described above will be described.
[0023]
FIG. 2 is a flowchart showing a control flow of the memory access arbiter 20 in the first embodiment of the present invention. A control procedure in the memory access arbiter 20 will be described according to the flow.
[0024]
Step S1: A self-refresh operation is being performed in the memory system 40 based on a self-refresh setting request REQ from the self-refresh control device 17.
[0025]
Step S2: When a self-refresh release request REQ is received from the self-refresh control device 17, a release request is issued to the memory control unit 30.
[0026]
Step S3: It is determined whether 200 clocks have elapsed since the self-refresh was canceled.
[0027]
Step S4: When a read request or a write request (W / R REQ) is received from each DMAC or CPU access during a period when 200 clocks have not elapsed since the self-refresh is released (step S3-NO), the read request is interrupted. (Reject) and do not respond. On the other hand, it responds to the write request and accepts the write target address and data.
[0028]
Step S5: When responding to the write request in the period when 200 clocks have not elapsed after the self-refresh is released in step S4, the target address and data in the responded write request are transferred to the memory control unit 30, and the memory control unit 30 sends them to the memory system 40. On the other hand, write processing is executed with the address and data.
[0029]
Step S6: When 200 clocks have elapsed from the cancellation of the self-refresh (step S3-YES), arbitration is performed with normal priority.
[0030]
FIG. 3 is a flowchart showing a control flow of the memory access arbiter 20 in the second embodiment of the present invention. The memory access arbiter 20 includes buffers (address storage buffer 21 and data storage buffer 22) inside. This buffer functions as a cache that makes memory access to the memory system 40 more efficient. A control procedure in the memory access arbiter 20 will be described according to the flow.
[0031]
Step S11: During the self-refresh operation in the memory system 40 based on the self-refresh setting request REQ from the self-refresh control device 17.
[0032]
Step S12: When a self-refresh release request REQ is received from the self-refresh control device 17, a release request is issued to the memory control unit 30.
[0033]
Step S13: It is determined whether 200 clocks have elapsed since the self-refresh was canceled.
[0034]
Step S15: When a read request or a write request (W / R REQ) is received from each DMAC or CPU access during a period when 200 clocks have not elapsed since the self-refresh is released (step S13-NO), the read request is interrupted. (Reject) and do not respond. It responds only when it receives a write request and accepts the address and data related to the write request.
[0035]
Step S16: When responding to the write request in step S15, the address and data of the responded write request are transferred to the memory control unit 30, and the memory control unit 30 causes the memory system 40 to execute the write process, and at the same time, the memory access arbiter Addresses and data are stored in internal buffers (address storage buffer 21 and data storage buffer 22).
[0036]
Step S14: When a read request is received from each DMAC or CPU during a period in which 200 clocks have not elapsed since the self-refresh was released (step S13-NO), the address related to the request in the read request is determined in step S16. It is determined whether the address stored in the internal buffer 21 matches.
[0037]
Step S17: If the address in the read request matches the address stored in the buffer 21 in step S14, the data stored in the buffer 22 is returned and responded.
[0038]
Step S18: After 200 clocks have elapsed from the cancellation of the self-refresh (step S13—YES), arbitration is performed with normal priority.
[0039]
The embodiment of the present invention has been described above. The above-described embodiment shows an example of a preferred embodiment of the present invention, and the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. .
[0040]
【The invention's effect】
As is apparent from the above description, according to the present invention, in a memory access arbiter that performs arbitration of memory access to a memory system configured using a DDR-SDRAM as a storage unit, and a memory control device including the memory access arbiter, According to the first aspect of the present invention, a plurality of DMACs or control means are requested for a memory system composed of a memory that cannot be read-accessed for a predetermined clock period after the self-refresh is canceled, even during a predetermined clock period after the self-refresh is canceled. The memory access process is improved regardless of the priority order, so that the memory access process can be improved.
[0041]
According to the second aspect of the present invention, the address and data of the write access responding during the predetermined clock after the self-refresh is released are stored in a buffer provided in the memory access arbiter, and then the predetermined value after the self-refresh is released. When a read request to the same address stored in the buffer is generated between clocks, the data stored in the buffer is returned and responded instead of being interrupted, improving the memory access processing There is an effect that can be done.
[Brief description of the drawings]
FIG. 1 is a diagram showing an overall system configuration including a memory access arbiter and a memory control device including the memory access arbiter according to an embodiment of the present invention.
FIG. 2 is a flowchart showing a control flow of a memory access arbiter according to the first embodiment of the present invention.
FIG. 3 is a flowchart showing a control flow of a memory access arbiter according to the second embodiment of the present invention.
[Explanation of symbols]
100 Memory Controllers 11-15 DMA Controller I / F Unit 16 CPU Access I / F Unit 17 Self-Refresh Control Device (Self-Refresh Control Unit)
20 Memory Access Arbiter 21 Address Storage Buffer 22 Data Storage Buffer 30 Memory Control Unit 40 Memory System

Claims (4)

For a memory system that reads and writes data using memory as a storage means, it can accept read requests and write requests from multiple DMA controllers and control means, cause the memory control section to execute the requests, and also request and release self-refresh A memory access arbiter capable of accepting a request and causing the memory control unit to execute the request;
A memory access arbiter having an internal buffer and responding only to a write request when the read request and the write request are received during the self-refresh canceling operation. The address and data in the write request executed during the self-refresh release operation are stored in the buffer, and then when a read request is received from the DMA controller or control means for the same address as the address 2. The memory access arbiter according to claim 1, wherein the memory access arbiter responds by returning data stored in the buffer. A memory access arbiter that can accept read requests and write requests from a plurality of DMA controllers and control means, and can accept self-refresh requests and release requests, for a memory system that reads and writes data using memory as storage means;
A memory control unit that executes the request to the memory system based on arbitration by the memory access arbiter,
The memory access arbiter has an internal buffer, and when the read request and the write request are received during the self-refresh canceling operation, the memory control arbiter responds only to the write request and executes the memory control unit Control device. The memory access arbiter stores the address and data in the write request executed during the self-refresh cancel operation in the buffer, and then receives a read request from the DMA controller or control means for the same address as the address 4. The memory control device according to claim 3, wherein the memory controller responds by returning the data stored in the buffer.

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