JP2005222245A - Processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a processor, and to further provide technology for speeding up processing therein. <P>SOLUTION: By providing a bus switch 145 allowing connection switching to a plurality of memory buses provided in each memory allowing individual access, and a bus switch controller 144 capable of controlling operation of the bus switch according to a memory access request from a central processor 10 or a data buffer controller 142, and allowing connection to the plurality of memory buses 15-1 to 15-n provided in each the image memory allowing the individual access, the access to the image memories 16-1 to 16-n can be individually performed through a corresponding memory bus. Thereby, probability of competition of the memory access is reduced, and the image processing is speeded up. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a processor and further to a technique for speeding up the processing in the processor, and more particularly to a technique effective when applied to an image processing processor for processing image data from a camera, for example.

  A digital image processing system is a flexible and flexible method that uses a computer to obtain different results by changing processing parameters even in the same processing. In particular, in image processing with a large number of processing data, since a single processor takes processing time, it is common to use a multiple processor configuration. As one of the methods, for example, a configuration is known in which a plurality of microprocessors and a large-capacity semiconductor memory are connected by the same bus, and each processor individually accesses and processes the large-capacity memory (see, for example, Patent Document 1). ).

JP-A-11-144045 (paragraph 0002)

  According to the above prior art, access from a plurality of processors to a large-capacity semiconductor memory is performed in a time-sharing manner, so that other processors are kept in a waiting state while one processor is accessing. This waiting state is regarded as a main factor that hinders high-speed processing. The multiple processors and large-capacity semiconductor memory are simple in structure and easy to implement, but the processing capacity is not proportional to the number of processors. This is because when the number of processors increases, the access contention to the large-capacity image memory increases, and the waiting time within the processing time increases.

  An object of the present invention is to provide a technique for increasing the processing speed.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, a system processor interface that can be connected to a central processing unit via a system bus, a data buffer that enables buffering of data to be processed, and a data buffer controller that can control the operation of the data buffer. When the processor is configured, the data transfer path between the central processing unit and the memory is switched by switching the connection with a plurality of memory buses provided for each individually accessible memory, and A bus switch capable of forming a data transfer path between the data buffer and the memory, and a bus switch controller capable of controlling the operation of the bus switch in response to a memory access request from the central processing unit or the data buffer controller And provide.

  According to the above means, the bus switch enables connection to a plurality of memory buses provided for each individually accessible image memory, so that access to the image memory can be performed by the corresponding memory bus. Can be done individually. This reduces the probability of competing memory accesses and achieves faster image processing.

  At this time, in order to avoid that the image data size exceeds the area size by changing the area size according to the data size of the image to be handled, a register in which the logical address space of the memory can be set in a programmable manner It is good to provide.

  In order to shorten the memory access time, the bus switch performs a first mode for simultaneously writing the same data to a plurality of memories, and stores data stored in the plurality of memories to which the same data is written in the central processing. The second mode can be configured to be individually readable according to read access from the apparatus and the data buffer controller.

  When read access to the same memory occurs from the data buffer controller and the central processing unit, both the data buffer and the central processing unit can quickly obtain read data from the memory. The bus switch controller includes an identical address determination circuit capable of determining whether an address for memory access from the central processing unit matches an address for memory access from the data buffer controller. It is preferable that the same data read from the memory by the memory access from the data buffer controller can be transmitted to both the central processing unit and the data buffer when the two addresses match.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, by enabling connection to a plurality of memory buses provided for each individually accessible image memory, access to the image memory is performed individually via the corresponding memory bus. This reduces the probability of competing memory accesses, thus achieving faster image processing.

  FIG. 1 shows an image processing system to which an image processor which is an example of a processor according to the present invention is applied. The image processing system 100 shown in FIG. 1 is not particularly limited, but a central processing unit (CPU) 10, a system memory 13, and an image processing processor 14 are connected so that signals can be exchanged with each other via the system bus 11. Is done. The image processor 14 receives image memories 16-1, 16-2, 15-n via image memory buses 15-1, 15-2, 15-3,..., 15-n provided separately from the system bus 11. 16-3, ..., 16-n are connected. The image memories 16-1, 16-2, 16-3,..., 16-n are individually connected via corresponding image memory buses 15-1, 15-2, 15-3,. Random access memory (RAM) that can be accessed.

  In the above configuration, the CPU 10 and the image processor 14 can access the system memory 13 via the system bus 11. While the system memory 13 is being accessed by the CPU 10, the system bus 11 is occupied by the CPU 10, and therefore the image processor cannot access the system memory 13. However, apart from the system bus 11, image memory buses 15-1, 15-2, 15-3,..., 15-n are provided, and image memories 16-1, 16-2, 16-3,. -N is connected, so that even during the period in which the system memory 13 is being accessed by the CPU 10, the image processing processor 14 can receive the image memories 16-1, 16-2, 16-3,. n can be accessed.

  FIG. 2 shows a configuration example of the image processor 14. The image processor 14 is not particularly limited, but is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

  As shown in FIG. 2, the image processor 14 is not particularly limited, but includes a camera interface 141, a data buffer controller (DB-CNT) 142, a system processor interface (SYSP) 143, a bus switch controller 144, a bus switch 145, A data buffer 146, an image processing circuit 147, and a display processing circuit 148 are included.

  The camera interface 141 can capture image data obtained by a monitoring camera (not shown). Image data captured via the camera interface 141 is temporarily stored in the data buffer 146 for buffering. The data buffer 146 includes a plurality of buffers DB1 to DBm corresponding to a camera interface, an image processing circuit, a display processing circuit, and the like.

  The image processing circuit 147 has a function of performing predetermined arithmetic processing on the image data taken in via the data buffer 146. The image-processed data is transmitted again to the display processing circuit 148 via the data buffer 146, or written to the image memories 16-1 to 16-n via the bus switch 145 as necessary.

  The display processing circuit 148 performs arithmetic processing for displaying the image data taken in via the data buffer 146 on a display device (not shown). The calculation processing result here is transmitted to a display device (not shown).

  The data buffer controller 142 controls the operation of the data buffer 148. The data buffer controller 142 also exchanges image data between the data buffer 146 and the image memories 16-1 to 16-n with respect to the bus switch controller 144. Request 16-n access. Memory access from the data buffer controller 142 is particularly DB access, and is distinguished from memory access from the CPU 10 (SYSP access).

  A system processor interface (SYSP) 143 is connected to the CPU 10 and the system memory 13 via the system bus 11 and enables exchange of signals with the CPU 10 and the system memory 13. Further, the system processor interface 143 includes a register Reg capable of holding setting information related to area division of the logical address space as will be described in detail later, and the logical address space of the memory can be divided and set in a programmable manner.

  The bus switch 145 switches the connection with a plurality of memory buses 15-1 to 15-n provided for each memory, thereby forming a data transfer path between the CPU 10 and the image memories 16-1 to 16-n. In addition, it is possible to form a data transfer path between the data buffer 146 and the memories 16-1 to 16-n. The bus switch 145 is not particularly limited, but switches 145-1, 145-2,..., 145-n provided corresponding to the memory buses 15-1 to 15-n are shown in FIG. The operation is controlled by a switching control signal from the bus switch controller 144. The system processor interface (SYSP) 143 and the data buffers DB1 to DBm are connected to all the switches 145-1 to 145-n. As a result, lower bits, strobe signals, data, and the like in the address signal transmitted from the system processor interface (SYSP) 143 and the data buffers DB1 to DBm are passed through any one of the switches 145-1 to 145-n to the image memory. 16-1 to 16-n. The upper bits in the address signal transmitted from the system processor interface (SYSP) 143 and the data buffers DB1 to DBm are used to generate selection signals for the switches 145-1 to 145-n. By switching the connection to the plurality of memory buses 15-1 to 15-n, memory access from the CPU 10 (SYSP access) and memory access from the data buffer controller 142 (DB access) can be executed simultaneously. it can. Further, when the read access (SYSP access) to the memory from the CPU 10 and the read access (DB access) to the memory from the data buffer controller 142 have the same address, the same data is transmitted to the CPU 10 and the data buffer 146. Can do.

  The bus switch controller 144 is not particularly limited. As shown in FIG. 3, the bus switch controller 144 determines an access conflict based on the physical address and an address conversion unit 1443 for converting the input logical address into a physical address. Address determining unit 1442 and an arbiter unit 1441 for arbitrating address conflict, and controls the operation of the bus switch 145.

  Next, area division of the logical address space will be described.

  A monitoring camera (not shown), a client such as the image processing circuit 147, and the CPU 10 are shown in FIG. 3B without being aware of a plurality of memory buses corresponding to the physical address map shown in FIG. The memory is accessed as a virtual linear space indicated by such a logical address map. As shown in FIG. 3C, this logical address space is divided into n areas for each predetermined number of words. These areas 1 to n are selected by the upper bits of the physical address. In the example shown in FIG. 3D, it is divided into three areas. The address determination circuit 1442 performs a conflict check for each area. The area division size is determined based on the area size information stored in the register Reg in the system processor interface 143. The area size information of the register Reg can be rewritten by the CPU 10. Therefore, the division size of the area can be set programmable. When handling a large image, the data size of the image may exceed the area size. In such a case, it is not possible for the address determination unit 1442 to make a correct conflict determination for a portion exceeding the area size. Therefore, by changing the area size according to the data size of the image to be handled, it is possible to prevent the image data size from exceeding the area size. The address determination unit 1442 determines whether the area for SYS access and the area for DB access match based on the physical address.

  Next, the switching operation by the bus switch 145 will be described.

  As shown in FIG. 5, examples of signals exchanged between the CPU 10 and the system processor interface 143 include an address signal, data, strobe signal, wait signal, bus request signal, and bus acknowledge signal. Examples of signals exchanged between the data buffer controller 142 and the bus switch controller 144 include an address signal, data, a strobe signal, a request signal, and an acknowledge signal.

  In memory access (SYSP access) by the CPU 10, an address signal and data are supplied from the CPU 10 to the system processor interface 143. In memory access (DB access) by the data buffer controller 142, the request signal is enabled by the data buffer controller 142, and the acknowledge signal is enabled by the bus switch controller 144 accordingly. An address signal and a strobe signal are supplied from 142 to the bus switch controller 144. At the operation timing shown in FIG. 6, 4 burst transfer is performed for SYS access, and block transfer of 128 bytes or 256 bytes is performed for DB access. When the address in the SYS access and the address in the DB access do not conflict, in other words, when the SYSP access and the DB access are performed on different areas, as shown in FIG. DB access is performed in parallel.

  Next, a case where the data buffer controller 142 tries to access an area being accessed by the CPU 10 as shown in FIG. 7 will be described. FIG. 8 shows the operation timing in that case. In this example, 4 burst transfers are performed for SYS access, and 128 or 256 byte block transfers are performed for DB access.

  When the data buffer controller 142 tries to access an area that is being accessed by the CPU 10, the address determination unit 1442 determines that the bus switch controller 144 sends a bus request signal to the CPU 10 via the system processor interface. Enable state (T1). In the CPU 10, the read strobe signal is disabled, the bus acknowledge signal is enabled accordingly (T 2), and is transmitted to the data buffer controller 142 (T 3), so that the data buffer controller 142 is controlled by the CPU 10. Detects the end of memory access. Thereafter, under the control of the bus switch controller 144, path switching is performed at the bus switch 145, and DB access is started.

  Next, as shown in FIG. 9, a case where the CPU 10 tries to access an area being accessed by the data buffer controller 142 will be described. FIG. 10 shows the operation timing in that case. In this example, 4 burst transfers are performed for SYS access, and 128 or 256 byte block transfers are performed for DB access.

  The request signal is enabled by the data buffer controller 142, and the acknowledge signal is enabled accordingly, thereby starting DB access (T4). When the CPU tries to access the area being accessed by the data buffer controller 142, the address determination unit 1442 determines that the wait signal for the CPU 10 is enabled (T5).

  The bus switch controller 144 requests a wait by enabling the wait signal to the CPU 10 via the system processor interface 143. When the memory access by the data buffer controller 142 is completed, the bus switch controller 144 disables the wait signal for the CPU 10 (T6). In response to this, the CPU 10 can start memory access.

  Next, simultaneous writing to the plurality of image memories 16-1 to 16n will be described.

  By the switching operation by the bus switch 145, each of the CPU 10 and the data buffers DB1 to DBm can be demultiplexed with respect to the plurality of image memories 16-1 to 16-n. For example, as shown in FIG. 11, the data buffer DB1 is connected to both the image memories 16-3 and 16-4 via the bus switch 145, so that the write access for the data A is executed only once. The same data A can be simultaneously written in both the image memories 16-3 and 16-4. This operation mode is referred to as “copy mode”. In this copy mode, the same data can be simultaneously written in any of the plurality of image memories 16-1 to 16n by the switching operation by the bus switch 145, and the image data to the image memories 16-1 to 16n can be written. The write access time can be shortened as compared with the case where writing is performed individually for each memory.

  As shown in FIG. 11, when the same data A is simultaneously written in both the image memories 16-3 and 16-4, the data A in the image memories 16-3 and 16-4 are simultaneously written. By reading in parallel, the calculation throughput can be improved. For example, as shown in FIG. 12, an access path from the data buffer DB1 to the image memory 16-3 and an access path from the data buffer DB2 to the image memory 16-4 are formed via the bus switch 145. The data buffers DB1 and DB2 can simultaneously obtain data A from the image memories 16-3 and 16-4, respectively. As a result, the image processing circuit 147 can perform the image processing for the data A in the data buffer DB1, and the display processing circuit 148 can perform the display processing for the data A in the data buffer DB2. In this way, different processes for the same data can be executed simultaneously, so that the calculation throughput can be improved.

  Further, as shown in FIG. 13, by forming an access path from the CPU 10 to the image memory 16-3 and an access path from the data buffer DB2 to the image memory 16-4 via the bus switch 145, the CPU 10 And the data buffer DB2 can simultaneously obtain data A from the image memories 16-3 and 16-4, respectively. In this case, the CPU 10 and the image processor 14 simultaneously execute different processes on the same data. Can do.

  According to the above example, the following operational effects can be obtained.

  (1) Since there are a plurality of memory buses 15-1 to 15-n provided for each individually accessible image memory, access to the image memories 16-1 to 16-n is supported. Since this can be done individually via the memory bus, the probability of memory access contention is reduced. As a result, the speed of image processing can be increased.

  (2) When handling a large image, the data size of the image may exceed the area size. In such a case, it is not possible for the address determination unit 1442 to make a correct conflict determination for a portion exceeding the area size. However, according to the above example, the area size can be set in a programmable manner by rewriting the register Reg. Therefore, by changing the area size according to the data size of the image to be handled, the data size of the image is changed to the area size. It is possible to avoid exceeding the size.

  (3) The bus switch 145 has a copy mode. In this copy mode, the same data can be simultaneously written in any of the plurality of image memories 16-1 to 16-n. The write access time can be shortened as compared with the case where the image data is written to 1-16-n individually for each memory.

  (4) According to the copy mode, data written to any of a plurality of image memories can be read simultaneously and in parallel, and can be subjected to different processes at the same time, so that the calculation throughput can be improved. .

  (5) Since no bus contention occurs between the access of the system memory 13 by the CPU 10 and the access of the image memories 16-1 to 16-n by the image processor 14, the access of the system memory 13 by the CPU 10 and the image processor 14 can access the image memories 16-1 to 16-n simultaneously in parallel.

  Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, the bus switch controller 144 can be configured as shown in FIG. The bus switch controller 144 shown in FIG. 14 is greatly different from that shown in FIG. 5 in that the same address determination unit 1444 is provided. The same address determination unit 1444 determines whether the address signal transmitted from the data buffer controller 142 matches the address signal transmitted from the CPU 10 via the system processor interface 143. When the same address determination unit 1444 determines that the address signal transmitted from the data buffer controller 142 matches the address signal transmitted from the CPU 10 via the system processor interface 143, the address is set to the address. Read data from the corresponding memory is transmitted to both the data buffer 146 and the CPU 10. FIG. 15 shows the operation timing in this case. Assume that a read access to the same image memory 16-1 occurs from the data buffer controller 142 and the CPU 10, respectively. In this case, access competition for the same area is performed in the address determination unit 1443, and it is determined in the same address determination circuit 1444 that the access is for the same address. Since access is to the same area, the bus switch controller 144 enables the wait signal for the CPU 10, thereby waiting for access by the CPU 10. During this time, memory access is performed by the data buffer controller 142, and 128-byte or 256-byte block transfer from the image memory 16-1 to the data buffer 146 is performed. At the same time as this block transfer, if the addresses transmitted from the data buffer controller 142 and the CPU 10 match, the same data is also transferred to the CPU 10. That is, when read access to the same image memory 16-1 occurs from the data buffer controller 142 and the CPU 10, the access of the CPU 10 is awaited, and the data read from the image memory 16-1 during that time is read. The data is transmitted to both the data buffer 146 and the CPU 10. As a result, the CPU 10 can quickly obtain the target data despite the fact that the wait signal is actually enabled and the memory access is waited.

  As described above, according to the configuration shown in FIG. 14, even when read access to the same image memory occurs from the data buffer controller 142 and the CPU 10, access contention between the data buffer controller 142 and the CPU 10 is avoided. . Similarly, there may be an access conflict between the data buffers DB1 to DBm for the same image memory. In such a case, such an access conflict is avoided. For example, when read access to the same image memory 16-1 occurs in order to transfer the stored data of the image memory 16-1 to a plurality of data buffers, the same address determination unit 1444 performs access determination for the same address. Based on this, the same data read from the image memory 16-1 is transferred to a plurality of data buffers, thereby avoiding access contention among the data buffers DB1 to DBm.

  In the above description, the case where the invention made mainly by the present inventor is applied to the image processor which is the field of use behind the invention has been described. However, the present invention is not limited to this and is widely applied to various processors. can do.

  The present invention can be applied on condition that data processing is performed.

1 is a block diagram illustrating a configuration example of an image processing system to which an image processor that is an example of a processor according to the present invention is applied. It is a block diagram of a configuration example of the image processor. It is a block diagram of a configuration example of a bus switch controller included in the image processing processor. It is explanatory drawing about the area division | segmentation of the logical address space managed in the said image processor. It is explanatory drawing about the signal exchanged in the said image processor. It is an operation | movement timing diagram of the principal part in the said image processor. It is operation | movement explanatory drawing of the bus switch in the said image processor. It is an operation | movement timing diagram of the principal part in the said image processor. It is operation | movement explanatory drawing of the bus switch in the said image processor. It is an operation | movement timing diagram of the principal part in the said image processor. It is operation | movement explanatory drawing of the bus switch in the said image processor. It is operation | movement explanatory drawing of the bus switch in the said image processor. It is operation | movement explanatory drawing of the bus switch in the said image processor. It is a block diagram of another example of a structure of the bus switch controller in the image processor. It is an operation | movement timing diagram of the principal part in the said image processor. It is a block diagram of a configuration example of a bus switch in the image processing processor.

Explanation of symbols

10 CPU
DESCRIPTION OF SYMBOLS 11 System bus 12 PCI bus 13 System memory 14 Image processor 15-1 to 15-n Memory bus 16-1 to 16-n Image memory 141 Camera interface 142 Data buffer controller 143 System processor interface 144 Bus switch controller 145 Bus switch 146 Data buffer 147 Image processing circuit 148 Display processing circuit 1441 Arbiter unit 1442 Address determination unit 1443 Address conversion unit 1444 Same address determination unit Reg registers DB1 to DBm Data buffer

Claims (5)

A processor including a system processor interface connectable to a central processing unit via a system bus, a data buffer capable of buffering data to be processed, and a data buffer controller capable of controlling the operation of the data buffer Because
By switching the connection with a plurality of memory buses provided for each individually accessible memory, a data transfer path between the central processing unit and the memory, and between the data buffer and the memory A bus switch capable of forming a data transfer path of
A bus switch controller capable of controlling the operation of the bus switch in response to a memory access request from the central processing unit or the data buffer controller. 2. The processor according to claim 1, further comprising a register capable of programmably dividing and setting the logical address space of the memory. 3. The processor according to claim 2, wherein the bus switch has a mode for simultaneously writing the same data to a plurality of memories. The bus switch reads from the central processing unit and the data buffer controller the first mode for simultaneously writing the same data to a plurality of memories and the storage data of the plurality of memories to which the same data is written. The processor according to claim 2, further comprising: a second mode that can be individually read according to access. The bus switch controller includes an identical address determination circuit capable of determining whether or not an address related to memory access from the central processing unit and an address related to memory access from the data buffer controller match. When the addresses match, based on the output of the same address determination circuit, the same data read from the memory by the memory access from the data buffer controller is stored in both the central processing unit and the data buffer. The processor of claim 2 being communicated.

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