JP2007108858A - Pin sharing device and pin sharing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of achieving sharing of an LSI pin without reducing the performance in a manner of sharing the LSI pin by connecting a device communicating through a different bus protocol to the common LSI pin and changing the bus protocol by time sharing. <P>SOLUTION: The device communicating through the different bus protocol is connected to the common LSI pin using a common bus formed in a substrate pattern, the inside of the LSI has a constitution allowing posted write by disposing a write buffer in a block connected to the internal bus, and the priority at which the bus arbiter permits the bus use right of the common bus is set so that the read access to the device connected to the common bus has higher priority than write access. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an LSI pin sharing method, and more particularly to a method for connecting devices communicating with a plurality of different bus protocols by sharing LSI pins.

  In recent years, the scale of a circuit that can be integrated into one LSI has been dramatically increased as the LSI manufacturing process has been miniaturized. The number of pins that can be mounted on a single LSI package to connect the LSI to a memory or other device is such as pad spacing on silicon, narrower package pin spacing, and multiple pins using surface mount packages. However, the increase in the number of pins has not caught up with the increase in circuit scale. As a result, there is a problem called pad limit where the silicon size of the LSI is determined not by the circuit scale but by the number of pads, and there is a problem that the utilization efficiency of silicon deteriorates. There is a problem that the area becomes large and the LSI mounting board area increases.

  For these problems, it is effective to reduce the number of pins of the LSI. In order to reduce the number of pins, conventionally, a parallel data bus in which a bus for address, data, etc. is defined and transferred by a plurality of pins is replaced with a serial bus and realized by several pins. For example, there is a technical trend to replace the PCI bus with a serial bus called PCI Express to achieve both high speed and a reduced number of pins.

  Further, an example is disclosed in which each CPU and a shared memory are connected to the memory control unit so that one memory can be shared by two CPUs, and the memory control unit arbitrates memory access from the two CPUs ( For example, see Patent Document 1).

A method has also been devised in which devices that communicate with different bus protocols are connected to a common LSI pin, and the bus protocol is switched in a time-sharing manner to share the LSI pins (for example, see Patent Document 2).
JP-A-6-301626 Japanese Patent Laid-Open No. 2002-278921

  When the parallel bus is replaced with a serial bus as in the conventional example, the number of pins can be reduced, but the device connected to the bus must also support the serial bus. There is a problem that it is not possible to use inexpensive conventional parallel bus interface devices that are widely spread in the market, and it is necessary to wait until a device having a serial bus interface having the same function is developed or to develop oneself. is there. There is also a method of using a bus conversion LSI (bus bridge) between an LSI mounted with a serial bus and a conventional parallel bus interface device, but considering the total system, in addition to the cost increase of the bus bridge LSI, the bus bridge There are disadvantages such as an increase in the area of a substrate on which an LSI is mounted and an increase in power consumption.

  As a method for sharing the parallel bus, the contents disclosed in Patent Document 1 will be described. As shown in FIG. 7, peripheral blocks 1 503 and 2 504 are connected to peripheral device buses of CPU 1 501 and CPU 2 502, and the buses 501 b and 502 b of each CPU are connected to the memory control unit 505. The CPUs are configured to be able to access the RAM 506 connected to the memory control unit 505 via the bus 505b.

  A control circuit that arbitrates access requests to the memory from the two CPUs is provided in the memory control unit 505, and operates so as to preferentially permit the memory access that has been accessed first.

  However, in the above-described conventional example, the two CPUs operate independently, but even if it is necessary to preferentially use memory access for a certain process, this conventional example cannot cope with it. For example, when the peripheral device 2 is communicating with an external device, even if there is a restriction that communication is interrupted if a response is not returned within a certain time, memory access from the CPU 1 side is executed first. There is a possibility that the peripheral device 2 cannot access the memory within a certain time, and communication is interrupted in the worst case.

  On the other hand, Patent Document 2 discloses an example in which devices communicating with different bus protocols are connected to a shared bus and the bus protocols are switched in a time division manner. In this example, when two CPUs, SCSI devices, and DMA devices having different bus protocols access the bus, the bus use right is arbitrated under the control of the interface arbitration circuit. The priority of the bus use right is lower in the CPU, and is set higher in the order of SCSI and DMA. When a low priority device is using the bus and a high priority device requests the bus use right, The bus access that is in use is interrupted, and a bus having a higher priority is used, and then the interrupted access is resumed.

  However, if priority is given by focusing only on the bus protocol as in Patent Document 2 described above, the performance of the entire system may be deteriorated. For example, when data processing is performed by the CPU, if data can be read quickly from the external memory, processing using the data can be started quickly. On the other hand, when writing the processed data to the external memory, the CPU proceeds to the next process without waiting until the data is actually written to the external memory when the writing process in the CPU is completed. In recent years, many CPUs support such a write operation and posted write. The same can be applied to LSI internal blocks other than the CPU, and there is no need to wait until the write data is written to the actual memory device. If the read data can be passed quickly, the processing performance of the entire system can be improved. . However, when an external device with a different protocol is connected to the shared bus and the bus use permission is given in the priority order according to the protocol described above, the read access of the protocol with the lower priority is the write access of the protocol with the higher priority. There is a drawback that the system is interrupted and the performance of the system is deteriorated.

  The present invention has been made in view of the above-described conventional example. In a system in which devices communicating with different bus protocols are connected to a common LSI pin, the bus protocol is switched in a time division manner, and the pins of the LSI are shared. It is an object of the present invention to provide a method that does not degrade the system performance by controlling the priority order for granting the usage right so that the read access is given priority over the write access.

  In order to solve such a problem, the pin sharing apparatus according to claim 1 of the present invention is an apparatus that connects pins operating on at least two different protocols by sharing pins of an LSI. Bus interface block 1 that operates, bus interface block 2 that operates according to protocol 2, shared pin, bus switching connection unit that switches between bus interface block 1 and bus interface block 2 and connects to the shared pin, and bus switching And a bus switching control unit for controlling the operation.

  In order to solve such a problem, the bus interface block of the pin sharing apparatus according to claim 2 of the present invention is provided with a write buffer capable of temporarily holding write data from other blocks in the LSI. .

  In order to solve such a problem, the bus interface block of the pin sharing apparatus according to claim 3 of the present invention includes a write buffer capable of temporarily holding write data from other blocks in the LSI. .

  In order to solve such a problem, the bus interface block of the pin sharing apparatus according to claim 4 of the present invention includes a write buffer capable of temporarily holding write data from other blocks in the LSI. .

  In order to solve such a problem, a pin sharing method according to claim 5 of the present invention is a method for connecting devices operating at least two different protocols by sharing pins of an LSI, Bus interface block 1 that operates, bus interface block 2 that operates according to protocol 2, shared pin, bus switching connection unit that switches between bus interface block 1 and bus interface block 2 and connects to the shared pin, and bus switching And a bus switching control unit that controls the bus switching so that a shared pin is used preferentially over a bus that operates according to a protocol with read access.

  In order to solve such a problem, the bus interface block in the pin sharing method according to claim 6 of the present invention comprises a write buffer capable of temporarily holding write data from other blocks in the LSI, and the state of the write buffer Can be notified to the bus switching control unit, and the bus switching control unit performs the bus switching so that the shared interface is used in preference to the bus interface block in which the write buffer is full.

  According to the present invention, devices that communicate with different bus protocols are connected to a common LSI pin, the bus protocol is switched in a time-sharing manner, and the priority order for permitting the right to use the bus is read. By controlling the access so that it is prioritized over the write access, it is possible to realize the system without degrading the system performance. Therefore, there is an effect that the number of pins, which is a valuable resource of the LSI, can be reduced and both performance and low cost can be realized.

Example 1
A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a system in which LSI pins are shared by buses operating with two different protocols. Reference numeral 101 denotes an LSI, and an SOC (System On a Chip) in which a CPU core is mounted in a chip is shown as an example. The LSI 101 includes a CPU 102, a memory controller 103, an internal bus master 104, a bus-1 master 105, a bus-2 master 106, a MUX 107, a shared IO pin 108, and a bus arbiter 109. Each block is connected to the internal bus of the LSI as shown. Has been. The LSI 101 has a memory 110 connected to n shared bus pins 108 and n bus-1 devices 1 operating according to the bus-1 protocol and m bus-2 devices operating according to the bus-2 protocol. Here, since the bus-1 device operates as a bus master, the bus usage right request signal and the bus usage right permission signal indicate that the bus arbiter 109 and each device are connected. On the other hand, the bus-2 device does not operate as a bus master, and the bus-2 is driven from the LSI 101.

  The CPU 102 operates according to the program and controls the operation of the LSI 101 and the system. The memory controller 103 is connected to the external memory 110 and performs data read / write control.

  The internal bus master 104 is, for example, a data compression / decompression function block or an image processing block. The internal bus master 104 serves as a bus master for the internal bus, and accesses the bus-1 device and the bus-2 device connected to the outside of the memory 110 and the LSI 101. .

  The bus-1 master 105 operates in accordance with the bus-1 protocol, and when the CPU102 and the internal busmaster 104 access the bus-1 device, the bus-1 becomes the bus-1 bus master and is connected to the external shared bus- Access one device. In addition, an internal write buffer is provided, and write data passed from the CPU 101 or the internal bus master 104 can be buffered. Increasing the capacity of the write buffer increases the performance because the write data that can be stored increases, but the circuit scale increases, so the capacity is determined by a trade-off between performance and scale. By providing the write buffer, the CPU 102 and the internal bus master 104 can perform posted write processing. As long as there is an empty space in the write buffer at the time of write operation, the write processing can be finished immediately and the next processing operation can be performed.

  On the other hand, when the bus-1 device connected to the external shared bus becomes the bus master and accesses the memory 110, a bus-1 slave block (not shown) in the LSI accepts bus access from the bus-1 device.

  The bus-2 bus master 106 operates in accordance with the bus-2 protocol. When the CPU 102 or the internal bus master 104 accesses the bus-2 device, the bus-2 becomes the bus-2 bus master and is connected to the external shared bus- 2 Access the device. Like the bus-1 bus master, a write buffer is provided inside, and write data passed from the CPU 101 or the internal bus master 104 can be buffered. Increasing the capacity of the write buffer increases the performance because the write data that can be stored increases, but the circuit scale increases, so the capacity is determined by a trade-off between performance and scale.

  The MUX 107 is a block that multiplexes and demultiplexes the bus-1 signal and the bus-2 signal. In accordance with a control signal from the bus arbiter 109, which bus is connected to the shared IO pin 108 is selected.

  The shared IO pin 108 is connected to the MUX 107, and is an IO pad and a pin that are shared and used by the bus-1 and bus-2. A substrate pattern is connected to the shared IO pin 104 on the substrate on which the LSI 101 is mounted, and a plurality of devices are connected to the same pattern.

  The bus arbiter 109 is a block that arbitrates the right to use the internal bus and the external shared bus. Connected to each of the LSI internal block and each of the bus-1 devices outside the LSI by the bus use right request signal and the bus use right grant signal, and either the internal block or the external device outputting the bus use right request signal On the other hand, a bus use right permission signal is output to permit use of the bus. Read access is given priority when deciding which device is granted the bus use permission. For the MUX 107 block, a signal for controlling which of the bus 1 and the bus 2 is valid is output.

  The external shared bus is connected to bus-1 devices 111, 113, and 115 that operate according to the bus-1 protocol, and each device operates as a bus master of the bus-1. Therefore, a bus usage right request signal line and a bus usage right are granted. The signal line 112, 114, 116 that represents the signal line as a single line is connected to the bus arbiter 109. In addition, bus-2 devices 117, 119, and 121 that operate using the bus-2 protocol are also connected to the external shared bus. Since 117, 119, and 121 are all bus slave devices of bus-2, they are not connected to the bus arbiter 109.

  Next, the flow of processing operations of the bus arbiter and the external shared bus of this embodiment will be described with reference to the flowchart of FIG.

  When the bus usage right permission device determination process of the bus arbiter 109 in FIG. 1 is started, whether there is an access request to the bus-2 device depends on whether the bus usage right request signal is asserted from the bus-2 bus master 106. Determine (S101). If there is an access request, the process proceeds to S102, and if not, the process proceeds to S110. In S102, it is determined whether the access to the bus-2 device is a read access. If it is read access, the process proceeds to S103, and if it is not read access, the process proceeds to S107. In S103, it is determined whether or not an access process to the bus-1 device is in progress. If the access process to the bus-1 device is being performed, the process proceeds to S104. If the access process is not being performed, the process proceeds to S109. S104 is a bus access interruption process for bus-1. In this embodiment, the priority of read access to bus-2 is higher than access to bus-1, so if there is a read access to bus-2 during the bus access of bus-1, this processing is performed. In (S104), the bus access of bus-1 is interrupted, and then the read access of bus-2 is started (S105). Before starting the access to the bus-2 device in S105, the bus arbiter 109 controls the MUX 108 to connect the external shared bus to the bus-2 master and gives the bus-2 master 106 the right to use the bus. When the bus-2 read access is completed, the bus arbiter changes the bus use right permission given to the bus-2 master 106 to non-permission, connects the MUX 107 to the bus-1, and the bus-1 master 105 or the external shared bus. The bus use is permitted to the device outputting the bus use right request signal of any one of the bus-1 devices 1 to n connected to the bus 1, and the bus access of the bus-1 suspended in S103 is resumed (S106).

  S107 is a process executed when the bus-2 access is not a read access, and is a process for setting the bus use permission prohibition setting of the bus-1 device. In this case, the use prohibition process is the bus-1 device (bus-1 master 108, bus-1 device 1 111, bus-1 device 2 113, bus-1 at the time of the next bus access after the bus access being executed is completed. The device n 117) is set not to permit the right to use the bus.

  S108 is a process for determining whether an access process to the bus-1 device is being executed. If it is being accessed, it waits for the current bus access to finish. When the bus access ends or when the bus access is not being executed, the process proceeds to S109.

  S109 is a bus-2 device access execution process. The bus-2 is permitted to use the bus, the external shared bus is switched to the bus-2, and the bus-2 device is accessed.

  In S110, when it is determined in S101 that there is no access request to the bus-2 device, it is determined whether there is an access request to the bus-1 device. If there is an access request, the process proceeds to S111 and the bus use of the bus-1 device is permitted. If there is no access request, the process ends.

  As described above, in this embodiment, an example using a bus arbiter in which the priority of read access to the bus-2 device is higher than the bus access to the bus-1 device is shown. If priority is given to read access to the bus-2 device to increase the processing efficiency of the entire system, it may be configured as in this embodiment.

(Example 2)
Next, in the second embodiment of the present invention, in addition to the first embodiment, the priority of read access processing to the bus-1 being executed is increased so that the read access being executed is not interrupted. This is the case.

  The processing operation of this embodiment is shown in FIG.

  In FIG. 2 of the first embodiment, if there is a read access of the bus-2 device during the access process to the bus-1 device in S103, the access of the lot-1 is interrupted in S104. As shown in S203, The read access of bus-2 is prioritized only during the write access to the bus-1 device. If the access being processed on the bus-1 is a write access in S102, the process proceeds to S204, where the bus-1 access processing is interrupted and the bus-2 read access is preferentially executed. In S203, if the bus-1 access is not a write access, the process proceeds to S208. If the bus-1 device access process ends, or if the bus-1 device access process is not in progress, the process proceeds to S209, where the bus-2 Bus access is permitted, the external shared bus is switched to bus-2, and the bus-2 device is accessed.

  As described above, in this embodiment, an example is shown in which a bus arbiter with an increased priority of read access to the bus-1 device and the bus-2 device is used. If the processing efficiency of the entire system is increased by equalizing the priority of read access to the bus-1 and bus-2 devices, the configuration of this embodiment may be used.

(Example 3)
Next, in addition to the first embodiment, the third embodiment of the present invention is configured such that the signal indicating the bus-2 is connected to the bus master 109 depending on the empty state of the write buffer in the bus-2 master 106. In addition to the read access of the bus-2 master 106, the bus arbiter 109 does not allow the write buffer of the CPU 102 or the internal bus master 104 to perform posted write because the write buffer has no free space. By increasing the priority of the write access to the same level as the read access of the bus-2 master, it is possible to suppress the performance degradation of the system due to the generation of the internal bus wait.

  The processing operation of this embodiment is shown in FIG.

  In FIG. 2 of the first embodiment, it is determined whether or not the read access to the bus-2 device is performed in S102. If the read access is not performed, the end of the bus access of the bus-1 is waited. In this way, a process for determining whether the write buffer of the bus-2 bus master 106 is full is added. If the write buffer is full, the process returns to S303, and the process is performed with the same priority as the read access to the bus-2 device. It is what I do.

  As described above, this embodiment increases the priority of read access to the bus-2 device over the bus access to the bus-1 device, and the write buffer of the bus-2 bus master becomes full. 2 shows an example using a bus arbiter that increases the priority of write access to two devices. If priority is given to read access to the bus-2 device and priority is given to eliminating the weight of write access, the processing efficiency of the entire system can be increased. In particular, this embodiment is effective when the capacity of the write buffer is increased and the influence on the circuit scale is increased.

Example 4
Next, the fourth embodiment of the present invention is a combination of the second embodiment and the third embodiment. That is, in addition to the second embodiment, a signal indicating the free state of the write buffer in the bus-2 master 106 is connected to the bus master 109, and the bus arbiter 109 performs the read access of the bus-2 master 106 and the write buffer. When there is no more free space and the write processing of the CPU 102 and the internal bus master 104 cannot be posted, the priority of the write access of the bus-2 master 106 is controlled to be as high as the read access of the bus-2 master. Therefore, it is possible to suppress a decrease in system performance due to generation of bus waits.

  The processing operation of this embodiment is shown in FIG.

  In FIG. 2 of the first embodiment, it is determined whether or not the read access to the bus-2 device is performed in S202. If the read access is not performed, the end of the bus access of the bus-1 is waited. In this way, a process for determining whether the write buffer of the bus-2 bus master 106 is full is added. If the write buffer is full, the process returns to S403, and the process is performed with the same priority as the read access to the bus-2 device. It is what I do.

  As described above, in this embodiment, when the priority of the read access to the bus-1 device and the bus-2 device is increased and the write buffer of the bus-2 bus master is full, the bus-2 device is transferred to the bus-2 device. An example using a bus arbiter that increases the priority of write access is shown. If the overall processing efficiency of the system is increased by giving priority to the priority of read access to the bus-1 and bus-2 devices and giving priority to eliminating the weight of write access to the bus-2 device, What is necessary is just to comprise like an Example. This is particularly effective when the capacity of the write buffer is increased and the influence on the circuit scale is increased.

(Example 5)
Next, as another embodiment, a block diagram of a configuration in the case where the bus-2 device connected to the external shared bus can operate as a bus master is shown in FIG. 1 differs from FIG. 1 in that the bus-2 device 1 218, the bus-2 device 2 219, and the bus-2 device m 221 connected to the external shared bus operate as bus masters. In other words, the bus arbiter 209 is connected by signal lines 218, 220, and 222, which represent the line and the bus use right permission signal line as a single line.

  When devices operating as bus masters are connected to both bus-1 and bus-2 as in the present embodiment, basically the same processing as in the above-described embodiment may be performed.

1 is a block diagram illustrating a system and an internal configuration of an LSI constituting the system in an embodiment of the present invention. 3 is a flowchart showing processing operations of the bus arbiter and the external shared bus in the first embodiment of the present invention. It is a flowchart which shows the processing operation of the bus arbiter and external shared bus in 2nd Example of this invention. It is a flowchart which shows the processing operation of the bus arbiter and external shared bus in the 3rd Example of this invention. It is a flowchart which shows the processing operation of the bus arbiter and external shared bus in the 4th Example of this invention. It is a block diagram which shows the internal structure of LSI which comprises the system in the other Example of this invention, and a system. It is a block diagram which shows the system configuration | structure of a prior art example.

Explanation of symbols

101 LSI
102 CPU
103 Memory Controller 104 Internal Bus Master 105 Bus-1 Master 106 Bus-2 Master 107 MUX
108 Shared IO pin 109 Bus arbiter 110 Memory 111 Bus-1 device 1
112 Bus use right request signal and bus use permission signal of bus-1 device 1 113 Bus-1 device2
114 Bus-1 device 2 bus use right request signal and bus use permission signal 115 Bus-1 device n
116 Bus-1 device n bus use right request signal and bus use permission signal 117 Bus-2 device 1
118 Bus-2 Device 2
119 Bus-2 device m

Claims (6)

A device that shares pins of an LSI and connects devices operating at least two different protocols;
Bus interface block 1 that operates with protocol 1, bus interface block 2 that operates with protocol 2, shared pin, bus switching block that switches between bus interface block 1 and bus interface block 2 and connects to the shared pin and bus switching A pin sharing apparatus comprising: a bus switching control unit to control.   2. The pin sharing apparatus according to claim 1, wherein the bus switching control unit performs bus switching control so that a shared pin is used in preference to a bus that operates according to a protocol that has undergone read access.   3. The pin sharing apparatus according to claim 1, wherein the bus interface block includes a write buffer capable of temporarily holding write data from other blocks in the LSI.   The bus interface block can notify the bus switching control unit of the state of the write buffer, and the bus switching control unit switches the bus so that the shared interface is used in preference to the bus interface block in which the write buffer is full. The pin sharing apparatus according to claim 1, wherein the pin sharing apparatus is a pin sharing apparatus. A method of connecting devices operating on at least two different protocols by sharing LSI pins,
Bus interface block 1 that operates with protocol 1, bus interface block 2 that operates with protocol 2, shared pin, bus switching block that switches between bus interface block 1 and bus interface block 2 and connects to the shared pin and bus switching A pin sharing method comprising: a bus switching control unit for controlling, and performing bus switching control so that a shared pin is used in preference to a bus operating with a protocol having read access.   The bus interface block includes a write buffer that can temporarily hold write data from other blocks in the LSI, and can notify the bus switching control unit of the state of the write buffer. The bus switching control unit has a full write buffer. 6. The pin sharing method according to claim 5, wherein bus switching is performed so that a shared pin is used preferentially for a bus interface block in a state.

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