JP4071225B2 - Transfer circuit - Google Patents

Description

  The present invention relates to a transfer circuit capable of transferring data in a rectangular area between memories having different memory configurations without giving an instruction for each data transfer and for each line.

  2. Description of the Related Art Conventionally, in image processing and image display in information processing apparatuses, screen data is widely transferred between a main memory and another memory (for example, a buffer or a video memory).

  For example, in Patent Document 1 described later, as shown in FIG. 19, a plurality of buffers 515 accessible by one-dimensional addresses are provided as work areas, and the ALU 511 accesses the image data in the buffer 515 (1). Thus, an information processing apparatus is disclosed in which the DMAC 516 brings the image data of the main memory 502 to the other buffer 515 (2) while performing processing such as filtering. Further, when processing such as filtering on the image data in the buffer 515 (1) is completed, the information processing apparatus stores the image data in the buffer 515 (1) after the processing in the main memory 502 by the operation of the DMAC 516. Simultaneously with this storage, the ALU 511 can perform image processing on the buffer 515 (2). That is, data processing and data transfer can be performed in parallel.

In the information processing apparatus, when image data in the main memory 502 is transferred to one of the buffers 515, the following processing is performed. That is, based on the program data in the main memory 502, the ALU 511 generates a two-dimensional address and supplies it to the DMAC 516. An address conversion circuit 661 in the DMAC 516 converts the two-dimensional address into a one-dimensional address for accessing the image data in the main memory 502 and supplies the converted data to the main memory 502. The image data read from the main memory 502 is given to the buffer 515. The ALU 511 generates a two-dimensional address for storing the image data in the buffer 515 based on the program data, and gives it to the address conversion circuit 514. The address conversion circuit 514 converts the image data into a one-dimensional address, gives it to the buffer 515, and stores the image data from the main memory 502.
Japanese Patent Laid-Open No. 6-231035 (Publication date: August 19, 1994)

  However, in the above conventional configuration, the ALU generates an address every time data is transferred, which increases the burden on the ALU. In particular, in a general-purpose computer or the like in which the CPU designates data to be transferred, if the CPU tries to perform this processing, it not only increases the burden on the CPU but also fails to meet the memory transfer speed, Data transfer speed will decrease. Furthermore, in the above conventional configuration, data is continuously stored in the buffer, and cannot be transferred to a memory having another memory configuration (another data storage method).

  The present invention has been made in view of the above problems, and an object thereof is to realize a transfer circuit capable of transferring data in an arbitrary rectangular area at high speed between memories having different memory configurations. It is in.

  In order to solve the above problems, a transfer circuit according to the present invention includes a transfer source address difference register for storing address difference information indicating a difference between start addresses between adjacent lines and a transfer destination memory in the transfer source memory. And a transfer destination address difference register for storing address difference information indicating a difference between start addresses between adjacent lines, and from an address specified by the transfer source memory to an address specified by the transfer destination memory. A transfer processing circuit for transferring data, a transfer source address calculating circuit for calculating an address of a transfer source memory to be next transferred for each data transfer by the transfer processing circuit, and instructing the transfer processing circuit; Each time data is transferred by the transfer processing circuit, the address of the transfer destination memory to which data is to be transferred next is calculated and the transfer destination address for instructing the transfer processing circuit is calculated. A calculation circuit; and a determination circuit for determining whether or not the transfer of the rectangular area in the current line is completed for each data transfer by the transfer processing circuit, and each of the address calculation circuits includes the determination circuit of the current line. If it is determined that the transfer of the rectangular area has been completed, the address difference information stored in the address difference register corresponding to each of the address difference registers is referred to, and the start address in the next line of the rectangular area is determined. It is characterized in that it is calculated and output as an address to be transferred next. Examples of the line include a horizontal line and a vertical line.

  In the above configuration, each address calculation circuit calculates the start address of the next line by referring to the respective address difference information when the determination circuit determines that the transfer of the rectangular area of the current line is completed. Is output as an address to which data is to be transferred. Therefore, unlike the configuration instructed by an external circuit (for example, a CPU) provided outside the transfer circuit for each line constituting the rectangular area and for each data transfer by the data processing unit, the transfer circuit includes: The rectangular area data can be transferred from the transfer source memory to the transfer destination memory without any problem. As a result, it is possible to prevent the overhead caused by the external circuit instructing the transfer circuit for each line or each data transfer.

  In addition, since the transfer source address difference register and the transfer destination address difference register are provided separately, by setting a value in each register in advance, the memory configuration of the transfer source (the start address between adjacent lines) Data in an arbitrary rectangular area can be transferred from a transfer source memory having a different difference) to a transfer destination memory.

  As a result, a transfer circuit capable of transferring data in an arbitrary rectangular area at high speed between memories having different memory configurations can be realized. In particular, if each register can be set from the external circuit, even if the memory configuration changes during operation and the start address difference between adjacent lines changes, the value of each address difference register is changed. By appropriately resetting, the transfer circuit can transfer data in an arbitrary rectangular area at high speed without any trouble.

  Further, in addition to the above configuration, the transfer processing circuit may collectively transfer data at a plurality of addresses in at least one of the transfer source memory and the transfer destination memory. An example of the batch transfer method is burst transfer.

  In the above configuration, since the transfer processing circuit collectively transfers data at a plurality of addresses, the number of times the transfer processing circuit designates an address in the memory can be reduced as compared with a configuration in which data is transferred for each address. Therefore, it is possible to realize a transfer circuit that can transfer data at a higher speed than a configuration in which data is transferred for each address.

  Further, in addition to the above configuration, the transfer processing circuit may be capable of transferring data from the transfer source memory to the transfer destination memory. In the above configuration, data can be transferred from the transfer source memory to the transfer destination memory. Therefore, for example, although it is basically configured to transfer data from the main memory to the video memory, data written by a circuit that directly writes data to the video memory, such as a video capture circuit, is transferred to the main memory, The data can also be used for applications that are referred to by an external circuit.

  According to the present invention, a transfer circuit capable of transferring data in an arbitrary rectangular area at high speed between memories having different memory configurations can be realized. For example, data transfer between a main memory and a video memory can be performed. First, it can be used widely and suitably as a transfer circuit for transferring data between various memories.

[First Embodiment]
An embodiment of the present invention will be described below with reference to FIGS. That is, the information processing apparatus 1 according to the present embodiment is an apparatus that can transfer data in an arbitrary rectangular area of an image at high speed between memories that store image data using a plurality of different storage methods. As shown in FIG. 2, a main memory 2 and a video memory 3 are provided as memories for storing the image data.

The video memory 3 is referred to by the graphic controller 4 to generate a video signal to be output to the display device 5, and can read data of each pixel at high speed with a relatively small circuit. Therefore, for example, as shown in FIG. 3, the data of each line of the image is arranged so that the difference between the start addresses of the data of two adjacent lines can be expressed by 2 ⁿ . If the data of each line is arranged in this way, depending on the pixel resolution (number of pixels), the address (start address of the next line) storing the data of the first pixel of the next line is the end of a certain line. However, in this case, the storage area from the address next to the address (end address) to immediately before the start address of the next line is not used.

For example, FIG. 3 shows a state where an image having a horizontal resolution of 800 pixels is stored in the video memory 3. In FIG. 3, the data of each line is arranged so that the difference between the start addresses of the data of two adjacent lines can be represented by 2 ¹⁰ , and one pixel (one address storage area) corresponds to one pixel. The case where the data of this is stored is illustrated. Accordingly, image data for a certain horizontal line is stored in A001h to A320h of the video memory 3, and image data for the next horizontal line is stored in A401h to A720h.

  In this configuration, when calculating the start address of the next line of the reference line, the next higher bit is incremented and the remaining lower bits of the reference line start address are concatenated. The start address of the line can be calculated. Therefore, when the graphic controller 4 outputs a video signal indicating the luminance of each pixel of the image every predetermined cycle (for example, every one frame period), it is a case where high-speed access is necessary. However, the graphic controller 4 can be realized with a relatively small circuit.

  On the other hand, the main memory 2 according to the present embodiment is a memory that is mainly accessed by the CPU 6 of the information processing apparatus 1. As shown in FIG. 4, image data of a certain horizontal line is stored in the previous horizontal line. It is stored at an address continuous to the address where the image data is stored.

  For example, FIG. 4 exemplifies the case where the horizontal resolution is 800 pixels and the data of one pixel is expressed by one word, as in FIG. 3. Is stored in A001h to A320h of the main memory 2, and the image data for the next horizontal line is stored in A321h to A640h.

  Further, as shown in FIG. 2, the information processing apparatus 1 according to the present embodiment includes a transfer circuit 11 that can access both the main memory 2 and the video memory 3. In accordance with an instruction from an external circuit such as the CPU 6, the data of the designated rectangular area A (see FIG. 5) in the image is transferred from the main memory 2 to the video memory 3 or from the video memory 3 to the main memory 2. Can do.

  The transfer circuit 11 according to the present embodiment, as a transfer instruction in advance, has a rectangular area width (number of pixels) and height (number of lines), a start address in the transfer source memory, and each line in the transfer source memory. The start address difference, the start address in the transfer destination memory, and the start address difference of each line in the transfer destination memory are received, and it is not necessary to receive a transfer instruction for each horizontal line constituting the rectangular area. For each horizontal line constituting the rectangular area, the following processing, that is, calculation processing of the start address of the line in both the transfer source memory and the transfer destination memory, and transfer processing of the data of each pixel constituting the line Can be repeated. As a result, the transfer circuit 11 receives a transfer instruction for each horizontal line constituting the rectangular area regardless of the position and size of the rectangular area and the difference in the start address of each line in the transfer source and transfer destination memories. The data in the rectangular area can be transferred without any problem.

  Specifically, as shown in FIG. 1, the transfer circuit 11 according to the present embodiment includes width and height registers 21 and 22 for storing the width (number of pixels) and height (number of lines) of a rectangular area, respectively. The difference between the start address of the rectangular area in the main memory 2 and the start address of the adjacent horizontal line in the main memory 2 is stored, and the start address and address difference registers 23 and 24, respectively, There are provided start address and address difference registers 25 and 26 for storing the start address and the difference between the start addresses of adjacent horizontal lines in the video memory 3, respectively. The address difference registers 24 and 26 correspond to the transfer source and transfer destination address difference registers described in the claims.

  Here, the value (starting address of the rectangular area) stored in each of the starting address registers 23 and 25 is the starting address of the entire data transfer in the rectangular area in the main memory 2 and the video memory 3, and this embodiment Then, as an example, since data transfer is started with the upper left corner of the rectangular area as a base point, the start address of the rectangular area is an address in which the data of the upper left pixel of the rectangular area is stored.

  Furthermore, the transfer circuit 11 includes a transfer processing unit (transfer processing circuit) 31 that performs data transfer between the specified address of the main memory 2 and the specified address of the video memory 3, and the width and height. Each time the data transfer by the transfer processing unit 31 is completed with reference to the values of the registers 21 and 22, the pixel is located at the end of the rectangular area (in this example, in the horizontal line where the pixel to be transferred is located). , Right end) and whether or not the data transfer of the entire rectangular area is completed, and the determination result is output as the control signal S1, and it is determined that the data transfer of the rectangular area is not completed. In this case, the transfer control unit (determination circuit) 32 instructing the transfer processing unit 31 to transfer the next data, and the values stored in the start address and address difference registers 23 and 24 and the Whether the area transfer (BitBlt) has been instructed, and whether the control signal S1 and the control signal S5 from the transfer processing unit 31 indicate the end of reading from the transfer source memory (in this case, the main memory 2). The main memory 2 calculates a next data transfer address in the main memory 2 and outputs an address signal A1 indicating the address to the transfer processing unit 31. Based on the start address and the value stored in the address difference registers 25 and 26, whether or not the transfer of the rectangular area is instructed, and the control signal S1, the address for the next data transfer in the video memory 3 is calculated. And a video memory address calculation unit that outputs an address signal A2 indicating the address to the transfer processing unit 31. And a transfer destination address calculating circuit) 34.

  The address calculation units 33 and 34 may directly receive a rectangular area transfer start instruction. However, in this embodiment, the transfer control unit 32 receives the rectangular area transfer start instruction and receives a control signal S2. To the address calculation units 33 and 34. Further, the transfer control unit 32 may notify the transfer instruction to the transfer control unit 32 via each of the address calculation units 33 and 34. However, in this embodiment, the transfer control unit 32 uses the transfer processing unit. Data transfer is instructed by a control signal S3 to 31. Further, the transfer control unit 32 monitors the input / output signal of the transfer processing unit 31 or determines whether or not a predetermined time has elapsed, and the data transfer by the transfer processing unit 31 is completed. In this embodiment, every time data transfer ends, the transfer processing unit 31 outputs a control signal S4 indicating transfer end, and the transfer control unit 32 performs the control. Based on the signal S4, it is detected whether or not the data transfer by the transfer processing unit 31 is completed. In the present embodiment, a control unit 43 described later generates control signals S2 and S3.

  As shown in FIG. 6, the transfer control unit 32 includes a width counter 41 for storing the number of pixels transferred so far in the horizontal line (current horizontal line) where the pixel to be transferred is located, The line number counter 42 for storing the number of horizontal lines transferred to the counter, the count values of the counters 41 and 42, the control indicating whether or not the data transfer of the rectangular area is instructed, and the data transfer by the transfer processing unit 31 Based on a signal indicating the completion (in this example, the control signal S4), the control signal S1 is generated and the counters 41 and 42 are controlled each time the data transfer by the transfer processing unit 31 is completed. And a control unit 43.

  The control unit 43 can reset the counters 41 and 42 when, for example, an external circuit such as the CPU 6 instructs data transfer in a rectangular area. Each time the control unit 43 receives the control signal S4, the control unit 43 compares the count values of the counters 41 and 42 with the values of the registers 21 and 22, respectively, and ends the rectangular area on the current horizontal line. A control signal S1 indicating whether or not the data transfer of the entire rectangular area has been completed can be generated.

  Further, when the control unit 43 determines that the end has not been reached, the control unit 43 increments the count value of the width counter 41 by the number of pixels to which data has been transferred. 41 can be reset. In this embodiment, since the transfer processing unit 31 transfers data pixel by pixel, the control unit 43 increments the width counter 41 by one.

  The control unit 43 can increment the count value of the line number counter 42 by 1 when determining that the end has been reached and determining that the data transfer of the entire rectangular area has not ended.

  On the other hand, as shown in FIG. 7, the main memory address calculation unit 33 includes a line start address register 51 for storing an address (line start address) of the start end (left end in this example) of the rectangular area in the current horizontal line; The address (current address) in the main memory 2 of the pixel to be transferred is stored, and the current address counter 52 that outputs the stored address as the address signal A1, the members 51 and 52, and the registers 23 and The control unit 53 controls the members 51 and 52 based on the value 24, the control signals S1 and S2 from the transfer control unit 32, and the control signal S5 from the transfer processing unit 31.

  The control unit 53 can store the value of the start address 23 in the line start address register 51 and the current address counter 52 when the transfer of the rectangular area is instructed by the control signal S2.

  When the control signal S1 reaches the end of the current horizontal line and indicates that the transfer of the rectangular area is not completed, the control unit 53 is stored in the line start address register 51. The incremented value can be increased by the value stored in the address difference register 24, and the increased value can be stored in the current address counter 52.

  Further, when the control signal S5 from the transfer processing unit 31 indicates the end of reading from the transfer source memory (in this case, the main memory 2), the control unit 53 counts the count value of the current address counter 52. Can be incremented by the amount of the data transferred by the transfer processing unit 31. In the present embodiment, since the transfer processing unit 31 transfers data by one address of the main memory 2, the control unit 53 increments the count value of the current address counter 52 by one.

  Since the current address counter 52 only needs to be incremented every time data is transferred by the transfer processing unit 31, the control unit 53 does not refer to the control signal S5 from the transfer processing unit 31 and from the transfer control unit 32. The current address counter 52 may be incremented when the control signal S1 indicates that the end of the line has not been reached and transfer of the entire rectangular area has not been completed. However, in this embodiment, in order to ensure a longer operating time of the current address counter 52, the transfer processing unit 31 outputs a control signal S5 indicating the end of reading from the main memory 2 serving as the transfer source, and the control unit 53 Is incrementing the current address counter 52 when the control signal S5 becomes true.

  Similarly, as shown in FIG. 8, the video memory address calculation unit 34 stores the line start address register 61 for storing the line start address of the current horizontal line and the current address in the video memory 3 as well as stored. Based on the current address counter 62 that outputs the address as the address signal A2, the values of the members 61 and 62 and the registers 25 and 26, and the control signals S1 and S2 from the transfer control unit 32, And a control unit 63 that controls the members 61 and 62.

  The control unit 63 can store the value of the start address 25 in the line start address register 61 and the current address counter 62 when the transfer of the rectangular area is instructed by the control signal S2.

  When the control signal S1 reaches the end of the current horizontal line and indicates that the transfer of the rectangular area is not completed, the control unit 63 is stored in the line start address register 61. The incremented value can be increased by the value stored in the address difference register 26, and the increased value can be stored in the current address counter 62.

  Further, when the control signal S1 from the transfer control unit 32 indicates that the end of the line has not been reached and the transfer of the entire rectangular area has not been completed, the control unit 63 determines that the current address counter 62 The count value can be incremented by the address of the data transferred by the transfer processing unit 31. In this embodiment, since the transfer processing unit 31 transfers data for each address of the video memory 3, the control unit 63 increments the count value of the current address counter 62 by one.

  In the above configuration, the CPU 6 stores the width and height of the rectangular area in the width and height registers 21 and 22 prior to transfer of the rectangular area. Further, the CPU 6 stores the start addresses of the rectangular areas in the main memory 2 and the video memory 3 in the start address registers 23 and 25 prior to the transfer of the rectangular areas. The values of the address difference registers 24 and 26 may be predetermined fixed values. In this embodiment, the CPU 6 stores the memory of the main memory 2 and the video memory 3 prior to the transfer of the rectangular area. The values of the address difference registers 24 and 26 are set according to the map.

  When a value is set in each of the registers 21 to 26 and the CPU 6 instructs the start of data transfer in the rectangular area, the transfer control unit 32 controls each address calculation unit 33 and 34 to indicate that the transfer start is instructed. S2 is output. In response to this, the address calculation units 33 and 34 output address signals A1 and A2 indicating the values of the start addresses 23 and 25, respectively, as addresses to which data is transferred next.

  Furthermore, the transfer processing unit 31 reads out data stored in the address indicated by the address signal A1 from the main memory address calculation unit 33 in the main memory 2 in response to the control signal S3 from the transfer control unit 32, and When the reading is completed, a control signal S5 indicating the completion of reading is output to the main memory address calculation unit 33. In addition, the transfer processing unit 31 writes the read data to the address indicated by the address signal A2 from the video memory address calculation unit 34 in the video memory 3, and when the writing is completed, the transfer processing unit 31 indicates that the writing is completed. The signal S4 is output to the transfer control unit 32.

  On the other hand, when it is detected by the control signal S4 from the transfer processing unit 31 that the transfer processing unit 31 has output the data transfer, the transfer control unit 32 determines whether the end of the current horizontal line has been reached or not. A control signal S1 indicating whether or not the data transfer is completed is output.

  Here, even if the transfer processing unit 31 transfers data, if the end of the current horizontal line is not reached, the transfer control unit 32 determines that the end has not been reached each time the transfer processing unit 31 transfers data. Then, the control signal S1 indicating that the transfer of the entire rectangular area is not completed is output.

  Therefore, each time the transfer processing unit 31 transfers data, each address calculation unit 33 and 34 performs the following processing, that is, the address of each memory 2 and 3 by the amount of the address that the transferred data occupies in each memory 2 and 3. Repeat the process of changing the current address.

  Here, current address counters 52 and 62 are provided corresponding to the main memory 2 and the video memory 3, respectively. 3 is set according to the address occupied by 3. Therefore, the data structure (memory configuration; for example, the number of addresses occupied by data indicating each pixel in the main memory 2) and the pixel data are stored in the video memory 3 when the pixel data is stored in the main memory 2. Although the data structures used for storage are different from each other, and the transfer processing unit 31 has not received an instruction from the CPU 6 for each data transfer, the transfer processing unit 31 does not have any problem and does not have any trouble. Data can be transferred from the main memory 2 to the video memory 3.

  When data transfer related to the current horizontal line is repeated and the end of the current horizontal line is reached, the transfer control unit 32 outputs a control signal S1 indicating arrival at the end.

  In this case, each of the address calculation units 33 and 34 refers to the corresponding address difference registers 24 and 26 to determine the line start address of the next horizontal line, and address signal A1 indicating each line start address.・ Output A2.

  Here, as described above, in the transfer circuit 11 according to the present embodiment, the address difference register 26 and the line corresponding to the video memory 3 are separated from the address difference register 24 and the line start address register 51 corresponding to the main memory 2. A start address register 61 is provided. Therefore, a data structure for storing pixel data in the main memory 2 (memory configuration; for example, a difference between start addresses of adjacent horizontal lines) and a data structure for storing pixel data in the video memory 3 Are different from each other, and even though the transfer processing unit 31 does not receive an instruction from the CPU 6 for each data transfer of each horizontal line, the transfer processing unit 31 transfers the data of each pixel without any trouble. The video data can be transferred from the main memory 2 to the video memory 3.

  The data transfer of each horizontal line is repeated until the horizontal line corresponding to the height of the rectangular area is transferred, and when the data transfer of the horizontal line corresponding to the height of the rectangular area is completed, the transfer control unit 32, for example, The CPU 6 is notified of the completion of the data transfer of the entire rectangular area by, for example, outputting to the CPU 6 a control signal indicating that the data transfer of the entire rectangular area has been completed.

  As described above, in the transfer circuit 11 according to the present embodiment, the address difference register 26 corresponding to the video memory 3, in addition to the address difference register 24 corresponding to the main memory 2, the line start address register 51, and the current address counter 52, Since the line start address register 61 and the current address counter 62 are provided, the data structures for storing pixel data in the memories 2 and 3 are different from each other, and the data transfer of the rectangular area is started. The data of the pixels in an arbitrary rectangular area can be transferred between the main memory 2 and the video memory 3 even though the CPU 6 has not instructed the transfer circuit 11 between the main memory 2 and the video memory 3. Therefore, the burden on the CPU 6 can be reduced.

  Further, for example, unlike the configuration in which the CPU 6 instructs the transfer circuit 11 at the time when the data in the rectangular area is being transferred, such as the end time of each horizontal line, the overhead caused by the CPU 6 instructing the transfer circuit 11 is generated. Can be prevented. As a result, data in an arbitrary rectangular area can be transferred at high speed between the memories 2 and 3 having different memory configurations.

  In addition, in the transfer circuit 11 according to the present embodiment, the address difference registers 24 and 26 are configured such that values can be set from the CPU 6. Therefore, even when the memory configuration changes and the start address difference between the adjacent horizontal lines changes, the transfer circuit 11 does not have any trouble by setting the values of the registers 24 and 26 appropriately. The data in an arbitrary rectangular area can be transferred at high speed.

  Hereinafter, a detailed circuit configuration example of each member 31 to 34 of the transfer circuit 11 will be described with reference to FIGS. 9 to 12.

  That is, in the configuration example shown in FIG. 9, the main memory 2 and the video memory 3 are realized by a DRAM (Dynamic Randam Access Memory), and the transfer processing unit 31 includes a DRAM controller 101 for controlling each reading and writing. And a buffer 103 that latches the data output to the data terminal of the main memory 2 and outputs the data to the data terminal of the video memory 3, and the DRAM until the buffer 103 latches the data output from the main memory 2 The controller 102 includes a timing control circuit 104 that delays writing data in the buffer 103 to the video memory 3.

  In addition, the transfer circuit 11 according to this configuration example does not continue to occupy the right to access the main memory 2 and the video memory 3 during the transfer of the rectangular area. When accessing the video data, even during the data transfer of the rectangular area, the data transfer is interrupted and access to the main memory 2 or the video memory 3 is permitted at an appropriate timing.

  Specifically, the transfer processing unit 31 arbitrates an access right to the main memory 2, and the control signal REQ1_OK from the arbitration circuit 111 gives the transfer circuit 11 an access right (rectangular shape). The address signal A1 from the main memory address calculation unit 33 is selected while the data transfer of the area is permitted), and the address signal from the external bus is selected during the remainder, And a multiplexer 112 that outputs the selected one to the address terminal of the DRAM controller 101. Further, the transfer processing unit 31 is arranged between the external bus and the data terminal of the main memory 2 and passes data only while the write control signal Write_L to the DRAM controller 101 instructs reading. The control signal REQ1_OK from the arbitration circuit 111 indicates that the access right is not given to the transfer circuit 11, and the control signal from the external bus instructs the writing. A logic circuit 114 is provided that outputs a write control signal Write_L instructing writing to the DRAM controller 101 only in the case of remaining data, and outputs a write control signal Write_L instructing reading in the remaining case. In this embodiment, when the access right is given to the transfer circuit 11, the control signal REQ1_OK is true, and when the external control signal and the write control signal Write_L are false, it means reading. Therefore, the logic circuit 114 is realized by an OR element.

  In addition, the transfer circuit 11 according to this configuration example does not continue to occupy the right to access the main memory 2 and the video memory 3 during the transfer of the rectangular area. When accessing the video data, even during the data transfer of the rectangular area, the data transfer is interrupted and access to the main memory 2 or the video memory 3 is permitted at an appropriate timing.

  Similarly, the transfer processing unit 31 arbitrates an access right to the video memory 3, and the control signal REQ1_OK from the arbitration circuit 121 gives the transfer circuit 11 an access right (in the rectangular area). The address signal A2 from the video memory address calculation unit 34 is selected while the data transfer is permitted), and the address signal from the external bus is selected and selected during the remainder. And a multiplexer 122 that outputs the signal to the address terminal of the DRAM controller 102. Further, the transfer processing unit 31 is arranged between the external bus and the data terminal of the video memory 3 and passes data only while the write control signal Write_L to the DRAM controller 102 instructs reading. The control signal REQ1_OK from the arbitration circuit 121 indicates that the right to access the transfer circuit 11 is not given, and the control signal from the external bus instructs reading. A logic circuit 124 is provided that outputs a write control signal Write_L for instructing reading to the DRAM controller 102 only in the case of remaining data, and outputs a write control signal Write_L for instructing writing in the remaining case.

  In this embodiment, when the access right is given to the transfer circuit 11, the control signal REQ1_OK is true, and when the external control signal and the write control signal Write_L are false, it means reading. An external control signal is inverted by an inverter and then applied to the logic circuit 124. Therefore, the logic circuit 124 is realized by a NOR element.

  Further, while the control signal REQ1_OK from the arbitration circuit 121 indicates that the transfer circuit 11 is given access right, the transfer processing unit 31 selects the data signal from the buffer 103 and stores the remainder. In addition, a multiplexer 125 is provided for selecting a data signal from the external bus and outputting the selected signal to the three-state buffer 123.

  Further, the timing control circuit 104 according to the present configuration example generates REQ1 indicating whether or not there is an access right request to the transfer circuit 11 by inverting and delaying the control signal REQ1_OK from the arbitration circuit 111, and the arbitration circuit 121. Is applied.

  Further, in the present configuration example, the control signal S3 from the transfer control unit 32 described above is applied to the arbitration circuit 121 as REQ1 indicating the presence or absence of an access right request to the transfer circuit 11. In addition, the timing control circuit 126 provided in the transfer processing unit 31 inverts and delays the control signal REQ1_OK from the arbitration circuit 121, and then indicates a pulse-like control signal indicating the end of data transfer by the transfer processing unit 31. Output as S4. Since the transfer control unit 32 that has received the control signal S4 outputs a new control signal S3, the arbitration circuit 111 that has received the control signal S3 instructs the DRAM controller 101 to rewrite the data in the buffer 103. . As a result, when the delay time of the timing control circuit 126 is short, the arbitration circuit 121 instructs the DRAM controller 102 to transfer data for the rectangular area, and then the DRAM controller 102 writes the data in the buffer 103 to the video memory 3. Until then, the data in the buffer 103 is rewritten. Therefore, the delay time is determined between the time when the arbitration circuit 121 instructs the DRAM controller 102 to transfer data for the rectangular area and the time when the DRAM controller 102 writes the data in the buffer 103 to the video memory 3. The data is set not to change.

  Further, signals from the external bus, which indicate a request for access right to the main memory 2 or the video memory 3, are respectively delayed by the one-shot multivibrator and then sent to the arbitration circuits 111 and 121. It is input as REQ0. The Busy signals from the DRAM controllers 101 and 102 are input to the Busy terminals of the corresponding arbitration circuits 111 and 121, respectively. The Access signals indicating the access permission output from the arbitration circuits 111 and 121 are respectively It is input to the Access terminal of the corresponding DRAM controller 101/102.

  Thus, the arbitration circuit 111 causes the transfer control unit 32 and the external bus to each of the main memory 2 based on the control signal S3 from the transfer control unit 32 and the signal input from the external bus to the REQ0 terminal. It can be determined whether or not access is requested.

  Further, the arbitration circuit 111 determines that at least one of the REQ0 and REQ1 terminals is true during the period when the Busy signal from the DRAM controller 101 is false (the period when the DRAM controller 101 is free) (requesting access). In the case where the access right is given to one of the ones requesting access in accordance with a predetermined procedure, and the control signal REQ1_OK indicating whether the access right is given to the transfer circuit 11 is output. it can. Further, when an access right is given to one of the transfer circuit 11 and the circuit connected to the external bus, an Access signal indicating that access is permitted can be output to the DRAM controller 101.

  Similarly, the arbitration circuit 121 determines whether each of the transfer control unit 32 and the external bus is based on a signal input from the timing control circuit 104 to the REQ1 terminal and a signal input from the external bus to the REQ0 terminal. It can be determined whether or not access to the video memory 3 is requested.

  Further, the arbitration circuit 121 determines that at least one of the REQ0 and REQ1 terminals is true during the period when the Busy signal from the DRAM controller 102 is false (the period when the DRAM controller 102 is free) (requesting access). In the case where the access right is given to one of the ones requesting access in accordance with a predetermined procedure, and the control signal REQ1_OK indicating whether the access right is given to the transfer circuit 11 is output. it can. Further, when an access right is given to one of the transfer circuit 11 and the circuit connected to the external bus, an Access signal indicating permission of access can be output to the DRAM controller 102.

  In the above configuration, when there is no external access request, the arbitration circuit 111 gives an access right to the transfer circuit 11 when the DRAM controller 101 is idle when the control signal S3 from the transfer control unit 32 becomes true. An Access signal and a REQ1_OK signal indicating that the Thereby, the multiplexer 112 outputs the address signal A1 to the DRAM controller 101, the logic circuit 114 instructs the DRAM controller 101 to read, and the three-state buffer 113 receives the data from the external bus to the main memory 2. Cut off. As a result, the data stored at the address indicated by the address signal A 1 is output from the main memory 2 and latched in the buffer 103.

  After the data is latched in the buffer 103, the control signal REQ1_OK from the arbitration circuit 111 is input to the REQ1 terminal of the arbitration circuit 121. Accordingly, the arbitration circuit 121 outputs an Access signal and a REQ1_OK signal indicating that the access right is given to the transfer circuit 11. Thereby, the multiplexer 122 outputs the address signal A2 to the DRAM controller 102, the logic circuit 124 instructs the DRAM controller 102 to write, and the multiplexer 125 and the 3-state buffer 123 video data from the buffer 103. Input to the data terminal of the memory 3. As a result, the data from the main memory 2 is stored in the video memory 3 at the address indicated by the address signal A2. Further, the timing control circuit 126 delays and inverts the control signal REQ1_OK from the arbitration circuit 121 and outputs it as a pulsed control signal S4.

  On the other hand, as shown in FIG. 10, the control unit 43 of the transfer control unit 32 according to the present configuration example compares the value of the width register 21 with the count value of the width counter 41 and determines the match / mismatch. Are compared with the value of the height register 22 and the count value of the line number counter 42 to determine coincidence / non-coincidence, based on the output of the comparator 201 and the control signal S4 from the transfer processing unit 31. Based on the logic circuit 203 for generating the control signal S11 indicating whether or not the end of the rectangular area in the horizontal line has been reached, the outputs of the comparators 201 and 202 and the control signal S4, the end of the rectangle and the rectangle A logic circuit 204 for generating a control signal S12 indicating whether or not both unfinished transfers of the entire area are established; And a logic circuit 205 that generates a control signal S13 indicating whether or not both the arrival at the end and the end of the transfer of the entire rectangular area are established based on the outputs of 201 and 202 and the control signal S4. ing.

  Accordingly, the control unit 43 can output the control signals S11 and S12 as the control signal S1 every time the transfer processing unit 31 performs data transfer. The control signal S12 is input as a part of the control signal S1 to circuits 221 and 222 (both described later) shared by the address calculation units 33 and 34 and the transfer control unit 32. .

  The logic circuit 203 is a circuit that outputs whether or not the output of the comparator 201 indicates inconsistency during a period in which the pulse of the control signal S4 is applied from the transfer processing unit 31, and the output of the logic circuit 203 The control signal S11 to be output is output to the video memory address calculation unit 34 as a part of the control signal S1 described above. The control signal S11 is input to the increment terminal INC of the width counter 41.

  Further, the logic circuit 204 determines whether or not both the condition that the output of the comparator 201 indicates coincidence and the condition that the output of the comparator 202 indicates disagreement are established from the transfer processing unit 31 by the control signal S4. The control signal S12 output from the logic circuit 204 is input to the increment terminal INC of the line number counter 42.

  Further, the logic circuit 205 is a circuit that outputs whether or not both outputs of the comparators 201 and 202 indicate coincidence during a period in which the pulse of the control signal S4 is applied from the transfer processing unit 31. The control signal S13 output from the logic circuit 205 is input to the reset terminal R to the transfer status register 211 described later.

  On the other hand, the control unit 43 of the transfer control unit 32 includes a transfer status register 211 that can be accessed from an external circuit such as the CPU 6 via an external bus, and the external circuit sets the transfer status register 211. Thus, the transfer circuit 11 can be instructed to transfer the rectangular area.

  Further, when the transfer of the rectangular area is completed, the logic circuit 205 resets the transfer status register 211, and the output of the transfer status register 211 is output to the external bus via the buffer. Thus, the external circuit can confirm whether or not the transfer of the rectangular area is completed by reading the output of the transfer status register 211.

  Further, the output signal of the transfer state register 211 is delayed by a timing control circuit 212 realized by, for example, a one-shot multivibrator or the like, and then, as the pulse-like control signal S2, the above-described address calculation units 33. 34. Thereby, the control unit 43 can output the control signal S2 when the transfer of the rectangular area is instructed. The control signal S12 is inverted by an inverter and then input to a low active reset terminal of the line number counter 42.

  Further, the control unit 43 inverts the output of the OR circuit 221 that calculates the logical sum of the control signal S2 and the control signal S12, and inputs the input to the low reset terminal of the width counter 41. And an inverter 222. These circuits 221 and 222 are also part of both the address calculation units 33 and 34 shown in FIG. 1, and the output signal S14 of the inverter 222 is sent to the line start address registers 51 and 61 and the address calculation units 33 and 34, respectively. A negative logic load signal is input to the current address counters 52 and 62.

  Further, the control unit 43 includes, for example, a timing control circuit 231 that is realized by a one-shot multivibrator or the like and delays an output signal of the OR circuit 221, an output signal of the timing control circuit 231, and the control signal. An OR circuit 232 that calculates a logical sum with S11 and outputs it as a control signal S3 is provided.

  Thus, the control unit 43 outputs a control signal S3 instructing the transfer processing unit 31 to perform a new transfer when the data transfer of the rectangular area is instructed and every time the transfer processing unit 31 ends the data transfer. it can.

  On the other hand, as shown in FIG. 11, the control unit 53 of the main memory address calculation unit 33 according to this configuration example includes an adder 301 that adds the value of the line start address register 51 and the value of the address difference register 24, A multiplexer that selects one of the output value of the adder 301 and the output value of the start address register 23 based on the control signal S 2 from the transfer control unit 32 and inputs the selected value to the line start address register 51 and the current address counter 52. 302.

  In the above configuration, when the transfer of the rectangular area is started, the control signal S2 from the transfer control unit 32 becomes true. In response to this, the multiplexer 302 inputs the value of the start address register 23 to both the circuits 51 and 52.

  Further, after the control signal S2 becomes true, the negative logic control signal S14 becomes true (Low) after being delayed by the delay time of the OR circuits 221 and 223 and the timing control circuit 231 shown in FIG. At this time, since the value of the start address register 23 is input to the input terminal D of both the circuits 51 and 52, the circuits 51 and 52 store the values. The pulse width of the control signal S2 is at least true from the time when the control signal S2 becomes true until the value of the start address register 23 is stored in both the circuits 51 and 52. It is set to continue.

  Further, since the control signal S5 is input from the transfer processing unit 31 to the current address counter 52, the value of the current address counter 52 is incremented each time the control signal S5 is input.

  On the other hand, after the start of transfer of the rectangular area is instructed and the pulsed control signal S2 is output, the control signal S2 is always kept false. In this state, since the multiplexer 301 selects the output of the adder 301, the value of the line start address register 51 and the value of the address difference register 24 are added to the input terminals D of both the circuits 51 and 52. The result is entered.

  In this state, when the logic circuit 203 of the transfer control unit 32 determines that the end of the rectangular area has been reached in the current horizontal line and the control signal S12 is set to true, the control signal S14 becomes true. Therefore, both the circuits 51 and 52 newly store the addition result.

  Similarly, the control unit 63 of the video memory address calculating unit 34 according to this configuration example includes an adder 401 that adds the value of the line start address register 61 and the value of the address difference register 26, as shown in FIG. Based on the control signal S2 from the transfer control unit 32, one of the output value of the adder 401 and the output value of the start address register 25 is selected and input to the line start address register 61 and the current address counter 12. And a multiplexer 402.

  The operations of the members 25, 26, 61, 62, 301, and 302 related to the video memory address calculating unit 34 are as follows, in place of the control signal S5 at the increment terminal INC of the current address counter 62. , Except that the control signal S11 is input and the count value of the current address counter 62 is incremented every time the control signal S11 becomes true. Since the operation is the same as 24, 51, 52, 401, and 402, the description thereof is omitted.

[Second Embodiment]
In the first embodiment, the case where the transfer processing unit 31 transmits pixel data one word at a time has been described as an example. On the other hand, in the present embodiment, a configuration in which the main memory 2 and the video memory 3 are capable of burst transfer and the transfer processing unit performs burst transfer for each of a plurality of words will be described.

  As will be described later, the transfer processing unit may perform burst transfer of data for a plurality of pixels, but in the following, data for one pixel corresponds to data for a plurality of words in the main memory 2 and the video memory 3. This will be described as an example.

  That is, as shown in FIG. 1, the main memory 2a and the video memory 3a according to the present embodiment are substantially the same as the main memory 2 and the video memory 3 according to the first embodiment. , Written across multiple addresses.

  The transfer circuit 11a according to the present embodiment is substantially the same as the transfer circuit 11 shown in FIG. 1, except that the increments of the current address counters 52a and 52a of the address calculators 33a and 34a are respectively increased in the main memory 2a. The number of addresses occupied by data of one pixel and the number of addresses occupied by data of one pixel in the video memory 3a are set.

  Furthermore, in the transfer processing unit 31a according to the present embodiment, the buffer 103a is realized by a FIFO (First In First Out) buffer, and can store data for one pixel. The DRAM controller 101a is configured to write the data in the main memory 2 to the buffer 103a by burst transfer, and the DRAM controller 102a is configured to write the data in the buffer 103a to the video memory 3 by burst transfer. Here, the burst length when the DRAM controllers 101a and 102a perform burst transfer is set to the number of addresses occupied by one pixel data in the main memory 2a and the number of addresses occupied by one pixel data in the video memory 3a. Is set to

  Note that, among the members of the transfer circuit 11a, the members that have not been described above and the functions and operations that have not been described are the functions and operations of the members described above according to the first embodiment. Since it is the same as each member of the transfer circuit 11 or a corresponding member (a member excluding “a” at the end of the reference numeral), description thereof is omitted.

  In the above configuration, although data for one pixel is written to the main memory 2a and the video memory 3a over a plurality of addresses, the data of each pixel is transferred to the transfer source memory (in this case, by burst transfer). The main memory 2a) is transferred to the destination memory (in this case, the video memory 3a). Therefore, the data in the rectangular area can be transferred in a shorter time than when transferring one word at a time.

  Even in this case, the external circuit such as the CPU 6 does not need to give an instruction to the transfer processing unit 31a for each data transfer by the transfer processing unit 31a or for each data transfer for one horizontal line by the transfer processing unit 31a. Therefore, it is possible to prevent the occurrence of overhead due to the external circuit instructing the transfer circuit 11a. As a result, data in an arbitrary rectangular area can be transferred at high speed between the memories 2a and 3a having different memory configurations.

  In both memories 2 and 3, the number of addresses occupied by data for one pixel may be the same or different from each other. When the read unit (data amount for one word) is different from the write unit, the FIFO buffer 103a is in the unit of the DRAM controller as viewed from the DRAM controller (in this case, 101a) to be written. From the viewpoint of the DRAM controller (in this case, 102a) that accepts and reads data, it suffices if it is configured to be able to accept data read in units of the DRAM controller. In the above description, the case of performing burst transfer to both the main memory 2 and the video memory 3 has been described as an example, but the same effect can be obtained even when only one of them is burst transferred.

  By the way, in the above, as an example of burst transfer, data for one pixel corresponds to data of a plurality of words in the main memory 2 and the video memory 3, and the transfer processing unit 31a transfers data for one pixel. Explained. In contrast, a case where data of a plurality of pixels is burst transferred will be described below. The following configuration can also be applied to a case where data for one pixel corresponds to a plurality of words, but in the following, for convenience of explanation, data for one pixel is 1 as in the first embodiment. The case where it corresponds to a word will be described.

  That is, the transfer circuit 11b according to this modification is configured in substantially the same manner as the transfer circuit 11 as shown in FIG. 13, but the transfer processing unit 31b is configured to be capable of burst transfer of data for a plurality of pixels. The increments of the current address counters 52b and 52b of the address calculation units 33b and 34b are set to the number of addresses occupied by the data for the plurality of pixels in the main memory 2 or the video memory 3, respectively. In addition, in the transfer control unit 32b according to this modification, the increment of the width counter 41b is set to the number of pixels to be transferred in a batch.

  Furthermore, in addition to the determination of the transfer control unit 32, the transfer control unit 32b according to the present modification example does not reach the end of the current horizontal line, and if the transfer of the entire rectangular area is not completed, The number of pixels to be transferred can be calculated and output to the transfer processing unit 31b as the control signal S6. The circuit that outputs the control signal S6 can be realized by, for example, a circuit that subtracts the count value of the width counter 41 from the value stored in the width register 21.

  In addition, the transfer processing unit 31b includes, for example, a circuit that outputs the number of words corresponding to the number of pixels of the control signal S6 to the DRAM controllers 101b and 102b as the burst length of each DRAM controller 101b and 102b. Data of the number of words corresponding to the number of pixels indicated by the control signal S6 can be burst transferred.

  As an example, when the data for one pixel corresponds to one word in each of the memories 2 and 3, and the transfer processing unit 31b is configured to be capable of burst transfer of data for four pixels, each address calculation unit 33b The increment of the current address counter 52b / 52b of 34b is set to 4 words.

  In this case, if the transfer control unit 32b does not reach the end of the current horizontal line and the transfer of the entire rectangular area has not been completed, the transfer area 32b has to remain at least 4 pixels in the rectangular area of the current horizontal line. 4 is output as the control signal S6, and when only 3, 2 or 1 pixel remains, 3, 2 or 1 is output as the control signal S6.

  Furthermore, if the rectangular area of the current horizontal line remains in 4 pixels or more, the transfer processing unit 31b reads the data in the main memory 2 by 4 words and burst transfer, and transfers the data to the video memory 3 by burst transfer of 4 words. Write to.

  On the other hand, when only 3 pixels remain in the rectangular area of the current horizontal line, the data in the main memory 2 is read out by the corresponding word (in this case, 3 words) by burst transfer, and the number of remaining pixels is determined. The data is written into the video memory 3 by burst transfer of another word (in this case, 3 words).

  Of the members of the transfer circuit 11b, the members not described above and the functions and operations of the members described above are the same as those described above. Or, since it is the same as a corresponding member (a member excluding b at the end of the reference numeral), the description thereof is omitted.

  Even in the above configuration, the data of each pixel is transferred from the transfer source memory (in this case, the main memory 2) to the transfer destination memory (in this case, the video memory 3) by burst transfer. Therefore, similarly to the transfer circuit 11a, data in an arbitrary rectangular area can be transferred at high speed between the memories 2 and 3 having different memory configurations.

[Third Embodiment]
In the first and second embodiments, as an example, the configuration in which the transfer circuit transfers the rectangular area data from the main memory to the video memory has been described. In contrast, in the present embodiment, a configuration in which the transfer circuit transfers data bidirectionally will be described. Although this configuration can be applied to the second embodiment, a case where it is applied to the first embodiment will be described below as an example.

  That is, the transfer circuit 11c according to the present embodiment, as shown in FIG. 14, in accordance with an instruction from an external circuit such as the CPU 6, the transfer direction is not limited to the direction from the main memory 2 to the video memory 3. It is configured so that it can be changed in the reverse direction.

  Specifically, as shown in FIG. 15, the transfer circuit 11 c is provided with a transfer direction register 241 that can be accessed from an external circuit such as the CPU 6, and the value set in the transfer direction register 241 is set as a control signal. As S7, the data can be output to the transfer processing unit 31c. In the present embodiment, a configuration in which the transfer direction register 241 is provided in the transfer control unit 32c will be described as an example. However, the transfer processing unit 31c may receive an instruction of the transfer direction directly from the external circuit.

  On the other hand, in addition to the configuration of the transfer processing unit 31 illustrated in FIG. 9, the transfer processing unit 31 c includes a buffer 105 having the same configuration as the buffer 103 as illustrated in FIG. 16. However, the buffer 105 is a buffer for transfer in the reverse direction to the buffer 103, and data from the video memory 3 is input to the input terminal D through the buffer. The output of the buffer 105 is input to the 3-state buffer 113 via a multiplexer 106 provided between the external bus and the 3-state buffer 113. The multiplexer 106 is configured to select the output of the buffer 105 while the control signal S7 instructs the transfer from the video memory 3 to the main memory 2, and to select the external bus otherwise. Yes.

  Furthermore, not only the circuit shown in FIG. 16 but also the circuit shown in FIG. 17 are added to the transfer processing unit 31c. That is, until the control signal S3 is input to the REQ1 terminal of the arbitration circuit 111 shown in FIG. 9, the multiplexer 151 that selects one of the inputs according to the control signal S7 is provided. The multiplexer 151 inputs the control signal S3 to the REQ1 terminal when the control signal S7 instructs the transfer to the video memory 3, and controls the transfer when the control signal S7 instructs the transfer to the main memory 2. Instead of the signal S3, the output of the timing control circuit 126 shown in FIG. 9 can be input to the REQ1 terminal.

  In the transfer processing unit 31c, a multiplexer 152 that selects one of the inputs according to the control signal S7 is provided between the timing control circuit 104 illustrated in FIG. 9 and the REQ1 terminal of the arbitration circuit 121. When the control signal S7 instructs the transfer to the video memory 3, the multiplexer 152 inputs the output of the timing control circuit 104 to the REQ1 terminal of the arbitration circuit 121 and instructs the transfer to the main memory 2. In this case, the control signal S 3 can be input to the REQ 1 terminal of the arbitration circuit 121 instead of the output of the timing control circuit 104.

  Further, a replacement circuit 153 that replaces both in accordance with the control signal S7 is provided until the outputs of the timing control circuits 104 and 126 shown in FIG. 9 are output as the control signals S5 and S4. The replacement circuit 153 can output the outputs of the timing control circuits 104 and 126 as the control signals S5 and S4, as in FIG. 9, when the control signal S7 instructs the transfer to the video memory 3. On the other hand, when the control signal S7 instructs transfer to the main memory 2, unlike FIG. 9, the output of the timing control circuit 104 is output as the control signal S4, and the output of the timing control circuit 126 is It can be output as the control signal S5.

  Each address calculation unit 33c / 34c is provided with a replacement circuit 311 shown in FIG. 18 as a circuit common to both. The replacement circuit 311 inputs one of the control signal S11 from the transfer control unit 32c and the control signal S5 from the transfer processing unit 31c to the current address counter 52 of the main memory address calculation unit 33c, and the other to When the control signal S7 indicates a transfer to the video memory 3, the circuit is input to the current address counter 52 of the video memory address calculation unit 34c. When transfer to the memory 2 is indicated, the control signal S5 can be input to the current address counter 62.

  In the above configuration, when the control signal S7 indicates the transfer to the video memory 3, each member of the transfer circuit 11c operates in the same manner as the transfer circuit 11 of the first embodiment, and the data of the main memory 2 is transferred. Transfer to the video memory 3.

  On the other hand, when the control signal S 7 indicates transfer to the main memory 2, the roles of the main memory 2 and the video memory 3 are switched, and data in the video memory 3 is written into the main memory 2 via the buffer 105.

  In any case, as in the above embodiments, the external circuit such as the CPU 6 transfers the data every time the data is transferred by the transfer processing unit 31c or every time the data is transferred for one horizontal line by the transfer processing unit 31c. Since there is no need to give an instruction to the processing unit 31c, it is possible to prevent the occurrence of overhead due to the instruction from the external circuit to the transfer circuit 11. As a result, data in an arbitrary rectangular area can be transferred at high speed between the memories 2 and 3 having different memory configurations.

  In this embodiment, since data can be transferred in the direction from the video memory 3 to the main memory 2, for example, data written by a circuit that directly writes data to the video memory 3, such as a video capture circuit (not shown), The data can be transferred to the main memory 2, and the data can be grasped by an external circuit such as the CPU 6.

  In each of the above embodiments, the case where the width, height, start address, or address difference itself is stored in each of the registers 21 to 26 has been described as an example. However, the present invention is not limited to this. Information that can identify these values by calculation from the values (for example, upper left and lower right coordinates instead of the width and height) may be stored, and the above values may be calculated by calculation. However, when each value is stored directly as in each of the above embodiments, the operation in the transfer circuit (11 to 11c) is not required, so that the circuit configuration of the transfer circuit can be simplified.

  According to the present invention, a transfer circuit capable of transferring data in an arbitrary rectangular area at high speed between memories having different memory configurations can be realized. For example, data transfer between a main memory and a video memory can be performed. First, it can be used widely and suitably as a transfer circuit for transferring data between various memories.

1, showing an embodiment of the present invention, is a block diagram showing a main configuration of a transfer circuit. FIG. It is a block diagram which shows the principal part structure of the information processing apparatus containing the said transfer circuit. It is drawing which shows the memory structure of the video memory provided in the said information processing apparatus. It is drawing which shows the memory structure of the main memory provided in the said information processing apparatus. It is drawing which shows the display screen of the said information processing apparatus. It is a block diagram which shows the principal part structure of the transfer control part provided in the said transfer circuit. It is a block diagram which shows the principal part structure of the main memory address calculation part provided in the said transfer circuit. It is a block diagram which shows the principal part structure of the video memory address calculation part provided in the said transfer circuit. It is a circuit diagram which shows the structural example of the transfer process part provided in the said transfer circuit. It is a circuit diagram which shows the structural example of the said transfer control part. It is a circuit diagram which shows the structural example of the said main memory address calculation part. It is a circuit diagram which shows the structural example of the said video memory address calculation part. FIG. 29, showing another embodiment of the present invention, is a block diagram showing a main configuration of a transfer circuit. It is a block diagram which shows the modification of the said transfer circuit, and shows the principal part structure of a transfer circuit. FIG. 24 is a block diagram illustrating a transfer direction register provided in a transfer circuit according to still another embodiment of the present invention. It is a circuit diagram which shows the example of a structure of the transfer process part of the said transfer circuit, and shows the added buffer and multiplexer. It is a circuit diagram which shows the example of a structure of the transfer process part of the said transfer circuit, and shows the circuit added to both arbitration circuit vicinity. It is a block diagram which shows the structural example of both the address calculation parts of the said transfer circuit, and shows the added substitution circuit. It is a block diagram which shows a prior art and shows the principal part structure of information processing apparatus.

Explanation of symbols

11 to 11c Transfer circuit 24 Address difference register (transfer source address difference register)
26 Address difference register (transfer destination address difference register)
31-31c Transfer processing unit (transfer processing circuit)
32 to 32c Transfer control unit (determination circuit)
33-33c Main memory address calculation unit (transfer source address calculation circuit)
34 to 34c Video memory address calculation unit (transfer destination address calculation circuit)

Claims (3)

A transfer circuit for transferring data of a rectangular area image composed of a plurality of lines from a transfer source memory to a transfer destination memory,
At the transfer source memory, the transfer source address difference register for storing the address difference information indicating the difference between the start address each other between data corresponding to adjacent lines of the rectangular region image,
At the destination memory, and the transfer destination address difference register for storing an address difference information indicating the difference between the start address each other between data corresponding to adjacent lines of the rectangular region image,
A transfer processing circuit for transferring data from the designated address of the transfer source memory to the designated address of the transfer destination memory;
For each data transfer by the transfer processing circuit, calculate the address of the transfer source memory to be transferred next, and instruct the transfer processing circuit, a transfer source address calculation circuit;
For each data transfer by the transfer processing circuit, a transfer destination address calculating circuit that calculates an address of a transfer destination memory to which data is transferred next and instructs the transfer processing circuit;
A determination circuit for determining whether or not the transfer of the rectangular area in the current line is completed for each data transfer by the transfer processing circuit,
Both the address difference information stored in the transfer source memory and the address difference information stored in the transfer destination memory can be arbitrarily set,
When each of the address calculation circuits determines that the transfer of the rectangular area of the current line is completed, the address calculation circuit refers to the address difference information stored in the corresponding address difference register among the address difference registers. A transfer circuit which calculates a start address in the next line of the rectangular area and outputs it as an address to which data is to be transferred next.   2. The transfer circuit according to claim 1, wherein the transfer processing circuit collectively transfers data of a plurality of addresses in at least one of the transfer source memory and the transfer destination memory. The transfer source address difference register and the transfer destination address difference register can change the address difference information stored in the corresponding address difference register during the data transfer by the transfer processing circuit. Item 3. The transfer circuit according to Item 1 or 2.