JP2009032248A - Bus communication apparatus using shared memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus communication apparatus which allows a communication destination master to issue a command in advance and is capable of improving bus transfer efficiency. <P>SOLUTION: A communication source master 101 selectively uses an arbitration completion notification signal and a memory access completion notification signal. Based on the arbitration completion notification signal, the communication source master 101 issues a command issue permission signal to the communication destination master 102, and the communication destination master 102 generates and issues a command for accessing a shared memory 12. Based on the memory access completion notification signal, the communication source master 101 issues a command issue permission signal to the communication destination master 102, and the communication destination master 102 generates and issues a command for accessing the shared memory 12. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a bus communication device that performs data transfer between masters via a shared memory.

Conventionally, bus communication is performed between a plurality of masters using a shared memory. At this time, upon completion of access to the shared memory by the communication source master, the communication source master starts up, triggered by an interrupt output from the communication source master to the communication destination master or a completion notification signal from the communication source master, The process proceeds to a phase for generating a memory access command to the shared memory.
As an example, in the bus communication device described in Patent Document 1, in data transfer between processors, the transfer source processor writes data to the shared memory, and outputs an interrupt to the transfer destination processor after the writing is completed. The transfer destination processor that has received the interrupt accesses the shared memory and reads the data written in the memory.

Further, according to the technique described in Patent Document 2, when transferring the data in the local memory of the transfer source system to the transfer destination system via the shared memory, the transfer source system is transferred using a direct memory access controller. Write local memory data directly to the shared memory. When the writing is completed, the direct memory access controller notifies the transfer destination system of an interrupt via the interrupt branch circuit when the writing is completed. Upon receiving the interrupt notification, the transfer destination system accesses the shared memory and reads the written data.
JP 2004-86615 A JP 2004-70642 A

In the conventional bus communication device as described above, the communication destination master shifts to the memory access command generation phase with an interrupt or a communication source completion notification signal when the data transfer is completed by the memory access of the communication source master. Yes.
For this reason, even if the command of the communication destination master is issued in advance before the data transfer of the communication source master is completed, even if data coherency is maintained, the command is advanced by the communication destination master. There is a problem that it cannot be issued automatically.

  The present invention solves the above-described problems, and provides a bus communication device and a control method thereof capable of improving the bus transfer efficiency by enabling the command issuance by the communication destination master in the above case. With the goal.

  To achieve the above object, the present invention is a bus communication device including a shared memory, a memory control unit, a communication source master, and a communication destination master. The memory control unit (a) arbitrates a plurality of commands indicating access to the shared memory, grants an access right to any command, and (b) arbitrates indicating that arbitration has been completed for the command. A completion signal is output, (c) the shared memory is accessed based on the command to which the access right is given, and (d) the access to the shared memory is completed when the access to the shared memory by the command is completed. An access completion signal indicating completion is output. The communication source master outputs a write command indicating writing of target data to the shared memory, programmably selects the arbitration completion signal or the access completion signal, and issues a command based on the selected completion signal A permission signal indicating permission is output. The communication destination master outputs a read command indicating reading of the target data from the shared memory based on the permission signal.

According to this configuration, since the arbitration completion signal or the access completion signal is selected programmably and the permission signal is output, the command generation timing of the communication destination master can be more flexibly compared to the conventional technique using only the access completion signal. It becomes possible to control.
Here, in the bus communication device, the communication source master outputs a generation instruction signal instructing generation of the read command together with the output of the write command, and provides a time difference after outputting the generation instruction signal. The permission signal indicating permission to issue the read command is output, and the communication destination master generates the read command based on the generation instruction signal, and outputs the generated read command based on the permission signal. It is good.

According to this configuration, since the generation of the read command of the communication destination master is started in advance when the generation instruction signal is received, the command generation is completed earlier than when generation is started when the permission signal is received. It becomes possible to issue a command at an early stage.
Here, in the bus communication device, the memory control unit arbitrates a plurality of commands indicating access to the shared memory, and acquires an access right, and a command arbitration unit that grants an access right to any command A memory access unit that accesses the shared memory based on the command, an arbitration completion signal output unit that outputs the arbitration completion signal when any command acquires an access right, and an access right An access completion signal output unit for generating the access completion signal when access to the shared memory by the command is completed. The communication source master programmatically selects a command output unit that outputs the write command, and the arbitration completion signal or the access completion signal, and outputs the permission signal based on the selected completion signal. With.
Here, in the bus communication device, the communication source master further stores, in correspondence with each master, top priority information indicating whether or not the master has the highest priority authority in the command arbitration unit. The completion notification control unit includes a master information table, and the completion notification control unit determines whether the transfer destination master has the highest priority authority using the highest priority information stored in the master information table and corresponding to the transfer destination master. Then, when the transfer destination master has the highest priority authority, the access completion signal is selected, and when the transfer destination master does not have the highest priority authority, the arbitration completion signal is selected.

If the communication destination master has the highest priority authority, the execution order of the communication source command and the communication destination command can be reversed if the command of the communication destination master is subject to arbitration before the transfer of the communication source master is completed. Therefore, data coherency cannot be maintained.
In this configuration, when the transfer destination master has the highest priority authority, the permission signal is generated based on the access completion signal, so that data coherency can be maintained.

On the other hand, if the communication destination master does not have the highest priority authority in the command arbitration unit, communication can be performed even if the communication destination command is issued in advance, after the command of the communication source master is adjusted by the command arbitration unit. Since the order of execution of the communication destination command does not change after execution of the original command, data coherency is maintained.
In this way, data coherency is ensured by programmablely selecting a trigger that generates a permission signal indicating permission to issue a command based on whether the communication destination master has the highest priority authority in the command arbitration unit. However, the bus transfer efficiency can be improved.
Here, in the bus communication device, the communication source master further determines whether access to the area by the master has the highest priority authority for each area constituting the shared memory corresponding to each master. Including a slave attribute information table storing the highest priority information to be displayed, wherein the completion notification control unit is stored in the slave attribute information table and uses the highest priority information for an area to be accessed by the transfer destination master. Determining whether or not the area to be accessed by the transfer destination master has the highest priority authority. If the area has the highest priority authority, the access completion signal is selected, and the area is If the highest priority authority is not possessed, the arbitration completion signal is selected.

According to this configuration, while ensuring data coherency by programmatically selecting a trigger that generates a permission signal indicating permission to issue a command based on whether the area to be accessed has the highest priority authority, The bus transfer efficiency can be improved.
Here, in the bus communication device, the communication source master further stores, in correspondence with each master, first highest priority information indicating whether or not the master has the highest priority authority in the command arbitration unit. Corresponding to each master, and for each area constituting the shared memory, second highest priority information indicating whether the access by the master to the area has the highest priority authority is stored. The completion notification control unit (a) uses the first highest priority information stored in the master information table and corresponding to the transfer destination master, and the transfer destination master has the highest priority. (B) using the second highest priority information for the area that is stored in the slave attribute information table and is the access target by the transfer destination master Determining whether or not the area to be accessed by the transfer destination master has the highest priority authority, and (c) the transfer destination master does not have the highest priority authority, and the area has the highest priority authority. The arbitration completion signal is selected, and (d) the communication destination master has the highest priority authority, or the communication destination master does not have the highest priority authority, and the area Selects the access completion signal when has the highest priority.

According to this configuration, permission to issue a command is indicated based on whether the communication destination master has the highest priority authority in the command arbitration unit, and whether the area to be accessed has the highest priority authority. By selecting the trigger for generating the permission signal in a programmable manner, it is possible to improve bus transfer efficiency while ensuring data coherency.
In addition, the present invention is a bus communication device including a shared memory, a memory control unit, a communication source master, and a communication destination master. The memory control unit arbitrates a plurality of commands indicating access to the shared memory, grants an access right to any command, and outputs an arbitration completion signal indicating that arbitration has been completed for the command, The shared memory is accessed based on the command to which the access right is given. The communication source master outputs (a) a write command indicating writing of the target data to the shared memory, and (b) whether or not the access related to the write command has the highest priority authority in the arbitration. (C) When it is determined that the user does not have the highest priority authority, after receiving the arbitration completion signal for the write command, a permission signal indicating permission to issue a command is output. When the communication destination master receives the permission signal, the communication destination master outputs a read command indicating reading of the target data from the shared memory.

  As described above, when the communication destination master does not have the highest priority authority in the command arbitration unit, data coherency is ensured by generating a permission signal indicating permission to issue a command after receiving the arbitration completion signal. However, the bus transfer efficiency can be improved.

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 shows a configuration of a bus communication device 10 according to the present embodiment. A bus communication device 10 illustrated in FIG. 1 includes a communication source master 101, a communication destination master 102, a memory control unit 11, a shared memory 12, a communication bus 13, and a memory bus 14. The communication source master 101, the communication destination master 102, and the memory control unit 11 are connected to each other via a communication bus 13, and the memory control unit 11 and the shared memory 12 are connected to each other via a memory bus 14. Note that the bus communication device 10 includes only two of the communication source master 101 and the communication destination master 102 as masters for simplification of description, but may be configured to include two or more masters. . Here, each of the communication source master 101 and the communication destination master 102 is a processor, for example.

The communication source master 101 and the communication destination master 102 each access the shared memory 12 via the memory control unit 11.
The memory control unit 11 (a) arbitrates a plurality of commands indicating access to the shared memory 12, grants an access right to any command, and (b) completes arbitration for the command to which the access right is granted. (C) outputs an arbitration completion notification signal indicating that access is made to the shared memory 12 based on the command to which the access right is granted, and (d) completes access to the shared memory 12 by the command to which the access right is granted. When this occurs, a memory access completion notification signal indicating completion of access to the shared memory is output.

The communication source master 101 outputs a write command indicating the writing of the target data to the shared memory 12, and programmably selects the arbitration completion notification signal or the memory access completion notification signal, and based on the selected completion notification signal Then, a command issue permission signal indicating permission for command issue is output.
The communication destination master 102 outputs a read command indicating the reading of the target data from the shared memory 12 based on the command issue permission signal.

  FIG. 2 shows the internal configuration of the memory control unit 11. As shown in FIG. 2, the memory control unit 11 includes memory access command holding units 201 and 202, an arbitration unit 21, and a memory access unit 22. Note that the memory control unit 11 includes only two memory access command holding units 201 and 202 as memory access command holding units for the sake of simplicity of explanation, but the number of masters constituting the bus communication device 10 The number of memory access command holding units may be the same.

  The memory access command holding unit 201 acquires and holds the memory access command of the communication source master 101. The memory access command of the communication source master 101 is a command indicating that the target data is written to the shared memory 12. Similarly, the memory access command holding unit 202 acquires and holds the memory access command of the communication destination master 102. The memory access command of the communication destination master 102 is a command indicating that the target data is read from the shared memory 12.

  The arbitration unit 21 arbitrates a plurality of commands to be arbitrated among the memory access commands held in each memory access command holding unit, grants an access right to any command, and performs arbitration for the command. An arbitration completion notification signal indicating completion is output. The arbitration unit 21 arbitrates in units of memory access commands. When there is an access from the master having the highest priority authority, the command being executed is temporarily stopped, the command having the highest priority authority is executed, and then the stopped command is resumed.

The memory access unit 22 actually accesses the shared memory 12 based on the memory access command that has been arbitrated and obtained the right.
FIG. 3 shows the internal configuration of the arbitration unit 21. The arbitration unit 21 includes an arbitration completion notification signal generation unit 31 that generates an arbitration completion notification signal. The arbitration completion notification signal indicates that the arbitration of the memory access command has been completed, and is notified to the command issuing master.

FIG. 4 shows the internal configuration of the memory access unit 22. The memory access unit 22 includes a memory access completion notification signal generation unit 41 that generates a memory access completion notification signal. The memory access completion notification signal indicates that access to the shared memory 12 has been completed and is notified to the command issuing master.
FIG. 5 shows the internal configuration of each master. The communication source master 101 includes a memory access command generation unit 51, a completion notification control unit 52, a bus communication setting register 55, and a master information table 71.

FIG. 6 shows the configuration of the bus communication setting register 55. The bus communication setting register 55 includes a bus transfer flag indicating whether or not the transfer is a transfer for performing bus communication and a communication destination master ID for identifying a master to be communicated when performing the bus communication.
At the start of the transfer, the communication source master stores in the bus communication setting register 55 a bus transfer flag indicating whether the transfer is a transfer for performing bus communication, and a communication destination indicating which master is to communicate with when performing the bus communication. Set the master ID. Further, the communication source master 101 holds information indicating which master has the highest priority authority in the arbitration unit 21 as the master information table 71 in FIG. The master information table 71 indicates whether the master has the highest priority authority or does not have the highest priority authority in association with the identification number (ID) of each master. In FIG. 7, as an example, the master identified by the identification number (ID) “0” has the highest priority authority, and the master identified by the identification numbers (ID) “1” to “3” is the highest priority. It shows that it does not have the authority of.

The completion notification control unit 52 selects either the arbitration completion notification signal or the memory access completion notification signal for each command being executed by the bus communication setting register 55 and the master information table 71, and sends the communication source to the corresponding communication destination master. Notify completion in the master.
The completion notification control unit 52 performs the above selection as follows.
The completion notification control unit 52 determines, based on the bus communication flag of the bus communication setting register 55, whether or not the transfer is a transfer for performing bus communication. When the bus communication flag indicates that the transfer is not for bus communication, the corresponding processing is performed. When the bus communication flag indicates that the transfer is to perform bus communication, the completion notification control unit 52 uses the master information table 71 to indicate that the communication master indicated by the communication master ID of the bus communication setting register 55 is the highest. Determine whether you have priority authority. When the completion notification control unit 52 determines that the communication master indicated by the communication master ID in the bus communication setting register 55 has the highest priority authority, the arbitration completion notification signal is selected. On the other hand, if it is determined that the communication master does not have the highest priority authority, the memory access completion notification signal is selected.

As shown in FIG. 5, the communication destination master 102 includes a command issue permission signal reception unit 53 and a memory access command generation unit 54.
The command issuance permission signal receiving unit 53 receives a command issuance permission signal from the communication source master 101 via the memory control unit 11. When the command issuance permission signal reception unit 53 receives the command issuance permission signal, the memory access command generation unit 54 generates a memory access command for the communication destination master 102 and outputs the generated memory access command to the memory control unit 11.

FIG. 10 shows an overall configuration diagram of the first embodiment.
Next, the operation of the bus communication device 10 in the present embodiment will be described using the sequence diagrams shown in FIGS.
In the bus communication device 10 according to the present embodiment, when the communication source master 101 is activated, the communication source master 101 causes the bus communication setting register 55 to identify the communication master that is the other party performing the bus communication flag and bus communication. A master ID is set (step S101). Next, the completion notification control unit 52 determines whether or not the communication master indicated by the communication destination master ID has the highest priority authority in the arbitration unit 21 using the master information table 71 (step S102).

  If the communication destination master does not have the highest priority authority (step S102), after the communication source command for performing bus communication is arbitrated by the arbitration unit 21, the communication source command can be issued no matter what timing the communication destination command is issued. After the command is executed, the execution order for executing the communication destination command does not change, and data coherency is maintained. Therefore, based on the arbitration completion notification signal from the arbitration completion notification signal generation unit 31 (step S111), the completion notification control unit 52 generates a command issuance permission signal for the communication destination master, and processing of the communication source master Completion is notified (step S112).

  The command issuance permission signal receiving unit 53 of the communication destination master 102 receives the command issuance permission signal (step S112), instructs the memory access command generation unit 54 (step S114), and the memory access command generation unit 54 receives the memory access command. Is generated (step S115), and the generated memory access command is issued (output) to the memory control unit 11 (step S116).

The memory control unit 11 receives the memory access command (step S116), and executes the received memory access command (step S117).
As a result, it becomes possible to generate and issue a command of the communication destination master at an earlier stage than the time when the memory access of the communication source master is completed, and the bus transfer efficiency is improved.
Further, when the communication destination master has the highest priority authority (step S102), if the communication destination master command is subject to arbitration before the transfer of the communication source master is completed, the communication source command and the communication destination command are updated. Since the execution order may be reversed, data coherency cannot be maintained. In this case, based on the memory access completion notification signal from the memory access completion notification signal generation unit 41 (step S131), the completion notification control unit 52 generates a command issuance permission signal to the communication destination master, and the communication source master. The process completion is notified (step S132).

  The command issuance permission signal accepting unit 53 receives the command issuance permission signal (step S132), instructs the memory access command generation unit 54 (step S134), and the memory access command generation unit 54 generates a memory access command (step S134). In step S135, the generated memory access command is issued (output) to the memory control unit 11 (step S136).

The memory control unit 11 receives the memory access command (step S136), and executes the received memory access command (step S137).
As described above, according to the present embodiment, the arbitration completion notification signal or the memory access completion notification signal is selected and used depending on whether or not the communication destination master has the highest priority authority in the arbitration unit 21. The bus transfer efficiency can be improved.

(Embodiment 2)
The bus communication device 10 according to the second embodiment uses the selection of the arbitration completion notification signal or the memory access completion notification signal by the communication source master 101 in the bus communication with respect to the communication destination master in the bus communication device 10 of the first embodiment. This is performed according to the attribute of the shared memory area.

  The communication source master 101 holds a slave attribute information table 81 shown as an example in FIG. 8 instead of the master information table 71. The shared memory 12 is composed of a plurality of areas A, B, C, D,. The slave attribute information table 81 stores, for each master, in association with each area of the shared memory 12, whether or not access to the area is arbitrated with the highest priority authority in the arbitration unit 21. As an example, the slave attribute information table 81 is associated with the start address and the end address of each area of the shared memory 12 for each master, and whether the access to the area is arbitrated with the highest priority authority in the arbitration unit 21. I remember whether or not. Further, the slave attribute information table 81 is associated with an area identifier for identifying each area of the shared memory 12 for each master, and whether or not access to the area is arbitrated with the highest priority authority in the arbitration unit 21. May be stored. The slave attribute information table 81 shown in FIG. 8 indicates that access to the area A is arbitrated with the highest priority authority in the arbitration unit 21 for the master 1, and to the areas B, C, D,. , Indicating that access to the area B is arbitrated with the highest priority authority in the arbitration unit 21 for the master 2, and the area A, This indicates that access to the area C, the area D,... Is not arbitrated with the highest priority authority in the arbitration unit 21.

  The completion notification control unit 52 uses the slave attribute information table 81 to determine whether the area to be accessed in bus communication is an area to be arbitrated with the highest priority authority in the arbitration unit 21 with respect to the communication destination master. . As an example, the completion notification control unit 52 acquires the address of the shared memory 12 to be accessed in bus communication, determines the master by the communication destination master ID of the bus communication setting register 55, and acquires the determined master. It is determined using the slave attribute information table 81 whether the area indicated by the address is an area to be arbitrated with the highest priority authority in the arbitration unit 21. As another example, the completion notification control unit 52 determines a master based on the communication destination master ID of the bus communication setting register 55, acquires an identifier for identifying an area to be accessed in bus communication, and for the determined master, The slave attribute information table 81 is used to determine whether the area indicated by the acquired identifier is an area to be arbitrated with the highest priority authority in the arbitration unit 21.

Next, the operation flow of the bus communication device 10 according to the present embodiment will be described with reference to the sequence diagrams shown in FIGS. 15, 13, and 14.
In the bus communication device 10 according to the present embodiment, when the communication source master 101 is activated, the communication source master 101 has the bus communication setting register 55 identify the communication master that is the other party performing the bus communication flag and bus communication. A master ID is set (step S150).

Next, the completion notification control unit 52 determines whether the area to be accessed in the bus communication is the area to be arbitrated with the highest priority authority in the arbitration unit 21 for the communication destination master determined by the communication destination master ID. The determination is made using the attribute information table 81 (step S151).
If there is no authority with the highest priority in the access area (step S151), after the communication source command for performing bus communication is arbitrated by the arbitration unit 21, the communication source command can be issued no matter what timing the communication destination command is issued. After execution, the execution order of execution of the communication destination command does not change and data coherency is maintained. Therefore, based on the arbitration completion notification signal from the arbitration completion notification signal generation unit 31 (step S111), the completion notification control unit 52 generates a command issuance permission signal for the communication destination master 102, and processing of the communication source master Completion is notified (step S112).

  The command issuance permission signal is received by the command issuance permission signal reception unit 53 of the communication destination master 102 (steps S112 and S114), and the memory access command generation unit 54 generates and issues a memory access command (step S115) (step S116). ). The memory control unit 11 receives the memory access command (step S116), and executes the received memory access command (step S117).

As a result, as in the prior art, it becomes possible to generate and issue commands of the communication destination master at an earlier stage than when the memory access of the communication source master 101 is completed, and the bus transfer efficiency is improved.
If the access area has the highest priority authority (step S151), if the command of the communication destination master 102 is subject to arbitration before the transfer of the communication source master 101 is completed, the communication source command and the communication destination command Since the execution order may be reversed, data coherency cannot be maintained. In this case, based on the memory access completion notification signal from the memory access completion notification signal generation unit 41 (step S131), the completion notification control unit 52 generates a command issuance permission signal to the communication destination master, and the communication source master. The process completion is notified (step S132).

  The command issuance permission signal accepting unit 53 receives the command issuance permission signal (step S132), instructs the memory access command generation unit 54 (step S134), and the memory access command generation unit 54 generates a memory access command (step S134). In step S135, the generated memory access command is issued to the memory control unit 11 (step S136).

The memory control unit 11 receives the memory access command (step S136), and executes the received memory access command (step S137).
As described above, according to the present embodiment, the arbitration completion notification signal or the memory access completion notification signal is selected depending on whether or not the shared memory area used for bus communication has the highest priority authority in the arbitration unit 21. To improve the bus transfer efficiency.

(Embodiment 3)
The bus communication device according to the third embodiment performs selection of the arbitration completion notification signal or the memory access completion notification signal in the first embodiment according to the type of the communication destination master, and further in the second embodiment. The selection of the arbitration completion notification signal or the memory access completion notification signal is also performed according to the attribute of the shared memory area accessed by bus communication.

The communication source master 101 has a master information table 71 indicating which master has the highest priority authority in the arbitration unit 21 and a slave attribute indicating which area of the shared memory is arbitrated with the highest priority authority in the arbitration unit 21. An information table 81 is held.
Next, the operation flow of the bus communication device 10 according to the present embodiment will be described with reference to the sequence diagrams shown in FIGS.

When the communication source master 101 is activated in the bus communication device 10 according to the present embodiment, the communication source master 101 sets the bus communication flag and the communication destination master ID for performing the bus communication in the bus communication setting register 55 (step S170). ).
Next, the completion notification control unit 52 determines whether or not the communication destination master indicated by the communication destination master ID has the highest priority authority in the arbitration unit 21 based on the master information table 71 (step S171).

Further, the completion notification control unit 52 determines whether or not an area accessed by bus communication is arbitrated with the highest priority authority in the arbitration unit 21 for the communication destination master indicated by the communication destination master ID. (Step S172).
If the communication destination master does not have the highest priority authority (NO in step S171) and the access area does not have the highest priority authority (NO in step S172), the arbitrating unit 21 adjusts the communication source command for performing the bus communication. After that, no matter what timing the communication destination command is issued, the execution order of the communication destination command does not change after the execution of the communication source command, and the data coherency is maintained. Therefore, based on the arbitration completion notification signal from the arbitration completion notification signal generation unit 31 (step S111), the completion notification control unit 52 generates a command issuance permission signal to the communication destination master, and the processing of the communication source master is completed. Is notified (step S112).

The command issuance permission signal is received by the command issuance permission signal receiving unit 53 of the communication destination master (step S112), and the memory access command generating unit 54 generates and issues a memory access command (step S115).
The memory control unit 11 receives the memory access command (step S116), and executes the received memory access command (step S117).

As a result, as in the prior art, it becomes possible to generate and issue a command of the communication destination master at an earlier stage than when the memory access of the communication source master is completed, thereby improving the bus transfer efficiency.
If the communication destination master does not have the highest priority authority (NO in step S171) and the access area has the highest priority authority (YES in step S172), or the communication destination master has the highest priority authority. In this case (YES in step S171), if the command of the communication destination master is subject to arbitration before the transfer of the communication source master is completed, the execution order of the communication source command and the communication destination command may be reversed. Data coherency cannot be maintained. In this case, based on the memory access completion notification signal from the memory access completion notification signal generation unit 41 (step S131), the completion notification control unit 52 generates a command issuance permission signal to the communication destination master, and the communication source Notification of master processing completion is sent (step S132).

  The command issuance permission signal accepting unit 53 receives the command issuance permission signal (step S132), instructs the memory access command generation unit 54 (step S134), and the memory access command generation unit 54 generates a memory access command (step S134). In step S135, the generated memory access command is issued to the memory control unit 11 (step S136).

The memory control unit 11 receives the memory access command (step S136), and executes the received memory access command (step S137).
As described above, according to this embodiment, whether or not the communication destination master has the authority of the highest priority in the arbitration unit 21, and the shared memory area used for bus communication has the highest priority in the arbitration unit 21. The bus transfer efficiency can be improved by selecting and using the arbitration completion notification signal or the memory access completion notification signal depending on whether or not there is an authority.

(Embodiment 4)
In the bus communication apparatus 10 according to the fourth embodiment, the communication source master 101 and the communication destination master 102 are configured as shown in FIG. 9, and a command generation instruction is sent from the communication source master 101 to the communication destination master 102. This is done in two steps: a signal and a command issue permission signal. FIG. 9 shows an internal configuration diagram of the communication source master 101 and the communication destination master 102 in the fourth embodiment. FIG. 11 is an overall configuration diagram of the bus communication device 10 according to the fourth embodiment.

  The communication source master 101 outputs a command generation instruction signal for instructing generation of a read command indicating reading of the target data from the shared memory 12 together with output of a write command indicating writing of the target data to the shared memory 12. After outputting the command generation instruction signal, a command issue permission signal indicating permission for issuing the read command is output with a time difference. The communication destination master 102 generates the read command based on the command generation instruction signal, and outputs the generated read command based on the command issue permission signal.

As shown in FIG. 9, the communication source master 101 includes a memory access command generation unit 91, a completion notification control unit 92, a bus communication setting register 55, and a master information table 71.
When the communication source master 101 starts the transfer of the communication source master, the communication source master 101 communicates with the bus communication setting register 55 which bus communication flag indicates whether the transfer is a transfer for performing the bus communication, and which master when the bus communication is performed. A communication destination master ID indicating whether or not to perform is set.

The completion notification control unit 92 determines whether or not the communication destination master identified by the communication destination master ID has the highest priority authority in the arbitration unit 21 using the master information table 71.
When the issue of the command is completed, the memory access command generation unit 91 notifies the completion notification control unit 92 of a command issue completion signal.
Upon receiving the command issuance completion signal, the completion notification control unit 92 causes the bus communication setting register 55 to generate a first-stage notification (hereinafter, a command generation instruction signal) to the corresponding communication destination master. Further, the arbitration completion notification signal or the memory access completion notification signal is selected by the bus communication setting register 55 and the master information table 71, and a second notification (hereinafter referred to as a command issue permission signal) is generated to the corresponding communication destination master. .

When receiving the command generation instruction signal, the command generation instruction / issue permission signal reception unit 93 instructs the memory access command generation unit 54 to generate a command for the communication destination master.
When the memory access command generation unit 54 receives the command generation instruction signal, the memory access command generation unit 54 starts generating the communication destination command, and when receiving the command issue permission signal, the memory access command generation unit 54 issues the generated command.
Next, the operation flow of the bus communication device 10 in the present embodiment will be described using the sequence diagrams shown in FIGS.

In the bus communication device 10 according to the present embodiment, when the communication source master 101 is activated, a communication destination master ID for performing bus communication is set in the bus communication setting register 55 (step S191).
When completing the issue of the command, the memory access command generation unit 91 notifies the completion notification control unit 92 of a command issue completion signal (step S192).

Upon receiving the command issue completion signal (step S192), the completion notification control unit 92 generates a command generation instruction signal to the corresponding communication destination master indicated by the bus communication setting register 55 (step S193).
The command generation instruction / issue permission signal reception unit 93 receives the command generation instruction signal (step S193), and the memory access command generation unit 54 performs communication according to an instruction from the command generation instruction / issue permission signal reception unit 93 (step S194). A command for the destination master 102 is generated (step S195), and issuance is waited.

The completion notification control unit 92 determines whether or not the communication destination master identified by the communication destination master ID has the highest priority authority in the arbitration unit 21 using the master information table 71 (step S196).
If the communication destination master 102 does not have the authority of the highest priority (step S196), after the communication source command for performing the bus communication is arbitrated by the arbitration unit 21, the communication destination command is issued no matter what timing is issued. After the original command is executed, the order in which the communication destination commands are executed does not change, and data coherency is maintained. Therefore, based on the arbitration completion notification signal from the arbitration completion notification signal generation unit 31 (step S201), the completion notification control unit 92 generates a command issue permission signal for the communication destination master and issues it to the communication destination master 102. A command issue permission signal indicating that the waiting state command can be issued is transmitted (step S202).

  When the command generation instruction / issue permission signal reception unit 93 receives the command issue permission signal (step S202), the memory access command generation unit 54 issues the command according to the instruction of the command generation instruction / issue permission signal reception unit 93 (step S203). A command in a waiting state is immediately issued (step S204). If command generation is not completed when the command issue permission signal is received, it is issued immediately after completion.

The memory control unit 11 receives the memory access command (step S204), and executes the received memory access command (step S205).
As a result, as in the prior art, it becomes possible to generate and issue commands at the communication destination master at an earlier stage than when the memory access of the communication source master is completed, and the bus transfer efficiency is improved.

  If the communication destination master 102 has the highest priority authority (step S196), if the command of the communication destination master 102 is subject to arbitration before the transfer of the communication source master 101 is completed, communication with the communication source command is performed. Since the execution order of the previous command may be reversed, data coherency cannot be maintained. In this case, based on the memory access completion notification signal from the memory access completion notification signal generation unit 41 (step S211), the completion notification control unit 92 notifies the communication destination master 102 of a command issuance permission signal, and the communication destination The master 102 is notified that the command can be issued (step S212).

When the command generation instruction / issue permission signal reception unit 93 receives the command issue permission signal (step S212), the memory access command generation unit 54 issues the command according to the instruction of the command generation instruction / issue permission signal reception unit 93 (step S213). A command in a waiting state is immediately issued (step S214).
The memory control unit 11 receives the memory access command (step S214), and executes the received memory access command (step S215).

As described above, according to the present embodiment, the arbitration completion notification signal or the memory access completion notification signal is selected and used depending on whether or not the communication destination master 102 has the highest priority authority in the arbitration unit 21. In addition, the bus transfer efficiency can be improved.
(Embodiment 5)
In the bus communication device 10 according to the fifth embodiment, the communication source master 101 and the communication destination master 102 are configured as shown in FIG. 9 and, like the bus communication device 10 according to the fourth embodiment, the communication source master. The notification from the communication destination master 102 to the communication destination master 102 is performed in two steps: a command generation instruction signal and a command issue permission signal.

The communication source master 101 holds a slave attribute information table 81 shown in FIG.
In the fifth embodiment, as in the fourth embodiment, a command generation instruction signal is notified to the communication destination master 102 upon completion of command issue of the communication source master 101, and the command issue permission signal described in the second embodiment is transmitted to the communication destination. By notifying the master 102, it is possible to realize early command generation of the communication destination master 102 and improve the bus transfer efficiency.

Next, the operation flow of the bus communication device 10 according to the present embodiment will be described with reference to the sequence diagrams shown in FIGS. 20, 18 and 19.
In the bus communication device 10 according to the present embodiment, when the communication source master 101 is activated, a communication destination master ID for performing bus communication is set in the bus communication setting register 55 (step S191).

When completing the issue of the command, the memory access command generation unit 91 notifies the completion notification control unit 92 of a command issue completion signal (step S192).
Upon receiving the command issue completion signal (step S192), the completion notification control unit 92 generates a command generation instruction signal to the corresponding communication destination master indicated by the bus communication setting register 55 (step S193).

The command generation instruction / issue permission signal reception unit 93 receives the command generation instruction signal (step S193), and the memory access command generation unit 54 performs communication according to an instruction from the command generation instruction / issue permission signal reception unit 93 (step S194). A command for the destination master 102 is generated (step S195), and issuance is waited.
Next, the completion notification control unit 92 determines, using the slave attribute information table 81, whether or not the area to be accessed in bus communication is an area to be arbitrated with the highest priority authority in the arbitration unit 21 (step). S231).

If there is no authority with the highest priority in the access area (step S231), the completion notification control unit 92 sends a command to the communication destination master based on the arbitration completion notification signal from the arbitration completion notification signal generation unit 31 (step S201). An issuance permission signal is generated, and a command issuance permission signal indicating that the issuance waiting state command can be issued is transmitted to the communication destination master 102 (step S202).
When the command generation instruction / issue permission signal reception unit 93 receives the command issue permission signal (step S202), the memory access command generation unit 54 issues the command according to the instruction of the command generation instruction / issue permission signal reception unit 93 (step S203). A command in a waiting state is immediately issued (step S204). The memory control unit 11 receives the memory access command (step S204), and executes the received memory access command (step S205).

If the access area has the highest priority authority (step S231), the completion notification control unit 92 determines whether the communication destination is the communication destination based on the memory access completion notification signal from the memory access completion notification signal generation unit 41 (step S211). A command issuance permission signal is notified to the master 102 to notify the communication destination master 102 that a command can be issued (step S212).
When the command generation instruction / issue permission signal reception unit 93 receives the command issue permission signal (step S212), the memory access command generation unit 54 issues the command according to the instruction of the command generation instruction / issue permission signal reception unit 93 (step S213). A command in a waiting state is immediately issued (step S214). The memory control unit 11 receives the memory access command (step S214), and executes the received memory access command (step S215).

(Embodiment 6)
In the bus communication device 10 according to the sixth embodiment, the communication source master 101 and the communication destination master 102 are configured as shown in FIG. 9 and, like the bus communication device 10 according to the fourth embodiment, the communication source master. The notification from the communication destination master 102 to the communication destination master 102 is performed in two steps: a command generation instruction signal and a command issue permission signal.

The communication source master 101 has a master information table 71 indicating which master has the highest priority authority in the arbitration unit 21 and a slave attribute indicating which area of the shared memory is arbitrated with the highest priority authority in the arbitration unit 21. An information table 81 is held.
In the sixth embodiment, as in the fourth embodiment, a command generation instruction signal is notified to the communication destination master 102 upon completion of command issue of the communication source master 101, and the command issue permission signal described in the second embodiment is communicated. By notifying the destination master 102, the early command generation of the communication destination master 102 can be realized, and the bus transfer efficiency can be improved.

Next, the operation flow of the bus communication device 10 according to the present embodiment will be described with reference to sequence diagrams shown in FIGS.
In the bus communication device 10 according to the present embodiment, when the communication source master 101 is activated, a communication destination master ID for performing bus communication is set in the bus communication setting register 55 (step S191).

When completing the issue of the command, the memory access command generation unit 91 notifies the completion notification control unit 92 of a command issue completion signal (step S192).
Upon receipt of the command issuance completion signal (step S192), the completion notification control unit 92 causes the bus communication setting register 55 to generate a command generation instruction signal to the corresponding communication destination master (step S193).

The command generation instruction / issue permission signal reception unit 93 receives the command generation instruction signal (step S193), and the memory access command generation unit 54 performs communication according to an instruction from the command generation instruction / issue permission signal reception unit 93 (step S194). A command for the destination master 102 is generated (step S195), and issuance is waited.
Next, the completion notification control unit 92 determines whether or not the communication destination master indicated by the communication destination master ID has the highest priority authority in the arbitration unit 21 based on the master information table 71 (step S251).

Further, the completion notification control unit 52 determines whether or not an area accessed by bus communication is arbitrated with the highest priority authority in the arbitration unit 21 for the communication destination master indicated by the communication destination master ID. (Step S252).
If the communication destination master does not have the highest priority authority (NO in step S251) and the access area does not have the highest priority authority (NO in step S252), the arbitration completion notification signal generated by the arbitration completion notification signal generation unit 31 is used as a source. (Step S201), the completion notification control unit 92 generates a command issuance permission signal for the communication destination master, and notifies the communication destination master 102 of a command issuance permission signal indicating that an issuance waiting state command can be issued (Step S201). S202).

  When the command generation instruction / issue permission signal reception unit 93 receives the command issue permission signal (step S202), the memory access command generation unit 54 issues the command according to the instruction of the command generation instruction / issue permission signal reception unit 93 (step S203). A command in a waiting state is immediately issued (step S204). The memory control unit 11 receives the memory access command (step S204), and executes the received memory access command (step S205).

  If the communication destination master does not have the highest priority authority (NO in step S251) and the access area has the highest priority authority (YES in step S252), or the communication destination master has the highest priority authority. In this case (YES in step S251), the completion notification control unit 92 sends a command issue permission signal to the communication destination master 102 based on the memory access completion notification signal from the memory access completion notification signal generation unit 41 (step S211). This is notified and the communication destination master 102 is notified that the command can be issued (step S212).

  When the command generation instruction / issue permission signal reception unit 93 receives the command issue permission signal (step S212), the memory access command generation unit 54 issues the command according to the instruction of the command generation instruction / issue permission signal reception unit 93 (step S213). A command in a waiting state is immediately issued (step S214). The memory control unit 11 receives the memory access command (step S214), and executes the received memory access command (step S215).

(Summary)
As described above, each of the above embodiments selects a multi-layered completion communication signal in order to improve transfer efficiency while maintaining coherency in bus communication between one master and another master. It is a control device that can be used.
Here, each layer indicates a phase of each event such as a command issue phase, an arbitration completion phase, and a memory access completion phase. The command issue phase is a phase in which the communication source master 101 issues a memory access command, the arbitration completion phase is a phase in which the arbitration unit 21 of the memory control unit 11 arbitrates a plurality of commands, and the memory access completion phase is This is a phase in which the memory access by the memory access command issued by the communication source master 101 is completed. These phases are organized hierarchically. As an example, the completion communication signal of each layer includes a command issue completion signal 301 indicating completion of command issuance shown in FIG. 11, an arbitration completion notification signal 302 indicating completion of command arbitration, and memory access indicating completion of memory access by the command. This is a notification completion signal 303.

Each embodiment uses these completion notification signals selectively to improve bus transfer efficiency.
(Other variations)
Although the present invention has been described based on the above embodiment, it is needless to say that the present invention is not limited to the above embodiment. The following cases are also included in the present invention.

  (1) A part or all of the constituent elements constituting each of the above-described apparatuses may be configured by one system LSI (Large Scale Integration). The system LSI is a super multifunctional LSI manufactured by integrating a plurality of components on one chip, and specifically, a computer system including a microprocessor, a ROM, a RAM, and the like. . A computer program is stored in the RAM. The system LSI achieves its functions by the microprocessor operating according to the computer program.

In addition, each part of the constituent elements constituting each of the above devices may be individually made into one chip, or may be made into one chip so as to include a part or all of them. Further, although it is referred to as LSI here, it may be referred to as IC, system LSI, super LSI, or ultra LSI depending on the degree of integration.
Further, the method of circuit integration is not limited to LSI's, and implementation using dedicated circuitry or general purpose processors is also possible. An FPGA (Field Programmable Gate Array) that can be programmed after manufacturing the LSI or a reconfigurable processor that can reconfigure the connection and setting of circuit cells inside the LSI may be used.

Further, if integrated circuit technology comes out to replace LSI's as a result of the advancement of semiconductor technology or a derivative other technology, it is naturally also possible to carry out function block integration using this technology. Biotechnology can be applied.
Specifically, the communication source master 101, the communication destination master 102, and the memory control unit 11 may be integrally configured by one LSI.

Further, the communication source master 101 is composed of one LSI, the communication destination master 102 is composed of another one LSI, and the memory control unit 11 is composed of another one LSI. It is good.
Further, the communication source master 101 and the communication destination master 102 may be integrally configured from one LSI, and the memory control unit 11 may be configured from another single LSI.

(2) The bus communication device described above is incorporated in devices such as a digital broadcast receiving device, a DVD player, a BD player, and a mobile phone. These devices constitute a bus communication system incorporating the above-described bus communication device.
(3) The present invention may be the method described above.
(4) A bus communication device according to a first invention includes a communication source master, a communication destination master, a shared memory, and a memory control unit. The memory control unit arbitrates a memory access command from the communication source master and the communication destination master, and grants an access right to any memory access command, and a memory access command that has acquired the access right A memory access unit that accesses the shared memory, an arbitration completion notification signal generation unit that generates an arbitration completion notification signal when a memory access command from the communication source master acquires an access right, and a communication source master A memory access completion notification signal generating section for generating a memory access completion notification signal when processing of the memory access command is completed; The communication source master programmatically selects a first command issuing unit that issues a memory access command for writing target data to the shared memory, and an arbitration completion notification signal or a memory access completion notification signal, and commands based on the selected signal A completion notification control unit for generating an issue permission signal. The communication destination master includes a second command issuing unit that issues a memory access command for reading target data from the shared memory based on a command issue permission signal.

In this configuration, the arbitration completion notification signal or the memory access completion notification signal is selected in a programmable manner, and a command issue permission signal is generated. Therefore, the communication destination is more flexible than the conventional technology that uses only the memory access completion notification signal. It becomes possible to control the command generation timing of the master.
The bus communication device according to the second invention includes a communication source master, a communication destination master, a shared memory, and a memory control unit. The memory control unit includes a memory access unit that accesses a shared memory based on a memory access command from a communication source master or a communication destination master. The communication source master generates a command generation instruction signal and a command generation instruction signal when a memory access command is issued, and a first command issuing unit that issues a memory access command for writing target data to the shared memory And a completion notification control unit for generating a second-stage command issuance permission signal with a time difference. The communication destination master includes a second command issuing unit that generates a memory access command for reading target data from the shared memory based on a command generation instruction signal and issues the generated memory access command based on a command issue permission signal. .

In this configuration, since the memory access command generation of the communication destination master is started in advance when the command generation instruction signal is received, the command generation is performed earlier than the generation is started when the command issue permission signal is received. Completion of the command can be performed early.
Further, in the bus communication device according to the third invention, the memory control unit arbitrates a memory access command from the communication source master and the communication destination master, and assigns an access right to any of the memory access commands; An arbitration completion notification signal generator for generating an arbitration completion notification signal when the memory access command from the communication source master acquires an access right, and a memory when the processing of the memory access command from the communication source master is completed. A memory access completion notification signal generation unit for generating an access completion notification signal; The memory access unit is configured to access the shared memory based on the memory access command that has acquired the access right. The completion notification control unit is configured to select an arbitration completion notification signal or a memory access completion notification signal in a programmable manner and generate a command issue permission signal based on the selected signal.

In this configuration, the arbitration completion notification signal or the memory access completion notification signal is programmably selected as a trigger for generating the command issue permission signal, so that the degree of freedom in controlling the command generation timing of the communication destination master is improved.
In the bus communication device according to the fourth invention, the communication source master further includes a master information table capable of setting information indicating which master has the highest priority authority in the arbitration unit. The completion notification control unit refers to the master information table, selects the memory access completion notification signal when the transfer destination master has the highest priority authority, and selects the memory access completion notification signal when the transfer destination master does not have the highest priority authority. And an arbitration completion notification signal is selected.

Here, if the communication destination master has the highest priority authority, if the communication destination master command is subject to arbitration before the transfer of the communication source master is completed, the execution order of the communication source command and the communication destination command will be Data coherency cannot be maintained because of the possibility of reverse.
In this configuration, when the transfer destination master has the highest priority authority, the command issue permission signal is generated based on the memory access completion notification signal, so that data coherency can be maintained.

On the other hand, if the communication destination master does not have the highest priority authority in the arbitration unit, the communication source command can be issued even if the communication destination command is issued in advance, after the communication source master command is adjusted by the arbitration unit. Since the order of execution of the communication destination commands does not change after execution of the data, data coherency is maintained.
In this way, by selecting the trigger that generates the command issuance permission signal based on whether or not the communication destination master has the highest priority authority in the arbitration unit, the bus transfer efficiency can be improved while ensuring data coherency. It becomes possible to improve.

  In the bus communication device according to the fifth invention, the communication source master further includes a slave attribute information table capable of setting information indicating which area of the shared memory has the highest priority authority in the arbitration unit. The completion notification unit refers to the slave attribute information table, selects the memory access completion notification signal when the access target area has the highest priority authority, and selects the memory access completion notification signal when the access target area does not have the highest priority authority. Is configured to select an arbitration completion notification signal.

In this configuration, it is possible to improve the bus transfer efficiency while ensuring data coherency by selecting the trigger that generates the command issue permission signal based on whether the access target area has the highest priority authority. It becomes possible.
According to the present invention, a communication destination command can be issued at an early stage, and bus transfer efficiency can be improved.

  (5) The above embodiment and the above modifications may be combined.

  The present invention is useful in a system LSI that performs data bus communication using a shared memory. It is also useful for applications such as network communication such as data transfer between a network chip and a CPU.

Configuration diagram of bus communication device 10 in the present invention Internal configuration diagram of memory control unit 11 according to the first embodiment Internal configuration diagram of arbitration unit 21 in the first embodiment Internal configuration diagram of memory access unit 22 in the first embodiment Configuration diagram of communication source master 101 and communication destination master 102 in the first embodiment Configuration diagram of bus communication setting register 55 in the first embodiment Configuration diagram of master information table 71 in the first embodiment Configuration diagram of slave attribute information table 81 in the second embodiment Configuration diagram of communication source master 101 and communication destination master 102 in the fourth embodiment Configuration diagram of bus communication device 10 in the first to third embodiments Configuration diagram of bus communication device 10 in Embodiments 4 to 6 FIG. 3 is a sequence diagram of the bus communication device 10 according to the first embodiment. Continued to FIG. 13 or FIG. FIG. 3 is a sequence diagram of the bus communication device 10 according to the first embodiment. Continuing from FIG. FIG. 3 is a sequence diagram of the bus communication device 10 according to the first embodiment. Continuing from FIG. FIG. 10 is a sequence diagram of the bus communication device 10 according to the second embodiment. FIG. 11 is a sequence diagram of the bus communication device 10 according to the third embodiment. FIG. 10 is a sequence diagram of the bus communication device 10 according to the fourth embodiment. Continued to FIG. 18 or FIG. FIG. 10 is a sequence diagram of the bus communication device 10 according to the fourth embodiment. It continues from FIG. FIG. 10 is a sequence diagram of the bus communication device 10 according to the fourth embodiment. It continues from FIG. FIG. 10 is a sequence diagram of the bus communication device 10 according to the fifth embodiment. FIG. 17 is a sequence diagram of the bus communication device 10 according to the sixth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Bus communication apparatus 101 Communication origin master 102 Communication destination master 11 Memory control part 12 Shared memory 13 Communication bus 14 Memory bus 201, 202 Memory access command holding part 21 Arbitration part 22 Memory access part 31 Arbitration completion notification signal generation part 41 Memory access Completion notification signal generation unit 51, 54 Memory access command generation unit 52 Completion notification control unit 53 Command issue permission signal reception unit 55 Bus communication setting register 71 Master information table 81 Slave attribute information table

Claims (12)

A bus communication device,
Shared memory,
(A) arbitrating a plurality of commands indicating access to the shared memory, granting an access right to any command, (b) outputting an arbitration completion signal indicating that arbitration has been completed for the command; (C) Access to the shared memory is performed based on a command to which an access right is given, and (d) an access completion signal indicating completion of access to the shared memory when access to the shared memory by the command is completed A memory control unit for outputting
A write signal indicating writing of the target data to the shared memory is output, the arbitration completion signal or the access completion signal is selected programmably, and a permission signal indicating permission to issue a command based on the selected completion signal Communication source master that outputs
A bus communication apparatus comprising: a communication destination master that outputs a read command indicating reading of the target data from the shared memory based on the permission signal. The communication source master outputs a generation instruction signal instructing generation of the read command together with the output of the write command, and after the generation instruction signal is output, indicates permission to issue the read command with a time difference. Outputting the permission signal;
The bus communication device according to claim 1, wherein the communication destination master generates the read command based on the generation instruction signal and outputs the generated read command based on the permission signal. The memory control unit
A command arbitration unit that arbitrates a plurality of commands indicating access to the shared memory and grants an access right to any command;
A memory access unit that accesses the shared memory based on a command that has acquired an access right;
An arbitration completion signal output unit that outputs the arbitration completion signal when any command acquires an access right;
An access completion signal output unit for generating the access completion signal when the access to the shared memory by the command having acquired the access right is completed,
The communication source master is
A command output unit for outputting the write command;
The bus communication apparatus according to claim 1, further comprising: a completion notification control unit that programmably selects the arbitration completion signal or the access completion signal and outputs the permission signal based on the selected completion signal. The communication source master further includes:
Corresponding to each master, including a master information table storing the highest priority information indicating whether the master has the highest priority authority in the command arbitration unit,
The completion notification control unit determines whether or not the transfer destination master has the highest priority authority using the highest priority information stored in the master information table and corresponding to the transfer destination master. 4. The access completion signal is selected if the access master has the highest priority authority, and the arbitration completion signal is selected if the transfer destination master does not have the highest priority authority. The bus communication device described. The communication source master further includes:
Corresponding to each master, for each area constituting the shared memory, including a slave attribute information table storing the highest priority information indicating whether the access by the master to the area has the highest priority authority,
The completion notification control unit is stored in the slave attribute information table and uses the highest priority information on the area to be accessed by the transfer destination master, so that the area to be accessed by the transfer destination master is the highest. It is determined whether or not it has priority authority, and if the area has the highest priority authority, the access completion signal is selected, and if the area does not have the highest priority authority, the arbitration completion signal is The bus communication device according to claim 3, wherein the bus communication device is selected. The communication source master further includes:
In correspondence with each master, a master information table storing first highest priority information indicating whether or not the master has the highest priority authority in the command arbitration unit;
Corresponding to each master, for each area constituting the shared memory, a slave attribute information table storing second highest priority information indicating whether access to the area by the master has the highest priority authority; Including
The completion notification control unit (a) uses the first highest priority information stored in the master information table and corresponding to the transfer destination master to determine whether the transfer destination master has the highest priority authority. (B) Using the second highest priority information on the area that is stored in the slave attribute information table and that is to be accessed by the transfer destination master, the area that is to be accessed by the transfer destination master has the highest priority. (C) if the transfer destination master does not have the highest priority authority and the area does not have the highest priority authority, the arbitration completion signal is selected; (D) When the communication destination master has the highest priority authority, or when the communication destination master does not have the highest priority authority and the area has the highest priority authority, the access completion signal is selected. That features The bus communication device according to claim 3. A control method used in a bus communication device composed of a shared memory, a memory control unit, a communication source master and a communication destination master,
In the communication source master, outputting a write command indicating writing of the target data to the shared memory;
In the memory control unit, arbitrating a plurality of commands indicating access to the shared memory, and granting an access right to any command;
In the memory control unit, outputting an arbitration completion signal indicating that arbitration has been completed for the command;
In the memory control unit, accessing the shared memory based on a command to which an access right is granted;
Outputting an access completion signal indicating completion of access to the shared memory when access to the shared memory by the command is completed in the memory control unit;
In the communication source master, the arbitration completion signal or the access completion signal is programmably selected, and based on the selected completion signal, outputting a permission signal indicating permission to issue a command;
And a step of outputting a read command indicating reading of the target data from the shared memory based on the permission signal in the communication destination master. An integrated circuit,
(A) Arbitrate a plurality of commands indicating access to the shared memory, grant an access right to any of the commands, (b) output an arbitration completion signal indicating that the arbitration has been completed for the command, ( c) accessing the shared memory based on the command to which the access right is given, and (d) when an access to the shared memory by the command is completed, an access completion signal indicating completion of the access to the shared memory A memory control unit to output;
A write signal indicating writing of the target data to the shared memory is output, the arbitration completion signal or the access completion signal is selected programmably, and a permission signal indicating permission to issue a command based on the selected completion signal Communication source master that outputs
An integrated circuit, comprising: a communication destination master that outputs a read command indicating reading of the target data from the shared memory based on the permission signal. A memory control circuit,
A command arbitration unit that arbitrates a plurality of commands indicating access to the shared memory and grants an access right to any command;
A memory access unit that accesses the shared memory based on a command that has acquired an access right;
An arbitration completion signal output unit that outputs an arbitration completion signal indicating that arbitration has been completed for the command when any command has acquired an access right;
An access completion signal output unit for generating an access completion signal indicating completion of access to the shared memory when access to the shared memory by the command having acquired the access right is completed. circuit. A master circuit,
A command output unit for outputting a write command indicating writing of target data to the shared memory;
A completion notification control unit that programmably selects the arbitration completion signal or the access completion signal output from the memory control circuit according to claim 9, and outputs the permission signal based on the selected completion signal. Master circuit to perform. A bus communication device,
Shared memory,
(A) arbitrating a plurality of commands indicating access to the shared memory, granting an access right to any command, (b) outputting an arbitration completion signal indicating that arbitration has been completed for the command; (C) Access to the shared memory is performed based on a command to which an access right is given, and (d) an access completion signal indicating completion of access to the shared memory when access to the shared memory by the command is completed A memory control unit for outputting
Outputting a write command indicating writing of target data to the shared memory and a generation instruction signal instructing generation of a read command indicating reading of the target data from the shared memory, and after outputting the generation instruction signal, A communication source master that outputs an issue permission signal indicating permission to issue the read command with a time difference;
A bus communication device comprising: a communication destination master that generates the read command based on the generation instruction signal and outputs the generated read command based on the issue permission signal. A bus communication device,
Shared memory,
A command that grants an access right by arbitrating a plurality of commands indicating access to the shared memory, granting an access right to any command, outputting an arbitration completion signal indicating that the arbitration has been completed for the command. A memory control unit for accessing the shared memory based on
(A) outputting a write command indicating writing of the target data to the shared memory; (b) determining whether or not the access relating to the write command has the highest priority authority in the arbitration; c) a communication source master that outputs a permission signal indicating permission to issue a command after receiving the arbitration completion signal for the write command when it is determined that the authority has the highest priority;
A bus communication apparatus comprising: a communication destination master that outputs a read command indicating reading of the target data from the shared memory when the permission signal is received.

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