JP2007193393A - Data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processor capable of quickly carrying out changing of a clock frequency in the data processor, and capable of raising the clock frequency only when data processing capacity increase is needed, and lowering the clock frequency when data processing capacity increase is not needed. <P>SOLUTION: The data processor is provided with a dack counter 21 counting the number of times of data transfer acknowledgement in a certain period, a register 24 storing a reference value, a comparator 25 comparing a count value of the dack counter 21 with the value of the register 24, and a clock supply circuit changing an operation clock frequency in the data processor to a first operation clock frequency when a pulse number of data transfer acknowledgement in the certain period is the reference value or more on the basis of output of the comparator 25, and changing it to a second operation clock frequency lower than the first operation clock frequency when the pulse number is less than the reference value. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data processing apparatus, and more particularly to a technique effective when applied to the operation clock switching control.

  2. Description of the Related Art Conventionally, a data processing apparatus configured with a synchronization circuit includes various functional circuit blocks that perform an operation of taking in a data input signal supplied to itself in synchronization with a clock signal. Is configured to be supplied with a constant clock signal at all times.

  However, when the circuit scale is increased and the operation speed is increased, a large amount of power is consumed only by the constant input of the clock signal.

  Japanese Patent Application Laid-Open No. 7-99434 (Patent Document 1) includes means for determining whether or not a predetermined functional block is in operation and means for supplying a clock only when the predetermined functional block is in operation. Provided, the clock supply is stopped during non-operation.

Japanese Patent Laid-Open No. 9-16424 (Patent Document 2) includes an oscillation unit that generates different clock frequencies, a clock cycle selection unit that selects a clock frequency, a temperature sensor, and a control unit, and the clock cycle selection unit has a high temperature. In this case, a low clock frequency is selected, and when the temperature is low, a high clock frequency is selected.
Japanese Unexamined Patent Publication No. 7-99434 JP-A-9-16424

  By the way, in general, a data processing apparatus is operated at a constant clock frequency, but there are cases where the clock frequency can be increased or decreased as necessary. For example, an optical disc recording / reproducing apparatus generally uses a memory for data processing. However, the bandwidth required for the memory varies greatly depending on the double speed of the disk recording / reproducing, and the necessary bandwidth for the high double speed recording / reproducing is low. Since there is a case where the recording / reproducing has an excessive bandwidth, if the clock frequency is lowered and the bandwidth is suppressed at the time of low-speed recording / reproducing, the power consumption can be further reduced.

  However, conventionally, the control of the clock frequency is controlled by monitoring the state of the data processing device using a microcomputer connected to the data processing device and sending a control signal of the clock frequency to the data processing device, It was not possible to change the clock frequency at high speed.

  Therefore, an object of the present invention is to change the clock frequency at high speed in the data processing apparatus, increase the clock frequency only when the data processing capability needs to be increased, and if the data processing capability does not need to be increased, the clock frequency is increased. It is an object of the present invention to provide a data processing apparatus capable of decreasing the frequency.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A data processing apparatus according to the present invention is a data processing apparatus for processing input data, and includes a counter for counting the number of pulses of a data transfer approval signal for a certain period generated in the data processing apparatus, and a data transfer approval for a certain period. A register that stores the reference value of the signal count value, a comparison circuit that compares the count value of the counter and the register value, and an output of the comparison circuit are input, and the operation clock frequency in the data processing device is set to When the number of pulses of the transfer approval signal is greater than or equal to the reference value, the frequency is switched to the first operation clock frequency. When the number of pulses of the data transfer approval signal for a certain period is less than the reference value, the second lower than the first operation clock frequency. And a clock supply circuit for switching to the operating clock frequency.

  The data processing apparatus according to the present invention is a data processing apparatus for processing input data, the counter for counting the number of pulses of a data transfer approval signal for a certain period generated in the data processing apparatus, and the data for a certain period A plurality of registers for storing reference values having different count values of the transfer approval signal, a multiplexer for switching the plurality of registers, a comparison circuit for comparing the output value of the multiplexer with the value of the counter, and a rising edge of the output signal of the comparison circuit The rise detection circuit to detect, the fall detection circuit to detect the falling edge of the output signal of the comparison circuit, and set and reset by the output signal from the rise detection circuit and the fall detection circuit to control the switching of the multiplexer Cut off by RS flip-flop and RS flip-flop The output of the comparison circuit to which the changed register value is input is input, and the operation clock frequency in the data processing device is changed from the first operation clock frequency to the second operation clock frequency lower than the first operation clock frequency. A clock supply circuit that uses the first reference value when switching and uses the second reference value when switching from the second operation clock frequency to the first operation clock frequency, and a clock supply circuit that switches the operation clock frequency It is.

  The data processing apparatus according to the present invention is a data processing apparatus for processing input data, the counter for counting the number of pulses of a data transfer approval signal for a certain period generated in the data processing apparatus, and the data for a certain period A plurality of registers for storing different reference values for the count value of the transfer approval signal, a multiplexer for switching between the plurality of registers, a comparison circuit for comparing the output value of the multiplexer with the value of the counter, and the output of the comparison circuit at regular intervals A D flip-flop to store, an AND circuit that performs a logical product of the value of the D flip-flop and the output of the comparison circuit, an OR circuit that performs a logical sum of the value of the D flip-flop and the output of the comparison circuit, and an output signal of the AND circuit A rising edge detection circuit that detects the rising edge of the OR circuit and a falling edge that detects the falling edge of the output signal of the OR circuit The detection circuit, the RS flip-flop for setting and resetting by the output signals from the rise detection circuit and the fall detection circuit, and controlling the switching of the multiplexer, and the output of the RS flip-flop are input, and the operation clock in the data processing device When switching the frequency from the first operation clock frequency to the second operation clock frequency lower than the first operation clock frequency, the first reference value is used, and the second operation clock frequency is changed to the first operation clock frequency. When switching, the second reference value is used. Further, when the number of pulses of the data transfer approval signal in a certain period is more than the second reference value, it is switched to the first operation clock frequency and the constant The number of pulses of the data transfer approval signal during the period may be less than the first reference value multiple times If it is obtained by a clock supply circuit for switching the second operating clock frequency.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, since the clock frequency can be changed in the data processing device based on the number of pulses of the data transfer approval signal in the data processing device, the clock frequency can be changed at high speed, Since the clock frequency is increased only when the data processing capability needs to be increased, and the clock frequency is decreased when the data processing capability is not increased, the power consumption can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
<Configuration of data processing apparatus>
The configuration of the data processing apparatus according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of a data processing apparatus according to Embodiment 1 of the present invention, and shows a case where the data processing apparatus is applied to a DVD (Digital Versatile Disc) playback drive.

  In FIG. 1, the data processing apparatus includes a demodulation circuit 1, an error correction circuit 2, a descrambling circuit 3, a memory control circuit 4, a memory 5, a clock oscillation circuit 6, a frequency dividing circuit 7, a multiplexer 8, and a clock control circuit 9. Has been.

  The demodulating circuit 1 demodulates the data (in_data) input from the disk by 8/16 and writes it to the memory 5 via the memory control circuit 4.

  The error correction circuit 2 reads the data written in the memory 5 through the memory control circuit 4 and writes the data subjected to error correction into the memory 5.

  The descrambling circuit 3 reads out the error-corrected data from the memory 5 via the memory control circuit 4, and scrambles and outputs it to the host computer (out_data).

  In response to data transfer requests (dem_dreq, ecc_dreq, dsc_dreq) from the demodulating circuit 1, the error correction circuit 2, and the descrambling circuit 3, the memory control circuit 4 receives data transfer acknowledge signals (dem_dack, ecc_dack, dsc_dack). ) To input / output data to / from the memory 5.

  The clock oscillation circuit 6 outputs a clock for operating the data processing device.

  The frequency dividing circuit 7 divides the clock output from the clock oscillation circuit 6 by ½.

  The multiplexer 8 selects and outputs the clock output from the clock oscillation circuit 6 and the clock output from the frequency divider circuit 7.

  The clock control circuit 9 monitors the data transfer acknowledge (dem_dack, ecc_dack, dsc_dack) and controls the multiplexer 8 to select an optimum operation clock.

  The clock oscillation circuit 6, the frequency divider circuit 7, and the multiplexer 8 constitute a clock supply circuit.

  When the data transfer request (dem_dreq, ecc_dreq, dsc_dreq) is output from the demodulation circuit 1, the error correction circuit 2, and the descrambling circuit 3, the memory control circuit 4 receives data transfer acknowledges (dem_dack, ecc_dack, dsc_dack) is output and data is input / output to / from the memory 5. This data transfer acknowledge can be monitored by the clock control circuit 9 to select an optimum operation clock for the data processing apparatus at that time.

<Configuration and operation of clock control circuit>
Next, the configuration and operation of the clock control circuit of the data processing apparatus according to the first embodiment of the present invention will be described with reference to FIG. FIG. 2 is a block diagram showing the configuration of the clock control circuit of the data processing apparatus according to Embodiment 1 of the present invention.

  In FIG. 2, the clock control circuit 9 includes an OR circuit 20, a duck counter 21, a clock counter 22, an inverting circuit 23, a register 24, a comparator 25 as a comparison circuit, and a delay circuit 26.

  The OR circuit 20 performs a logical OR of the data transfer acknowledges (dem_dack, ecc_dack, dsc_dack) output from the memory control circuit 4 to the demodulation circuit 1, the error correction circuit 2, and the descrambling circuit 3, and outputs the result to the dack counter 21. .

  The duck counter 21 counts and outputs a data transfer acknowledge for a certain period. For example, a count value counted within a certain period is output after a certain time has elapsed.

  The clock counter 22 counts the operation clock and outputs a carry signal to the dack counter 21 for every predetermined period (a constant number of clocks).

  The inverting circuit 23 inverts the carry signal output from the clock counter 22 and inputs it to the reset of the duck counter 21.

  The register 24 sets a value to be compared with the deck counter 21 by the comparator 25.

  The comparator 25 compares the output values of the duck counter 21 and the register 24, and outputs “0” when the value of the duck counter 21 is less than the value of the register 24. The value of the duck counter 21 becomes equal to or greater than the value of the register 24. Output "1".

  The delay circuit 26 adjusts the delay to an optimal timing for clock switching when the output of the comparator 25 is output to the multiplexer 8 to switch the clock.

  The optimum timing is, for example, the data transfer end timing. Generally, since the data transfer length is different for each block, a data transfer acknowledge (dem_dack, ecc_dack, dsc_dack) is input to the delay circuit 26. To switch the delay amount.

  The delay circuit 26 can be composed of a shift register, and the delay amount can be switched by changing the number of stages of the shift register.

  As for the operation of the clock control circuit 9, first, when any of the data transfer acknowledges (dem_dack, ecc_dack, dsc_dack) is input to the clock control circuit 9, the duck counter 21 advances, and when the value of the register 24 is exceeded, the clock control is performed. The signal (clk_sel) becomes “1”.

  Since the clock counter 22 counts the clock and the dack counter 21 is reset by the carry signal of the clock counter 22 and always counts for a certain period, the clock control circuit 9 monitors the data transfer acknowledge for a certain period. Thus, the clock control signal (clk_sel) can be switched.

<Operation of data processing apparatus>
Next, the operation of the data processing apparatus according to the first embodiment of the present invention will be described with reference to FIG. FIG. 3 is a timing chart for explaining the operation of the clock control circuit of the data processing apparatus according to the first embodiment of the present invention, and shows input / output signals and internal signals of the clock control circuit 9 shown in FIG. .

  Dem_dreq, ecc_dreq, and dsc_dreq are data transfer requests from the demodulation circuit 1, the error correction circuit 2, and the descrambling circuit 3.

  Dem_dack, ecc_dack, and dsc_dack are data transfer acknowledges to the demodulation circuit 1, the error correction circuit 2, and the descrambling circuit 3.

  Since the demodulating circuit 1 demodulates and outputs the input data by 8/16, a data transfer request is generated at a constant period corresponding to the rotational speed of the disk.

  Further, since error correction of a DVD is performed after data for one block (32 kbytes) is stored in the memory, the error correction circuit 2 generates data transfer requests intensively for each block stored in the memory. The descrambling is performed when data is sent to the host computer. There are several methods for selecting the output of each data transfer acknowledge when each data transfer request is generated at the same time. Here, it is assumed that the priority order is determined as dem_dreq> ecc_dreq> dsc_dreq.

  dem∪ecc∪dsc_dack is a logical sum signal of each data transfer acknowledge, and becomes “1” when even one data transfer acknowledge is “1”.

  “source” is an oscillation clock output from the clock oscillation circuit 6, and “source / 2” is a 1/2 frequency-divided clock output from the frequency-dividing circuit 7.

  clock is a clock selected by the multiplexer 8.

  count1 is the count value of the clock counter 22, counts from "0" to "7", and outputs a carry at "7".

  count2 is the count value of the duck counter 21, and the carry of the output of the clock counter 22 is inverted and input to the reset. Therefore, when the carry becomes "1", the count value is reset to "0".

  count3 is a count value output from the duck counter 21, and outputs a count value for a certain period from when the carry becomes "1" and the count value is reset to "0" until the next reset. Yes.

  In the example shown in FIG. 3, the count value is output for a certain period at the end of the certain period, that is, when the carry becomes “1” and the count value is reset to “0”. If the count value increases, the output of the count value may be increased at that time.

  If the count value within a certain period is 0, the carry becomes “1”, and the count value count3 output from the duck counter 21 becomes “0” when the count value is reset to “0”.

  Comp is an output of the comparator 25, compares count2 with a register value, outputs "0" when count2 is less than the register value, and outputs "1" when count2 is equal to or greater than the register value.

  When the register value is “2”, “1” is output when count2 = “2” or more.

  clk_sel is a clock switching signal obtained by delaying comp and is output to the multiplexer 8 to switch between source and source / 2.

  When clk_sel = “0”, clock = source / 2, and when clk_sel = “1”, clock = source.

  First, at timing 1, the data transfer request (dem_dreq) becomes “1”, and data transfer is requested from the demodulation circuit 1.

  At timing 2, the data transfer acknowledge (dem_dack) becomes “1” and the data transfer is approved for the demodulator circuit 1, so the demodulator circuit 1 transfers the data to the memory control circuit 4.

  When the data transfer is completed, the data transfer request (dem_dreq) becomes “0”.

  This data transfer sets the duck counter to “1”, but the register setting is “2”, so the comparator output remains “0” and the operation clock remains at source / 2.

  At timing 3, the data transfer request (ecc_dreq) becomes “1”, and data transfer is requested from the error correction circuit 2.

  At timing 4, the data transfer acknowledge (ecc_dack) becomes “1” and the data transfer is approved for the error correction circuit 2, so that the error correction circuit 2 transfers the data to the memory control circuit 4. Until the data transfer is completed, the data transfer request (ecc_dreq) remains “1”.

  Even at timing 5, the data transfer acknowledge (ecc_dack) becomes “1”, and the error correction circuit 2 transfers data to the memory control circuit 4.

  Due to these data transfers, the count of the duck counter 21 becomes “2”, and the carry counter from the clock counter 22 makes the output of the duck counter 21 “2”, which matches the register set value, so that the output of the comparator 25 is When it becomes “1” and subsequently clk_sel becomes “1”, the operation clock is switched to the source, and the data processing capability of each data processing circuit in the data processing device and the memory bandwidth are doubled.

  At timing 5, the data transfer request (dem_dreq) again becomes “1”, and data transfer is requested from the demodulation circuit 1.

  As described above, since dem_dreq has a higher priority than ecc_dreq, the data transfer acknowledge (dem_dack) becomes “1” at timing 6, the data transfer is approved to the demodulator circuit 1, and the demodulator circuit 1 receives the memory control circuit 4. Data transfer to When the data transfer is completed, the data transfer request (dem_dreq) becomes “0”.

  As long as the output of the duck counter 21 continues to be “2” or more, the output of the comparator 25 remains “1”, the operation clock remains source, and the data processing capability of each data processing circuit in the data processing device and the memory Continue to maintain double bandwidth.

  When the output of the duck counter 21 becomes less than “2”, the output of the comparator 25 returns to “0”, whereby the operation clock returns to source / 2, and the data processing of each data processing circuit in the data processing device Capability and memory bandwidth are halved.

  As described above, in the present embodiment, the number of docks for each fixed period is counted, and the operation clock frequency is increased only when the data processing capacity needs to be increased by switching the frequency of the operation clock according to the number of decks. When the increase is not necessary, the operation clock frequency is lowered, so that power consumption can be reduced.

(Embodiment 2)
<Configuration of data processing apparatus>
The configuration of the data processing apparatus according to the second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a block diagram showing the configuration of the data processing apparatus according to the second embodiment of the present invention, and the description of the same parts as those in the first embodiment is omitted.

  In FIG. 4, the data processing apparatus includes a demodulation circuit 1, an error correction circuit 2, a descrambling circuit 3, a memory control circuit 4, a memory 5, a clock oscillation circuit 6, a frequency dividing circuit 40, a multiplexer 41, and a clock control circuit 42. Has been.

  The frequency dividing circuit 40 divides the clock output from the clock oscillation circuit 6 into 1/2 and 1/4.

  The multiplexer 41 selects and outputs the clock output from the clock oscillation circuit 6 and the clock output from the frequency dividing circuit 40.

  The clock control circuit 42 monitors the data transfer acknowledge (dem_dack, ecc_dack, dsc_dack), controls the multiplexer 41, and selects an optimum operation clock.

  When a data transfer request (dem_dreq, ecc_dreq, dsc_dreq) is output from the demodulation circuit 1, the error correction circuit 2, and the descrambling circuit 3, the memory control circuit 4 outputs a data transfer acknowledge (dem_dack, ecc_dack, dsc_dack), Data input / output to / from the memory 5 is performed. The clock control circuit 42 can monitor this data transfer acknowledge and select an optimum operation clock for the data processing apparatus at that time.

<Configuration and operation of clock control circuit>
Next, the configuration and operation of the clock control circuit of the data processing apparatus according to the second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a block diagram showing the configuration of the clock control circuit of the data processing apparatus according to the second embodiment of the present invention, and the description of the same parts as those in the first embodiment is omitted.

  In FIG. 5, the clock control circuit 42 includes an OR circuit 20, a duck counter 21, a clock counter 22, an inverting circuit 23, a register 24, a comparator 25, a delay circuit 26, a register 51, a comparator 52, and a delay circuit 53. .

  The register 51 sets a value to be compared with the duck counter 21 by the comparator 52.

  The comparator 52 compares the output values of the duck counter 21 and the register 51, and outputs “0” when the value of the duck counter 21 is less than the value of the register 51. The value of the duck counter 21 becomes equal to or greater than the value of the register 51. Output "1".

  When the delay circuit 53 outputs the output of the comparator 52 to the multiplexer 41 to switch the clock, the delay circuit 53 adjusts the delay to the optimum timing for the clock switching.

  The optimal timing is, for example, the data transfer end timing. However, since the data transfer length is generally different for each block, a data transfer acknowledge (dem_dack, ecc_dack, dsc_dack) is input to the delay circuit 53, To switch the delay amount.

  The delay circuit 53 can be composed of a shift register, and the delay amount can be switched by changing the number of stages of the shift register.

  Here, as an example, “2” is set in the register 24 and “3” is set in the register 51.

  As for the operation of the clock control circuit 42, first, when any of the data transfer acknowledges (dem_dack, ecc_dack, dsc_dack) is input to the clock control circuit 42, the duck counter 21 advances, and the output of the duck counter 21 is the value of the register 24. When it becomes above, the clock control signal (clk_sel) becomes “1”, and when it becomes more than the value of the register 51, the clock control signal (clk_se2) becomes “1”.

  Specifically, the clock control signal (clk_sel) becomes “1” when the output of the duck counter 21 becomes equal to or greater than the value “2” of the register 24.

  When the output of the duck counter 21 becomes equal to or greater than the value “3” of the register 51, the clock control signal (clk_sel2) also becomes “1”.

  clk_sel2 is a clock switching signal obtained by delay-adjusting the output comp2 of the comparator 52, and is output to the multiplexer together with clk_sel to switch between source, source / 2, and source / 4.

  When clk_sel = clk_sel2 = “0”, clock = source / 4, and when clk_sel = “1” and clk_sel2 = “0”, clock = source / 2. When clk_sel = clk_sel2 = “1”, clock = source.

  As described above, in the present embodiment, as in the first embodiment, the number of docks per predetermined period is counted, and the operation clock frequency is switched only when the data processing capability needs to be increased by switching the frequency of the operation clock according to the number of docks. When the data processing capability is not required to be increased, the operation clock frequency is decreased, so that power consumption can be reduced.

  Furthermore, in this embodiment, by providing a plurality of comparison circuits and registers, the clock frequency can be switched to three or more stages instead of two stages with respect to the first embodiment.

(Embodiment 3)
<Configuration and operation of clock control circuit>
Next, the configuration and operation of the clock control circuit of the data processing apparatus according to the third embodiment of the present invention will be described with reference to FIG. FIG. 6 is a block diagram showing the configuration of the clock control circuit of the data processing apparatus according to the third embodiment of the present invention, and the description of the same parts as those in the first embodiment is omitted. The configuration and operation of the data processing device other than the clock control circuit are the same as those in the first embodiment.

  In FIG. 6, the clock control circuit 60 includes an OR circuit 20, a duck counter 21, a clock counter 22, an inverting circuit 23, a register 24, a comparator 25, a delay circuit 26, a D flip-flop 61, and an AND circuit 62.

  The clock control circuit 60 monitors the data transfer acknowledges (dem_dack, ecc_dack, dsc_dack) in the data processing device and controls the multiplexer 8 to select an optimum operation clock.

  The D flip-flop 61 takes in the output comp of the comparator 25 at the timing of the carry signal of the clock counter 22.

  The AND circuit 62 outputs a logical product of the output comp of the comparator 25 and the output of the D flip-flop 61.

  As for the operation of the clock control circuit 60, first, when any of the data transfer acknowledges (dem_dack, ecc_dack, dsc_dack) is input to the clock control circuit 60, the duck counter 21 advances, and the output of the duck counter 21 is the value of the register 24. When this is the case, the output comp of the comparator 25 becomes “1”. Since the output comp of the comparator 25 is connected to the D flip-flop 61 and the AND circuit 62, the clock control signal (clk_sel) is not detected until the output comp of the comparator 25 becomes “1” twice at the timing of the carry signal. Becomes “1”.

  Specifically, when the output of the duck counter 21 becomes equal to or greater than the value “2” of the register 24, the output comp of the comparator 25 becomes “1”, but since the output of the D flip-flop 61 is “0”, the clock The control signal (clk_sel) remains “0”.

  Then, when the carry signal of the clock counter 22 is input to the D flip-flop 61, since the output “1” of the comparator 25 is input to the D flip-flop 61, the output of the D flip-flop 61 is “ If the output comp of the comparator 25 is “1” at that time, the clock control signal (clk_sel) becomes “1”.

  As described above, in the present embodiment, as in the first embodiment, the number of docks per predetermined period is counted, and the operation clock frequency is switched only when the data processing capability needs to be increased by switching the frequency of the operation clock according to the number of docks. When the data processing capability is not increased, the clock frequency is decreased, so that power consumption can be reduced.

  Furthermore, in this embodiment, the clock frequency is increased only when the register value is reached twice in succession, so that it is possible to prevent the clock frequency from repeatedly increasing and decreasing.

  In this embodiment, the case where there is one comparison circuit has been described as an example. However, by providing a plurality of comparison circuits and registers, the clock frequency can be switched to three or more stages instead of two stages.

(Embodiment 4)
<Configuration and operation of clock control circuit>
Next, the configuration and operation of the clock control circuit of the data processing apparatus according to the fourth embodiment of the present invention will be described with reference to FIG. FIG. 7 is a block diagram showing the configuration of the clock control circuit of the data processing apparatus according to the fourth embodiment of the present invention, and the description of the same parts as those in the first and third embodiments is omitted. The configuration and operation of the data processing device other than the clock control circuit are the same as those in the first embodiment.

  In FIG. 7, the clock control circuit 70 includes an OR circuit 20, a duck counter 21, a clock counter 22, an inverting circuit 23, a register 24, a comparator 25, a delay circuit 26, a D flip-flop 61, and an OR circuit 71.

  The clock control circuit 70 monitors the data transfer acknowledge (dem_dack, ecc_dack, dsc_dack) in the data processing device, controls the multiplexer, and selects an optimum operation clock.

  The OR circuit 71 outputs a logical sum of the output comp of the comparator 25 and the output of the D flip-flop 61.

  As for the operation of the clock control circuit 70, first, when any of the data transfer acknowledges (dem_dack, ecc_dack, dsc_dack) is input to the clock control circuit 70, the duck counter 21 advances, and the output of the duck counter 21 is the value of the register 24. Thus, after the output comp of the comparator 25 becomes “1”, when the output of the duck counter 21 becomes less than the value of the register 24, the output comp of the comparator 25 becomes “0”.

  Since the output comp of the comparator 25 is connected to the D flip-flop 61 and the OR circuit 71, the clock control signal (clk_sel) is not detected until the output comp of the comparator 25 becomes “0” twice continuously at the timing of the carry signal. Becomes “0”.

  Specifically, when the clock control signal (clk_sel) is “1” and the output of the duck counter 21 is less than the value “2” of the register 24, the output comp of the comparator 25 becomes “0”. Since the output of the D flip-flop 61 is “1”, the clock control signal (clk_sel) remains “1”.

  Then, when the carry signal of the clock counter 22 is input to the D flip-flop 61, “0” of the output comp of the comparator 25 is input to the D flip-flop 61, so that the output of the D flip-flop 61 is “ The clock control signal (clk_sel) becomes “0”.

  As described above, in the present embodiment, the number of docks for a certain period is counted in the same manner as in the first embodiment, and the clock frequency is changed only when the data processing capability needs to be increased by switching the frequency of the operation clock according to the number of docks. When the data processing capability is not increased, the clock frequency is decreased, so that the power consumption can be reduced.

  Furthermore, in this embodiment, the clock frequency is lowered only when it becomes less than the register value twice in succession, so that it is possible to prevent the clock frequency from being repeatedly raised and lowered.

  In this embodiment, the case where there is one comparison circuit has been described as an example. However, by providing a plurality of comparison circuits and registers, the clock frequency can be switched to three or more stages instead of two stages.

(Embodiment 5)
<Configuration and operation of clock control circuit>
Next, the configuration and operation of the clock control circuit of the data processing device according to the fifth embodiment of the present invention will be described with reference to FIG. FIG. 8 is a block diagram showing the configuration of the clock control circuit of the data processing apparatus according to the fifth embodiment of the present invention, and the description of the same parts as those in the first embodiment is omitted. The configuration and operation of the data processing device other than the clock control circuit are the same as those in the first embodiment.

  In FIG. 8, a clock control circuit 80 includes an OR circuit 20, a duck counter 21, a clock counter 22, an inverting circuit 23, a comparator 25, a delay circuit 26, a rising detection circuit 81, a falling detection circuit 82, an RS flip-flop 83, and a multiplexer. 84 and registers 85 and 86.

  The clock control circuit 80 monitors the data transfer acknowledge (dem_dack, ecc_dack, dsc_dack) and controls the multiplexer 8 to select an optimum operation clock.

  The rising edge detection circuit 81 outputs a “1” pulse when the rising edge of the output comp of the comparator 25 is detected.

  The falling detection circuit 82 outputs a “1” pulse when the falling edge of the output comp of the comparator 25 is detected.

  The RS flip-flop 83 is set (output “1”) by the “1” pulse from the rising edge detection circuit 81 and reset (output “0”) by the “1” pulse from the falling edge detection circuit 82.

  The multiplexer 84 selects and outputs the registers 85 and 86 based on the output of the RS flip-flop 83.

  The registers 85 and 86 set values to be compared with the duck counter 21 by the comparator 25.

  In the first embodiment, an example in which “2” is set in the register 24 is shown, but in this embodiment, “2” is set in the register 85 and “1” is set in the register 86.

  The operation of the clock control circuit 80 is as follows. First, when any of the data transfer acknowledges (dem_dack, ecc_dack, dsc_dack) is input to the clock control circuit 70 with the multiplexer 84 selecting the register 85, the duck counter 21 is operated. , The output of the duck counter 21 becomes equal to or greater than the value of the register 85, and the output comp of the comparator 25 becomes “1”. Then, the multiplexer 84 selects the register 86, and the output of the duck counter 21 is less than the value of the register 86. Then, the output comp of the comparator 25 becomes “0”.

  Specifically, when the operation clock is source / 2, the multiplexer 84 selects the register 85, and if the output of the duck counter 21 becomes “2” due to the occurrence of data transfer, the set value of the register 85 Since it coincides with “2”, the output comp of the comparator 25 becomes “1”.

  Subsequently, when the clock control signal clk_sel becomes “1”, the operation clock is switched to the source, and the data processing capability and the memory bandwidth of each data processing circuit in the data processing device are doubled.

  Further, when the output comp of the comparator 25 becomes “1”, the rising edge detection circuit 81 outputs “1”, and the RS flip-flop 83 outputs “1”. As a result, the multiplexer 84 selects the register 86, and the value compared by the comparator 25 is not the setting value “2” of the register 85 but the setting value “1” of the register 86.

  As long as the output of the duck counter 21 continues to be “1” or more, the output comp of the comparator 25 remains “1”, the operation clock remains source, and the data processing capability of each data processing circuit of the data processing device Continue to maintain twice the memory bandwidth.

  When the output of the duck counter 21 becomes less than “1”, the output comp of the comparator 25 returns to “0”, and then the clock control signal clk_sel becomes “0”, so that the operation clock is set to source / 2. Returning, the data processing capacity of each data processing circuit and the bandwidth of the memory are halved.

  Further, when the output comp of the comparator 25 becomes “0”, the falling detection circuit 82 outputs “1”, and the RS flip-flop 83 outputs “0”. As a result, the multiplexer 84 selects the register 85, and the value compared by the comparator 25 is not the set value “1” of the register 86 but the set value “2” of the register 85.

  As described above, in the present embodiment, as in the first embodiment, the number of docks is counted per fixed period, and the clock frequency is increased only when the data processing capability needs to be increased by switching the frequency of the operation clock according to the number of docks. When the data processing capability does not need to be increased, the clock frequency is lowered, so that power consumption can be reduced.

  Furthermore, in the present embodiment, by setting different values in the two registers, the reference value for increasing the clock frequency and the reference value for decreasing the clock frequency can be changed, thereby preventing the clock frequency from repeatedly increasing and decreasing unnecessarily. be able to.

  In this embodiment, the case where there is one comparison circuit has been described as an example. However, by providing a plurality of comparison circuits and registers, the clock frequency can be switched to three or more stages instead of two stages.

(Embodiment 6)
<Configuration and operation of clock control circuit>
Next, the configuration and operation of the clock control circuit of the data processing device according to the sixth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a block diagram showing the configuration of the clock control circuit of the data processing apparatus according to the sixth embodiment of the present invention, and the description of the same parts as those of the first, third, fourth, and fifth embodiments is omitted. The configuration and operation of the data processing device other than the clock control circuit are the same as those in the first embodiment.

  In FIG. 9, the clock control circuit 90 includes an OR circuit 20, a duck counter 21, a clock counter 22, an inverting circuit 23, a comparator 25, a delay circuit 26, a D flip-flop 61, an AND circuit 62, an OR circuit 71, and a rising edge detection circuit 81. , Falling detection circuit 82, RS flip-flop 83, multiplexer 84, and registers 85 and 86.

  The clock control circuit 90 monitors the data transfer acknowledge (dem_dack, ecc_dack, dsc_dack), controls the multiplexer, and selects an optimum operation clock.

  In the first embodiment, an example in which “2” is set in the register 24 is shown. However, in the sixth embodiment, “2” is set in the register 85 and “1” is set in the register 86 as in the fifth embodiment. Set.

  The operation of the clock control circuit 90 is as follows. First, when any of the data transfer acknowledges (dem_dack, ecc_dack, dsc_dack) is input to the clock control circuit 70 with the multiplexer 84 selecting the register 85, the dack counter 21 is operated. When the value of the register 85 becomes equal to or greater than the value of the register 85 and the output comp of the comparator 25 becomes “1” twice at the timing of the carry signal, the multiplexer 84 selects the register 86.

  After that, when the duck counter 21 becomes less than the value of the register 86 and the output comp of the comparator 25 continuously becomes “0” twice at the timing of the carry signal, the multiplexer 84 selects the register 85.

  Specifically, when the data processing clock is source / 2, the multiplexer 84 selects the register 85, and if the output of the dock counter 21 becomes “2” due to the occurrence of data transfer, the set value of the register 85 Since it coincides with “2”, the output comp of the comparator 25 becomes “1”.

  Further, when the output comp of the comparator 25 continues to be “1” twice, the rising edge detection circuit 81 outputs “1”, and the RS flip-flop 83 outputs “1”.

  As a result, the multiplexer 84 selects the register 86, and the value compared by the comparator 25 is not the setting value “2” of the register 85 but the setting value “1” of the register 86.

  Further, when the RS flip-flop 83 is set to “1” and the clock control signal clk_sel is set to “1”, the operation clock is switched to the source, the data processing capability of each data processing circuit of the data processing device, and the memory bandwidth. Doubles.

  As long as the duck counter 21 continues to be “1” or more, the output comp of the comparator 25 remains “1”, the operation clock remains source, the data processing capability of each data processing circuit of the data processing device and the memory Continue to maintain double bandwidth.

  When the output of the duck counter 21 becomes less than “1”, the output comp of the comparator 25 returns to “0”.

  In addition, when the output comp of the comparator 25 continues to be “0” twice, the falling detection circuit 82 outputs “1”, and the RS flip-flop 83 outputs “0”. As a result, the multiplexer 84 selects the register 85, and the value compared by the comparator 25 is not the set value “1” of the register 86 but the set value “2” of the register 85.

  Further, when the RS flip-flop 83 becomes “0” and clk_sel becomes “0”, the operation clock returns to source / 2, and the data processing capability and the memory bandwidth of each data processing circuit of the data processing device are 1. / 2 times.

  As described above, in the present embodiment, the number of docks for a certain period is counted in the same manner as in the first embodiment, and the clock frequency is changed only when the data processing capability needs to be increased by switching the frequency of the operation clock according to the number of docks. When the data processing capability is not increased, the clock frequency is decreased, so that the power consumption can be reduced.

  Further, in this embodiment, since the clock frequency is increased only when the register value is reached twice in succession as in the third embodiment, it is possible to prevent the clock frequency from being repeatedly increased and decreased.

  Furthermore, in the present embodiment, the clock frequency is decreased only when it becomes less than the register value twice in succession as in the fourth embodiment, so that it is possible to prevent the clock frequency from being repeatedly increased and decreased. .

  Further, in the present embodiment, by setting different values in the two registers as in the fifth embodiment, the reference value for increasing the clock frequency and the reference value for decreasing the clock frequency can be changed. It is possible to prevent repeated ascent and descent.

  In this embodiment, the case where there is one comparison circuit has been described as an example. However, by providing a plurality of comparison circuits and registers, the clock frequency can be switched to three or more stages instead of two stages.

  In the first to sixth embodiments, the case where the present invention is applied to a data processing device of a DVD playback drive has been described as an example. However, the present invention is not limited to each of the above embodiments, and the gist of the present invention is as follows. Various modifications can be made without departing from the scope of the invention.

  The present invention relates to a data processing apparatus, and can be applied to a processing apparatus capable of performing operation clock switching control, such as a DVD playback drive.

It is a block diagram which shows the structure of the data processor which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the clock control circuit of the data processor which concerns on Embodiment 1 of this invention. It is a timing chart for demonstrating the clock control circuit operation | movement of the data processor which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the data processor which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the clock control circuit of the data processor which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the clock control circuit of the data processor which concerns on Embodiment 3 of this invention. It is a block diagram which shows the structure of the clock control circuit of the data processor which concerns on Embodiment 4 of this invention. It is a block diagram which shows the structure of the clock control circuit of the data processor which concerns on Embodiment 5 of this invention. It is a block diagram which shows the structure of the clock control circuit of the data processor which concerns on Embodiment 6 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Demodulation circuit, 2 ... Error correction circuit, 3 ... Descramble circuit, 4 ... Memory control circuit, 5 ... Memory, 6 ... Clock oscillation circuit, 7, 40 ... Divider circuit, 8, 41, 84 ... Multiplexer, 9 , 42, 60, 70, 80, 90 ... clock control circuit, 21 ... duck counter, 22 ... clock counter, 23 ... inverting circuit, 24, 51, 85, 86 ... register, 25, 52 ... comparator, 26, 53 ... Delay circuit 61... D flip-flop 62. AND circuit 71. OR circuit 81. Rising detection circuit 82. Falling detection circuit 83.

Claims (6)

A data processing device for processing input data,
A counter for counting the number of pulses of the data transfer approval signal for a certain period generated in the data processing device;
A register for storing a reference value of the count value of the data transfer approval signal for the predetermined period;
A comparison circuit for comparing the count value of the counter with the value of the register;
When the output of the comparison circuit is input, the operation clock frequency in the data processing device is switched to the first operation clock frequency when the number of pulses of the data transfer approval signal in the certain period is equal to or greater than the reference value, and the constant A data processing apparatus comprising: a clock supply circuit for switching to a second operation clock frequency lower than the first operation clock frequency when the number of pulses of the data transfer approval signal in the period is less than the reference value. A data processing device for processing input data,
A counter for counting the number of pulses of the data transfer approval signal for a certain period generated in the data processing device;
A plurality of registers for storing different reference values of the count value of the data transfer approval signal for the predetermined period;
A plurality of comparison circuits for comparing values of the counter and the plurality of registers;
The outputs of the plurality of comparison circuits are input, and the operation clock frequency in the data processing device is related to the vertical relationship between the number of pulses of the data transfer approval signal in the predetermined period and the plurality of reference values stored in the plurality of registers. And a clock supply circuit for switching to a plurality of operating clock frequencies according to the data processing apparatus. The data processing device according to claim 1 or 2,
A D flip-flop for storing the output of the comparison circuit at regular intervals;
An AND circuit that performs a logical product of the value of the D flip-flop and the output of the comparison circuit;
The clock supply circuit receives the output of the AND circuit, and the operation clock frequency in the data processing device is generated a plurality of times when the number of pulses of the data transfer approval signal in the certain period exceeds the reference value. Switch to the first operation clock frequency, and switch to the second operation clock frequency lower than the first operation clock frequency when the number of pulses of the data transfer approval signal in the predetermined period is less than the reference value. A data processing apparatus. The data processing device according to claim 1 or 2,
A D flip-flop for storing the output of the comparison circuit at regular intervals;
An OR circuit that performs a logical sum of the value of the D flip-flop and the output of the comparison circuit;
The clock supply circuit receives the output of the OR circuit, the operation clock frequency in the data processing device, and the first operation when the number of pulses of the data transfer approval signal in the predetermined period is greater than or equal to the reference value. Switch to the clock frequency, and if the number of pulses of the data transfer approval signal for the certain period falls below the reference value a plurality of times, switch to the second operation clock frequency lower than the first operation clock frequency. A data processing apparatus. A data processing device for processing input data,
A counter for counting the number of pulses of the data transfer approval signal for a certain period generated in the data processing device;
A plurality of registers for storing different reference values of the count value of the data transfer approval signal for the predetermined period;
A multiplexer for switching the plurality of registers;
A comparison circuit for comparing the output value of the multiplexer and the value of the counter;
A rising edge detection circuit for detecting a rising edge of the output signal of the comparison circuit;
A falling detection circuit for detecting a falling edge of the output signal of the comparison circuit;
An RS flip-flop that performs setting and resetting by output signals from the rise detection circuit and the fall detection circuit, and performs switching control of the multiplexer;
The output of the comparison circuit to which the value of the register switched by the RS flip-flop is input is input, and the operation clock frequency in the data processing device is changed from the first operation clock frequency to the first operation clock frequency. The first reference value is used when switching to a lower second operation clock frequency, and the second reference value is used when switching from the second operation clock frequency to the first operation clock frequency. A data processing apparatus comprising a clock supply circuit for switching frequencies. A data processing device for processing input data,
A counter for counting the number of pulses of the data transfer approval signal for a certain period generated in the data processing device;
A plurality of registers for storing different reference values of the count value of the data transfer approval signal for the predetermined period;
A multiplexer for switching the plurality of registers;
A comparison circuit for comparing the output value of the multiplexer and the value of the counter;
A D flip-flop for storing the output of the comparison circuit at regular intervals;
An AND circuit that performs a logical product of the value of the D flip-flop and the output of the comparison circuit;
An OR circuit that performs a logical sum of the value of the D flip-flop and the output of the comparison circuit;
A rising edge detection circuit for detecting a rising edge of an output signal of the AND circuit;
A falling detection circuit for detecting a falling edge of the output signal of the OR circuit;
An RS flip-flop that performs setting and resetting by output signals from the rise detection circuit and the fall detection circuit, and performs switching control of the multiplexer;
When the output of the RS flip-flop is input and the operation clock frequency in the data processing device is switched from the first operation clock frequency to the second operation clock frequency lower than the first operation clock frequency, the first operation clock frequency When a reference value is used to switch from the second operation clock frequency to the first operation clock frequency, a second reference value is used, and the number of pulses of the data transfer approval signal in the predetermined period is the second value. When the occurrence of the reference value or more occurs multiple times, the frequency is switched to the first operation clock frequency, and the number of pulses of the data transfer approval signal during the certain period is less than the first reference value. And a clock supply circuit for switching to the second operating clock frequency.

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