JPH11296989A - Read-channel circuit and optical disk device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optimize error rate by making a punching phase of data into the best point. SOLUTION: When an error is caused in a first slice level by a HPF 20, a comparator 21, a DSV measuring circuit 23, a LPF 24, and a D/A converter circuit 25, a reproduction stream is outputted through a reproduction stream generating circuit 29 and a flip-flop F3 by controlling a second slice level by a phase error detecting circuit 26, a LPF 27, a D/A converter 28, and a comparator 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to, for example, DV
The present invention relates to a read channel circuit and an optical disk device used for a disk reproducing device for reproducing disks of two or more types of recording formats that are not simultaneously reproduced, such as a D / CD / CD-ROM compatible reproducing device.

[0002]

2. Description of the Related Art Conventionally, DVD / C has been used as an optical disk device.
2. Description of the Related Art There is a read channel circuit used in a disc reproducing apparatus such as a D / CD-ROM compatible reproducing apparatus, which reproduces disks of two or more recording formats which are not simultaneously reproduced.

FIG. 6 shows a configuration of a conventional read channel circuit. The RF signal read from the disk is input to a high-pass filter HPF. The output of the high-pass filter HPF is input to the positive input of the comparator CMP1. The negative input of the comparator CMP1 has D
The output signal of the / A conversion circuit is input. The output signal of the D / A conversion circuit indicates a slice level.

The comparator CMP1 outputs an H level signal when the positive input level is higher than the negative input level, and outputs an L level signal when the positive input level is lower than the negative input level. Therefore, the high-pass filter HP
When the level of the output signal of F is higher than the slice level, the output of the comparator CMP1 becomes H level,
When the level of the output signal of the PF is equal to or lower than the slice level, the output of the comparator CMP1 becomes L level.

[0005] The output signal of the comparator CMP1 is input to a phase comparator and a DSV measurement circuit. The DSV measurement circuit uses the DSV (Digital Sam Value) of the CMP1 output signal.
Digital sum value). Based on the measurement result of the DSV measurement circuit, the H level occurrence probability and the L level occurrence probability of the CMP1 output signal can be compared.

If the occurrence probability of the H level in the CMP1 output signal is higher than the occurrence probability of the L level, the measurement result of the DSV measurement circuit becomes a positive value. If the occurrence probability of the H level in the CMP1 output signal is lower than the occurrence probability of the L level, the measurement result of the DSV measurement circuit becomes a negative value. CMP
If the occurrence probability of the H level in one output signal is equal to the occurrence probability of the L level, the measurement result of the DSV measurement circuit is zero.

[0007] The output of the DSV measurement circuit is input to a low-pass filter LPF. The output value of the low-pass filter LPF is a value corresponding to the slice level. The output of the low-pass filter LPF is input to the D / A conversion circuit. D /
The A conversion circuit outputs a signal having a voltage corresponding to the input signal value. The voltage of the output signal of the D / A conversion circuit is at the slice level. When the occurrence probability of the H level of the CMP1 output signal is higher than the occurrence probability of the L level, the slice level is controlled to increase.

As the slice level increases, the probability of occurrence of the H level of the CMP1 output signal decreases. When the occurrence probability of the H level of the CMP1 output signal is lower than the occurrence probability of the L level, the slice level is controlled to decrease. When the slice level decreases, the occurrence probability of the H level of the CMP1 output signal increases. The slice level is controlled so that the H level occurrence probability and the L level occurrence probability of the CMP1 output signal are equal.

The phase comparator has two flip-flops (F
1 · F2), an EOR circuit, an ENR circuit, and an inverter circuit. The flip-flop F1 has a CMP
One output signal is input as a data signal, and the reproduction clock is input as a clock signal. In the flip-flop F2,
The output of the flip-flop F1 is input as a data signal, and the output of the inverter circuit is input as a clock signal. A reproduced clock is input to the inverter circuit.

An EOR circuit receives an RF signal and an output signal of a flip-flop F1. The EOR circuit outputs a phase error detection pulse with offset. The output signals of the flip-flops F1 and F2 are input to the ENR circuit. The ENR circuit outputs an offset removal pulse.

The switch SW1 is controlled by a phase error detection pulse with offset. SW1 is turned on while the offset phase error detection pulse is H. When SW1 is on, a positive current is input to the loop filter via the resistor R1. The switch SW2 is controlled by the offset removal pulse. SW2 is turned on while the offset removal pulse is L. When SW2 is on, a negative current is input to the loop filter via the resistor R1.

The loop filter includes an operational amplifier, a capacitor, and a resistor. The potential at point A is VA, the point B
At the point C, VA−VC = VC−
A voltage Vc that becomes VB is input. The loop filter controls the potential VD at the point D so that VD = VC. In the VCO in this example, the frequency of the output signal is inversely proportional to the input control voltage. Therefore, if the output voltage of the loop filter increases, the frequency of the output signal of the VCO decreases, and if the output voltage of the loop filter decreases, the frequency of the output signal of the VCO increases. The frequency of the reproduction clock is controlled so that the phase error between the output signal of the comparator CMP1 and the reproduction clock becomes zero.

FIG. 7 shows how the phase error detection pulse with offset and the offset removal pulse are generated and the waveform of the current flowing through the addition resistor. 7A shows a CMP1 output signal, FIG. 7B shows a reproduced clock, FIG. 7C shows an output signal of the flip-flop F1, and FIG. 7D shows an output signal of the flip-flop F2. 7 (e) shows a phase error detection pulse with offset, FIG. 7 (f) shows an offset removal pulse, and FIG. 7 (g) shows a waveform of a current flowing through the resistor R1 when SW1 is turned on. And (h) of FIG.
2 shows a waveform of a current flowing through the resistor R1 when 2 is on.

At time (1) in FIG. 7, the phase of the phase error detection pulse with offset and the pulse width ratio of the output signal of the ENR circuit are equal to each other when the phase of the CMP1 output signal and the phase of the reproduced clock are synchronized. If VA-Vc = VC-VB, the area of the hatched portion in FIG. 7 (g) is equal to the area of the hatched portion in FIG. 7 (h), and the loop filter is formed by the phase error detection pulse with offset and the offset removal pulse. Are equal in absolute value. Since the polarities of the two charges are opposite, the output voltage of the loop filter does not change, and the frequency of the reproduced clock does not change. Therefore, the CMP1 output signal and the reproduction clock maintain a state in which the phases are synchronized.

At time (2) in FIG. 7, the phase of the CMP1 output signal is advanced with respect to the reproduction clock. The pulse width of the phase error detection pulse with offset is the time point (1)
Is increased by an amount corresponding to the phase error. As a result, the output voltage of the loop filter decreases, and the oscillation frequency of the VCO increases. When the oscillation frequency of the VCO rises, CMP
The phase error between one output signal and the recovered clock is reduced.

At time (3) in FIG. 7, the output signal of CMP1 has a phase lag with respect to the recovered clock. The pulse width of the phase error detection pulse with offset is the time point (1)
Is reduced by the phase error. As a result, the output voltage of the loop filter increases, and the oscillation frequency of the VCO decreases. When the oscillation frequency of the VCO decreases, CMP
The phase error between one output signal and the recovered clock is reduced. As described above, the phase error between the output signal of the CMP1 and the reproduced clock is removed by changing the pulse width of the phase error detection pulse with offset.

FIG. 8 shows a data structure and a data signal envelope at a data area switching point of the DVD-RAM. FIG. 8A shows a data configuration when the DVD-RAM disk is viewed from the direction perpendicular to the data recording surface. A hatched portion in FIG. 8A indicates a locus of movement of the pickup during data reproduction.

FIG. 8B shows the envelope of the RF signal, and FIG. 8C shows the envelope of the output signal of the HPF that receives the RF signal. The broken line portion in FIG.
This shows an ideal slice level when binarizing a data signal.

As shown in FIG. 8A, a DVD-RAM
Disk has 1 / the center line of the data track.
The ID data is recorded in a state shifted by two widths. When this portion is reproduced, the envelope of the RF signal greatly fluctuates at the data area switching points (time points (1), (2), and (3)) as shown in FIG. RF
Since the signal envelope fluctuates greatly, the envelope of the output signal of the HPF also fluctuates greatly at the data area switching point. If the slice level cannot follow this variation, the data signal is set to 2 at the ideal slice level.
Cannot be priced.

As in the above example, there are cases where the data signal cannot be binarized at an ideal slice level in reproduction of an optical disk or the like. In such a case, in the conventional circuit, there is a problem that the phase synchronization control between the data signal and the reproduction clock cannot be performed correctly, and the data error increases.

FIG. 9 shows the phase error detection pulse with offset and the offset removal pulse when the data signal cannot be binarized at an ideal slice level in the circuit of FIG.

9A shows an RF signal and a slice level, FIG. 9B shows an RF signal binarized by a slice level A, and FIG. 9F shows a binarized RF signal by a slice level B. 9 (c) and 9 (g) show the recovered clock, FIGS. 9 (d) and 9 (h) show the phase error detection pulse with offset, and FIGS. 9 (e) and 9 (i) show the recovered RF signal. 3 shows an offset removal pulse.

In FIG. 9A, the slice level A
Is an ideal slice level when binarizing the RF signal, and the slice level B is a non-ideal slice level. When the RF signal is binarized at the slice level A, 2
The phase of the digitized RF signal is synchronized with the reproduction clock. When the RF signal is binarized at the slice level B, the binarized RF signal has a rising phase delayed with respect to the reproduced clock and a falling phase advanced with respect to the reproduced clock. Since the polarity of the phase error is inverted at the rise and fall of the RF signal, the phase error is stabilized at a point where the two phase error amounts are balanced as shown in FIG. In this state, RF
There is a phase error between the RF signal and the recovered clock at both the rise and fall of the signal. If there is a phase error, the punchout phase of the data is not the best point,
If the F signal contains jitter, errors due to jitter increase.

In the prior art, there is a method of comparing the phase of only one edge of the RF signal with the phase of the reproduction clock. When comparing phases at one edge, the phase error signals do not cancel each other.

FIG. 10 shows a configuration of a binarizing circuit and a clock generating circuit for comparing only the rising edge of the RF signal with the phase of the reproduced clock. Compared with FIG. 6, the configuration of the phase comparator is different.
The R circuit is an OR circuit. As a result, the phase error detection pulse with offset and the offset removal pulse are output only at the rise of the RF signal. Even in the method of comparing the phase of the recovered clock with only one edge of the RF signal, if the slice level is not an ideal value, there is a problem that data errors increase.

FIG. 11 shows the state of the RF signal and the reproduced clock when the data signal is binarized at a non-ideal slice level in the circuit of FIG. (A) of FIG.
11B shows an RF signal and a slice level, FIG. 11B shows a signal obtained by binarizing the RF signal using the slice level A, and FIG.
(C) and (e) of FIG. 11 show the reproduced clock of the quantified signal.

In FIG. 11A, the slice level A is an ideal slice level when the RF signal is binarized, and the slice level B is a non-ideal slice level. When the binarization at the slice level A is performed so that the phase error between the rising edge of the binarized RF signal and the reproduced clock becomes zero, the phase error between the reproduced clock and the falling edge of the RF signal can be reduced. Becomes zero. When binarization is performed at the slice level B, there is a phase error with the reproduction clock on the falling side of the RF signal. If there is a phase error, the punchout phase of the data is not the best point,
If the RF signal contains jitter, errors due to jitter increase.

[0028]

As described above, if there is a phase error, the phase in which data is not punched out is not the best point, so that the error due to jitter increases when the RF signal contains jitter. was there. Therefore,
SUMMARY OF THE INVENTION It is an object of the present invention to provide a read channel circuit and an optical disk device that have the best error rate with the data punching phase being the best point.

[0029]

According to a read channel circuit of the present invention, a read channel circuit binarizes a received channel stream and generates a reception clock synchronized with the channel stream. First binarizing means for binarizing at a level, second binarizing means for binarizing the channel stream at a second slice level, and binarizing at the first binarizing means First generating means for generating a reception clock signal phase-synchronized with the binarized signal, and a binarized signal binarized by the second binarizing means and generated by the first generating means. So that the phase difference between the received clock signal and the received clock signal generated by the first binarizing unit is equal to the phase difference between the binarized signal binarized by the first binarizing unit and the received clock signal generated by the first generating unit. The second And changing means for changing the rice level, the binary signal from the first binarizing means and said second
And a second generation unit that generates a reproduction channel stream signal by combining the binarized signal from the binarization unit.

A read channel circuit according to the present invention binarizes a received channel stream and generates a receive clock synchronized with the channel stream. The read channel circuit binarizes the channel stream at a first slice level. A first binarizing means, and a second binarizing means for binarizing the channel stream at a second slice level
A first generating means for generating a reception clock signal phase-synchronized with the binary signal binarized by the first binarizing means; and a second binarizing means. The phase difference between the binarized signal binarized in the step (c) and the reception clock signal generated by the first generation unit is the same as that of the binarized signal binarized by the first binarization unit. Changing means for changing the second slice level so as to be opposite to a phase difference of the received clock signal generated by the first generating means; and a binarized signal from the first binarizing means; And a second generation unit for generating a reproduction channel stream signal by combining the binarized signal from the binary binarization unit.

A read channel circuit according to the present invention is a read channel circuit for binarizing a reception channel stream whose digital sum value is controlled and generating a reception clock synchronized with the channel stream. First binarizing means for binarizing at the slice level of
A second binarizing means for binarizing at the slice level, and an edge of the first polarity of the binarized signal binarized by the first binarizing means as a phase reference. A first generating means for generating a reception clock signal phase-synchronized so that the phase difference becomes zero, and a DSV of the binarized signal binarized by the first binarizing means being zero. Changing means for changing the first slice level, an edge of a second polarity of the binarized signal binarized by the second binarizing means, and reception generated by the first generating means. Detecting means for detecting a correction level at which the phase difference between the clock signal and the phase reference point becomes zero; and adding the first slice level changed by the changing means and the correction level detected by the detecting means. The adding means for setting the second slice level and the first binarizing means A second generation of a reproduction channel stream signal in which the time point at which the first polarity edge of the binarized binary signal is generated and the time point at which the second polarity edge of the second binary signal is generated are signal polarity inversion times. And generating means.

A read channel circuit according to the present invention is a read channel circuit for binarizing a reception channel stream whose digital sum value is controlled and generating a reception clock synchronized with the channel stream. First binarizing means for binarizing at the slice level of
A second binarizing means for binarizing at the slice level, and an edge of the first polarity of the binarized signal binarized by the first binarizing means as a phase reference. A first generating means for generating a reception clock signal phase-synchronized so that the phase difference becomes zero, and a DSV of the binarized signal binarized by the first binarizing means being zero. First changing means for changing the first slice level to the second slice level;
The edge of the second polarity of the binarized signal binarized by the binarizing means and the edge of the second polarity of the binarized signal binarized by the first binarizing means. Changing the second slice level so that the phase difference between the received clock signal generated by the first generation means and the phase reference point becomes zero.
Changing means, and the binarized binary data by the first binarizing means.
A reproduction channel stream signal having a point of occurrence of a first polarity edge of the binarized signal and a point of occurrence of a second polarity edge of the binarized signal binarized by the second binarization means at the time of signal polarity inversion. And a second generating means for generating.

A read channel circuit according to the present invention is a read channel circuit for binarizing a reception channel stream whose digital sum value is controlled and generating a reception clock synchronized with the channel stream, wherein the channel stream is first First binarizing means for binarizing at the slice level of
A second binarizing means for binarizing at the slice level, and an edge of the first polarity of the binarized signal binarized by the first binarizing means as a phase reference. A first generating means for generating a reception clock signal phase-synchronized so that the phase difference becomes zero, and a DSV of the binarized signal binarized by the first binarizing means being zero. Changing means for changing the first slice level, an edge of a second polarity of the binarized signal binarized by the second binarizing means, and a binary signal by the first binarizing means. Of the binarized binary signal
Detecting means for detecting a correction level at which a phase difference between the phase reference point of the received clock signal generated by the first generating means and closest to the edge of the polarity becomes zero; and the first level changed by the changing means. Adding means for adding a slice level and a correction level detected by the detection means to obtain the second slice level; and a first binarization signal binarized by the first binarization means. Polarity edge occurrence point and the second 2
And a second generation unit for generating a reproduction channel stream signal whose signal polarity is inverted when the edge of the second polarity of the binarized signal binarized by the binarization unit is generated.

An optical disk apparatus according to the present invention includes a reading means for irradiating an optical disk with light to read a signal, and a first binary for binarizing a signal read by the reading means with a first threshold value.
A binarizing unit, a second binarizing unit that binarizes the signal read by the reading unit with a second threshold value, and a binarized signal binarized by the first binarizing unit. First generating means for generating a phase-synchronized reception clock signal; and a binary clock signal binarized by the second binarization means and a reception clock signal generated by the first generation means. The phase difference is the first
Changing means for changing the second threshold value so as to be opposite to a phase difference between the binary signal binarized by the binarizing means and the reception clock signal generated by the first generating means; It comprises a second generating means for generating a reproduction signal by synthesizing the binary signal from the first binarizing means and the binary signal from the second binarizing means.

An optical disk apparatus according to the present invention comprises: a reading means for irradiating an optical disk with light to read a signal; and a first binary signal for binarizing a signal read by the reading means with a first threshold value.
A binarizing unit, a second binarizing unit for binarizing the signal read by the reading unit with a second threshold value, and a binarizing signal binarized by the first binarizing unit. A first generation unit that generates a reception clock signal that is phase-locked so that a phase difference from the phase reference becomes zero with an edge having a first polarity as a phase reference, Changing means for changing the first threshold value according to the value of the binarized signal;
A second binarized signal binarized by the second binarizing means;
Detecting means for detecting a correction value at which the phase difference between the edge of the polarity and the phase reference point of the received clock signal generated by the first generating means becomes zero; and a first threshold value changed by the changing means; Adding means for adding the correction value detected by the detecting means to the second threshold value, and generating an edge of the first polarity of the binary signal binarized by the first binarizing means And a second generating means for generating a reproduction signal having a time point and a time point at which the edge of the second polarity of the second binarized signal occurs when the signal polarity is inverted.

[0036]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an overall configuration of an optical disk reproducing system to which the present invention is applied.

The signal read from the disk 1 by the optical pickup 3 is current-voltage converted by an IV conversion amplifier 4 and output to an RF amplifier 5 and a servo error amplifier 6. CD / DVD from system controller 107
Optimal gains are set by the selection signals.

The RF amplifier 5 performs the optimum automatic gain control (AGC) and waveform equalization for the CD / DVD on the RF signal converted by the IV conversion amplifier 4 to obtain a DV signal.
DVD level slice / PLL circuit 8 for D-RF signal
And outputs the CD-RF signal to the CD level slice / PLL circuit 9. The CD / DVD selection signal is supplied from the system controller 107.

The servo error amplifier 6 is an IV conversion amplifier 4
Then, a focus error signal and a tracking error signal optimum for each of CD / DVD are generated from the signal obtained by the voltage conversion, and output to the focus / tracking control circuit 10. The CD / DVD selection signal is sent to the system controller 1
07.

The focus / tracking control circuit 10 performs optimal phase compensation, balance, gain adjustment, etc. for each CD / DVD for stabilizing the servo loop, and sends a tracking control signal and a focus control signal to the focus driver 11a and the tracking driver 11b. Outputs a tracking error signal and outputs a motor control circuit 1
Output to 3. The CD / DVD selection signal is supplied from the system controller 107.

Focus and tracking driver 11
Reference numerals a and 11b control the optical pickup 3 by outputting the amplified control signal to a focus and tracking actuator in the optical pickup main body.

The feed motor control circuit 13 generates a feed motor control signal for moving the pickup body based on a tracking error signal input from the focus / tracking control circuit 10 and a search command from the system controller 107, and outputs the signal to the feed motor driver 13. I do.

The feed motor driver 13 outputs the amplified control signal to the pickup feed motor 15 to control the movement of the pickup body. DVD level slice / PLL
The circuit 8 obtains an 8-16 signal obtained by binarizing the RF signal whose waveform has been equalized by the RF amplifier circuit 5. At the same time,
PLL synchronized with 8-16 signal to read 6 signals
Generate a clock. The binarized 8-16 signal (data signal) and the PLL clock are output to the DVD signal processing circuit 116. The present invention is incorporated in a DVD level slice / PLL circuit 8 and output from an RF amplifier circuit 5.
The present invention relates to a read channel circuit for binarizing an F signal.

The CD level slice / PLL circuit 9 is RF
The RF signal whose waveform has been equalized by the amplifier circuit 5 is binarized to obtain an EFM signal. At the same time, a PLL clock synchronized with the EFM signal is generated to read the EFM signal.
The binarized EFM signal and the PLL clock are output to the CD signal processing circuit 117.

The DVD signal processing circuit 116 detects a DVD synchronization signal from the 8-16 signal using the PLL clock, and performs data separation and 8-16 demodulation. The speed and phase error of the disk motor 2 are detected from the detected DVD synchronization signal, and a disk motor control signal is generated and output to the disk motor driver 12. The demodulated data is supplied to the DVD correction circuit 11
8 and the buffer memory controller 119 together with the DVD synchronization signal.

The DVD correction circuit 118 performs syndrome calculation according to the DVD format sequentially from the input data, and performs the DVD / CD / CD-ROM dual-purpose correction memory 12.
In 6, the calculation result of each line of PI and PO is written. Correction 1
After the syndrome calculation results for 16 blocks are stored in the correction memory 126, the calculation results are read out from the correction memory 126 in synchronization with the start timing of the next one correction block, and correction processing according to the DVD format is performed. The corrected data is written to the buffer memory 124 via the buffer memory controller 119.

The CD signal processing circuit 117 detects a CD synchronizing signal from the EFM signal using the PLL clock, and performs data separation and EFM demodulation. The subcode data and main data are separated from the demodulated data, and the subcode Q data is extracted from the subcode data and output to the system controller 107. The speed and phase error of the disk motor 2 are detected from the detected CD synchronization signal, and a disk motor control signal is generated and output to the disk motor driver 12. The main data is output to the CD correction circuit 121 together with the CD synchronization signal. The subcode data and the CD error flag are output to the CD-ROM signal processing circuit 122.

The CD correction circuit 121 converts the main data into a DV signal.
After writing in the D / CD / CD-ROM combined correction memory 126, a correction process according to the CD format is performed, and after the correction is completed, all the main data is read from the correction memory 126 and output to the CD-ROM signal processing circuit 122.

The disk motor driver 12 amplifies the control signal of the disk motor 2 and outputs an actual drive signal to the disk motor 2 to control the rotation speed of the disk 1. CD
-If the main data input from the CD correction circuit 121 is CD-ROM data, the ROM signal processing circuit 122
It detects a D-ROM synchronization signal, descrambles CD-ROM data, stores header data, and performs EDC calculation. CD-ROM data is stored in a CD-ROM correction circuit 12
7 and output to the buffer memory controller 119. The subcode data and the CD error flag are output to the buffer memory controller 119. The CD-ROM synchronization signal is output to the buffer memory controller 119, the CD-ROM correction circuit 127, and the system controller 107.
The EDC result and header data are stored in the system controller 10
7 is output. In the case of CD-DA data, CD-DA data, subcode data, and a CD error flag are output to the buffer memory controller 119. The sub-code synchronization signal is output to the buffer memory controller 119 and the system controller 107.

The CD-ROM correction circuit 127 sequentially calculates syndromes in accordance with the CD-ROM format from input data, and writes the calculation results of the P and Q lines into the DVD / CD / CD-ROM correction memory 126. . Correction of syndrome calculation result for one sector Memory 1
After the data is stored in the memory 26, the calculation result is read from the correction memory 126 in accordance with the next sector start timing, and a correction process according to the CD-ROM format is performed. The corrected data is written to the buffer memory 124 via the buffer memory controller 119.

The buffer memory controller 119 has a CD
A write control of data input from the ROM signal processing circuit 122 and the DVD signal processing circuit 116 to the buffer memory, a data write / read control generated when the system controller 107 accesses the buffer memory 124, and an interface circuit 250 Control of writing / reading data to / from the buffer memory 124 which occurs when data communication is performed with an external device (host computer) in accordance with the instruction of 107, DVD
/ CD-ROM control for reading / writing data to / from the buffer memory 124 generated in the correction control, and the buffer memory 1
The CD-DA data stored in the D / A converter 24 is read and output to the DA converter 230.

The DA conversion circuit 230 converts the digital signal input from the buffer memory controller 119 into an analog signal and outputs it as an audio signal through a low-pass filter.

The interface control circuit 250 controls the entire interface such as interface control for communicating with the host computer and data transfer control. The data read from the buffer memory 124 through the buffer memory controller 119 is transferred to an external device (host computer), and the data transferred from the external device is output to the buffer memory controller 119 in accordance with an instruction from the system controller 107.

The system controller 107 issues commands necessary for ON / OFF, start / end, switching, etc. of operations in each circuit such as search control, correction control, interface control, etc., and performs status reading analysis / judgment.
The operation of the entire D / DVD-ROM system is controlled.

FIG. 2 shows the configuration of the first embodiment according to the read channel circuit of the present invention. First, the RF signal is input to a high-pass filter (HPF) 20 including a resistor R3 and a capacitor C3. The output of the HPF 20 is input to the positive input of the comparator 21. The output signal of the D / A conversion circuit 25 is input to the negative input of the comparator 21. The output signal of the D / A conversion circuit 25 is the first
Indicates the slice level.

The comparator 21 outputs an H level signal when the positive input level is higher than the negative input level, and outputs an L level signal when the positive input level is lower than the negative input level. Therefore, when the level of the output signal of the HPF 20 is higher than the first slice level, the output of the comparator 21 becomes H level, and when the level of the output signal of the HPF 20 is lower than the first slice level, the output of the comparator 21 becomes L level. Becomes

The output signal of the comparator 21 is a signal obtained by binarizing the RF signal at the first slice level. DS
The V measurement circuit 23 calculates the D of the output signal from the comparator 21.
Measure SV (Digital Sam Value). From the DSV measurement result, the H level occurrence probability and the L level occurrence probability of the output signal of the comparator 21 can be compared.

If the H level occurrence probability in the output signal of the comparator 21 is higher than the L level occurrence probability, DSV
The measurement result is a positive value. If the H level occurrence probability in the output signal of the comparator 21 is lower than the L level occurrence probability, the DSV measurement result becomes a negative value. Comparator 2
If the H level occurrence probability in the output signal of 1 is equal to the L level occurrence probability, the DSV measurement result is zero.

The output of the DSV measurement circuit 23 is input to a low-pass filter (LPF) 24. The output value of the LPF 24 is a value corresponding to the first slice level. LPF
The output of 24 is input to the D / A conversion circuit 25. D / A
Conversion circuit 25 outputs a signal having a voltage corresponding to the input signal value. The output signal voltage of the D / A conversion circuit 25 is the first
At the slice level.

When the H level occurrence probability of the output signal of the comparator 21 is higher than the L level occurrence probability, the first slice level is controlled to increase. When the first slice level rises, the output signal H of the comparator 21 becomes high.
The level occurrence probability decreases. When the H level occurrence probability of the output signal of the comparator 21 is lower than the L level occurrence probability,
The first slice level is controlled to decrease. When the first slice level decreases, the H level occurrence probability of the output signal of the comparator 21 increases. As described above, the first slice level is H level of the output signal of the comparator 21.
Control is performed so that the level occurrence probability and the L level occurrence probability become equal.

The phase comparator 30 compares the rising of the output signal of the comparator 21 with the phase of the reproduced clock.
The phase comparator 30 includes two flip-flops F1, F0
2, AND circuit 31, OR circuit 32, and inverter circuit 3
3 is comprised.

The output signal of the comparator 21 is input to the data input side of the flip-flop F1, and the reproduced clock is input to the clock input side. The output of the flip-flop F1 is input to the data input side of the flip-flop F2, and the output of the inverter circuit 33 is input to the clock input side.

A reproduction clock is input to the inverter circuit 33. The RF signal and the output signal of the flip-flop F1 are input to the AND circuit 31. The AND circuit 31 outputs a phase error detection pulse with offset. The output signals of the flip-flops F1 and F2 are input to the OR circuit 32. The OR circuit 32 outputs an offset removal pulse. The switch SW1 is controlled by a phase error detection pulse with offset. The switch SW1 is turned on while the phase error detection pulse with offset is H. When the switch SW1 is on, a positive current is input to the loop filter 34 via the resistor R1.
The switch SW2 is controlled by the offset removal pulse. While the offset removal pulse is L, the switch SW2
Turns on. When the switch SW2 is on, a negative current is input to the loop filter 34 via the resistor Rl.

The loop filter 34 comprises an operational amplifier 35, a capacitor C2 and a resistor R2. Assuming that the potential of the point A is VA and the potential of the point B is VB,
A voltage VC that satisfies A-VC = VC-VB is input. The loop filter 34 controls the potential VD at the point D so that VD = VC. In the VCO 36 in this example, the frequency of the output signal is inversely proportional to the input control voltage. Therefore,
If the output voltage of the loop filter 34 rises, the VCO 36
The frequency of the output signal of the VCO 36 increases when the output voltage of the loop filter 34 decreases. The frequency of the reproduced clock is controlled so that the phase difference between the rising edge of the output signal of the comparator 21 and the reproduced clock becomes zero. The positive input of the comparator 22 is H
The output of the PF 20 is input.

The output signal of the D / A conversion circuit 28 is input to the negative input of the comparator 22. D / A conversion circuit 28
Indicates the second slice level. The comparator 22 outputs an H-level signal when the positive input level is higher than the negative input level, and outputs an L-level signal when the positive input level is lower than the negative input level. Therefore, when the level of the output signal of the HPF 20 is higher than the second slice level, the output of the comparator 22 becomes H level, and when the level of the output signal of the HPF 20 is lower than the second slice level, the output of the comparator 22 becomes L level.
Level. The output signal of the comparator 22 is a signal obtained by binarizing the RF signal with the second slice level.

The output signal of the comparator 21, the output signal of the comparator 22, and the reproduction clock are input to the phase error detection circuit 26. The phase error detection circuit 26 compares the fall of the output signal of the comparator 22 with the phase of the phase reference point. The phase reference point is the falling edge of the reproduced clock in the identification window including the falling edge of the output signal of the comparator 21 when the interval between the rising edges of the reproduced clock is used as the identification window.

The phase error detection circuit 26 includes a comparator 2
The phase reference point is detected using the output signal of No. 1 and the reproduced clock, and the falling edge of the output signal of the comparator 22, the phase error amount and the polarity of the phase reference point are detected. At the fall of the RF signal, if the phase of the output signal of the comparator 22 is ahead of the phase reference point, the phase difference can be removed by lowering the second slice level. Conversely, when the output signal of the comparator 22 is behind the phase reference point, the phase difference can be removed by increasing the second slice level.

The phase error detection circuit 26 includes a comparator 2
2 outputs a negative value when the output signal is ahead of the phase reference point, and outputs a positive value when the output signal is late. The output of the phase error detection circuit 26 is input to the LPF 27. The output of the LPF 27 is input to the D / A conversion circuit 28. The D / A conversion circuit 28 outputs a signal having a voltage corresponding to the input signal value. The voltage of the output signal of the D / A conversion circuit 28 is at the second slice level. The second slice level is an RF signal binarized by the second slice level.
Control is performed so that the falling of the signal and the phase of the reproduction clock are synchronized.

The output signals of the comparators 21 and 22 are input to the reproduction stream generation circuit 29. The reproduction stream generation circuit 29 includes the comparator 21
Are combined with the falling side of the output signal of the comparator 22. The output signal of the reproduction stream generation circuit 29 rises at the same time as the rise of the output signal of the comparator 21, and falls at the same time as the fall of the output signal of the comparator 22.

The output of the reproduction stream generation circuit 29 is input to the data input side of the flip-flop F3, and the output of the reproduction clock is input to the clock input side.
3 outputs a playback stream.

FIG. 3 shows a second slice level control method. FIG. 3A shows an RF signal and a first slice level and a second slice level (AB).
C) is shown. The second slice level B indicates an optimum value of the second slice level, and the second slice level A · C
Indicates a state where there is an error with respect to the optimum value. FIG. 3B shows the RF binarized by the first slice level.
3 (c) shows the reproduction clock, and FIG. 3 (d)
3E shows the RF signal binarized by the second slice level A, FIG. 3E shows the output of the phase error detection circuit 26 corresponding to FIG. 3D, and FIG. 3F shows the second slice level. 3 (g) of FIG. 3 shows the output of the phase error detection circuit 26 corresponding to FIG. 3 (f), and FIG. 3 (h) shows the second slice level A. 2 shows an RF signal binarized by. FIG. 3 (i) shows the output of the reproduction stream generation circuit 29.

In FIG. 3A, it is assumed that the first slice level has an error with respect to the ideal slice level. The reproduction clock is controlled such that the phase error between the rising edge of the RF signal binarized at the first slice level and the falling edge of the reproduction clock becomes zero. Therefore, the signals of FIG. 3B and FIG. 3C are synchronized in phase at the rise of the RF signal at the time (4), but are synchronized at the fall of the RF signal at the time (5). Has a phase error.

When the interval between the rising edges of the reproduced clock is used as the identification window, the phase reference point of the second slice level is located within the identification window including the falling edge of the RF signal binarized by the first slice level. This is the falling edge of the reproduction clock. The second slice level is
Control is performed so that the phase difference between the falling edge of the RF signal binarized at the second slice level and the phase reference point becomes zero. In FIG. 3, the falling edge of the RF signal shown in FIG. 3B binarized at the first slice level falls within the identification window B. Therefore, the phase reference point of the second slice level is the time point (7).

When the second slice level is higher than the expected value at the fall of the RF signal, the RF signal binarized at the second slice level has a phase advanced from the phase reference point. If the second slice level is smaller than expected,
The RF signal binarized at the second slice level has a phase delayed from the phase reference point. Therefore, if the result of comparing the phase of the RF signal binarized at the second slice level with the phase of the phase reference point is “advanced”, the phase error can be removed by lowering the slice level. If the result of comparing the phase of the RF signal binarized at the second slice level with the phase reference point is "lag", the phase error can be removed by increasing the slice level.

In FIG. 3A, when the second slice level is the state of A, the second slice level is 2
The phase error amount between the digitized RF signal and the phase reference point shown in FIG. 3D is a difference value between the time points (6) and (7).
Since the phase of the signal shown in FIG. 3D is advanced from the phase reference point, it is necessary to lower the slice level. Therefore, the phase comparator 30 shown in FIG. 2 measures the pulse width as shown in FIG. 3E and outputs the measurement result as a negative value. As a result, the second slice level is reduced and the phase error is removed.

When the second slice level is in the state C, the phase error amount between the RF signal binarized at the second slice level and the phase reference point shown in FIG. ) And (8). Since the phase of the signal shown in FIG. 3 (f) is behind the phase reference point, it is necessary to increase the slice level. Therefore, the phase comparator 30
Measures the pulse width shown in (g) of FIG. 3 and outputs the measurement result as a positive value. As a result, the second slice level is increased and the phase error is removed. By the above control, the second slice level becomes the state of B, and the phase error between the falling edge of the RF signal binarized at the second slice level and the phase reference point shown in FIG. become.

FIG. 4 shows how a reproduced stream is generated. FIG. 4A shows an RF signal and an ideal slice level, a first slice level, and a second slice level. FIG. 4B shows an ideal slice level of 2
FIG. 4C shows a reproduced clock whose phase is synchronized with the rising edge of FIG. 4B, and FIG. 4D shows a binary signal at the first slice level. FIG. 4E shows a reproduced clock whose phase synchronization is controlled with respect to the rising edge of FIG.
(F) shows the RF signal binarized at the second slice level, (g) of FIG. 4 shows the rising edge detection signal of (d) of FIG. 4, and (h) of FIG. FIG. 4 (i) shows the output signal of the reproduction stream generation circuit 29, and FIG. 4 (j) shows the reproduction stream.

In FIG. 4A, the first slice level is a state where there is an error with respect to the ideal slice level, and the second slice level is a value for correcting the error of the first slice level. And Since the reproduced clock shown in FIG. 4C is binarized at the ideal slice level in FIG. 4B, even if the phase synchronization control is performed only at the rising edge of FIG. 4B, the phase is synchronized at both the rising and falling edges.

The reproduced clock shown in (e) of FIG.
(C), and the phase is synchronized only at the rising edge of (d) in FIG. In FIG. 4F, since the phase error between the falling edge of FIG. 4F and the reproduced clock shown in FIG. 4E is controlled to be zero, at time point (6) The phase is synchronized with the reproduction clock shown in FIG. 4G is a rising edge detection signal of FIG. 4D, and the rising edge of FIG. 4G and the rising edge of FIG. 4D are in phase. FIG. 4H shows the falling edge detection signal of FIG. 4F, and the rising edge of FIG. 4H and the falling edge of FIG. 4F are in phase.

4 (i) is generated by the reproduction stream generation circuit 29 using FIG. 4 (g) as a set signal and FIG. 4 (h) as a reset signal. The rising edge in (i) of FIG. 4 is synchronized in phase with the rising edge of the signal shown in (d) of FIG. 4 binarized at the first slice level, and the falling edge of (i) in FIG. The phase of the edge is synchronized with the falling edge of the signal of FIG. 4F binarized at the second slice level. (I) of FIG.
At both the rise and the fall, the phase is synchronized with the reproduced clock shown in FIG. FIG.
(J) is an output of the flip-flop F3 in which (i) of FIG. 4 is a data signal input and (e) of FIG. 4 is a clock signal input.

FIG. 4 binarized at an ideal slice level
The width of the H level section of the RF signal shown in (b) is the difference between the time (2) and the time (5), and corresponds to three periods of the reproduced clock shown in (c) of FIG. The width of the L level section in FIG. 4B is the difference between the time point (5) and the time point (8),
Are three periods of the reproduction clock shown in FIG. On the other hand, the output signal H of the reproduction stream generation circuit 29 shown in FIG.
Both the width of the level section and the width of the L level section are three cycles of the reproduction clock shown in FIG.

Since the frequencies of FIG. 4C and FIG. 4E are equal, the distance between edges of FIG. 4B and the frequency of FIG.
Are equal. 4B and FIG. 4I.
Are equal to each other, the output signal of the reproduction stream generation circuit 29 is a signal equivalent to an RF signal binarized at an ideal slice level.

When the first slice level deviates greatly from the ideal slice level, the position of the identification window including the falling edge in FIG. 4D is not the optimum position, and the reproduced stream can be obtained correctly. Absent. Therefore,
When the falling edge of the RF signal binarized at the first slice level is included in the optimum identification window, the reproduction stream generation circuit 29 is equivalent to the RF signal binarized at the ideal slice level. Output the playback stream.

As described above, according to the first embodiment, even if the first slice level has an error with respect to the ideal slice level, the second slice level can be controlled by controlling the second slice level. A signal equivalent to an RF signal binarized at a typical slice level can be generated. Since the output signal of the reproduction stream generation circuit 29 shown in FIG. 4 (i) has both the rising edge and the falling edge in phase with the reproduction clock shown in FIG. 4 (e),
The phase at which data is eliminated is the best point, and the error rate of the reproduced stream signal is the best.

Next, a second embodiment of the present invention will be described. FIG. 5 shows the configuration of a second embodiment according to the read channel circuit of the present invention. The same parts as in the first embodiment are denoted by the same reference numerals, and the description is omitted.

A value obtained by adding the output of the LPF 24 and the output of the LPF 27 by the adder 40 is input to the D / A conversion circuit 28. The D / A conversion circuit 28 outputs a signal having a voltage corresponding to the input signal value. The voltage of the output signal of the D / A conversion circuit 28 is at the second slice level. The second slice level is controlled so that the falling edge of the RF signal binarized at the second slice level and the phase of the reproduction clock are synchronized.

The output signals of the comparators 21 and 22 are input to the reproduction stream generation circuit 29. The reproduction stream generation circuit 29 includes the comparator 21
Are combined with the falling side of the output signal of the comparator 22. The output signal of the reproduction stream generation circuit 29 rises at the same time as the rise of the output signal of the comparator 21, and falls at the same time as the fall of the output signal of the comparator 22. The output of the reproduction stream generation circuit 29 is input to the data input side of the flip-flop F3, the output of the reproduction clock is input to the clock input side, and the flip-flop F3 outputs the reproduction stream. In this example, the second slice level is determined by adding the output value of the LPF 27 by the adder 40 using the first slice level as a reference value.

For example, in the reproduction of the optical disk 1, the envelope of the reproduced signal fluctuates due to the runout of the disk. The first slice level is RF based on DSV control.
It is controlled to follow the fluctuation of the signal envelope.
Therefore, the variable range of the first slice level needs to be widened. The second slice level is located substantially symmetrically with the first slice level about the ideal slice level. The variable range of the second slice level is:
It needs to be as wide as the first slice level. Usually, since the error amount between the ideal slice level and the first slice level is small, the absolute value of the difference value between the first slice level and the second slice level is small.

When the second slice level is obtained by adding the first slice level and the output value of LPF 27, LP
The output value of F27 is a difference value between the first slice level and the second slice level. Since the absolute value of the difference value between the first slice level and the second slice level is small, L
The dynamic range of the output value of the PF 27 may be small. Similarly, the dynamic range of the output of the phase error detection circuit 26 may be small. When digital processing is performed with the same precision, when the second slice level is obtained by adding the output value of the LPF 27 to the first slice level, LP
LPF compared with the case of directly obtaining from the output value of F27
27 and the phase error detection circuit 26 can be reduced in circuit scale.

[0090]

As described in detail above, according to the present invention,
It is possible to provide a read channel circuit and an optical disk device in which the data punching phase is the best point and the error rate is the best.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of an optical disc playback system to which the present invention is applied.

FIG. 2 is a block diagram showing a configuration of a first embodiment according to a read channel circuit of the present invention.

FIG. 3 is a diagram showing a second slice level control method.

FIG. 4 is a diagram showing a state of reproduction stream generation.

FIG. 5 is a block diagram showing a configuration of a second embodiment of the read channel circuit of the present invention.

FIG. 6 is a diagram showing a configuration of a conventional read channel circuit.

FIG. 7 is a diagram showing a state of generation of a phase error detection pulse with offset and an offset removal pulse, and a waveform of a current flowing through an addition resistor.

FIG. 8 is a diagram showing a data configuration and a data signal envelope at a data area switching point of a DVD-RAM.

FIG. 9 is a diagram showing a state of a phase error detection pulse with offset and an offset removal pulse when a data signal cannot be binarized at an ideal slice level.

FIG. 10 is a diagram showing a configuration of a binarization circuit and a clock generation circuit that compare only the rising edge of an RF signal with the phase of a reproduced clock.

FIG. 11 is a diagram illustrating a state of an RF signal and a reproduction clock when a data signal is binarized at a non-ideal slice level.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Optical disk 5 ... RF amplifier 8 ... DVD level slice and PLL circuit 20 ... High-pass filter 21, 22 ... Comparator (binary conversion means) 23 ... DSV measurement circuit 24, 27 ... Low-pass filter 25, 28 ... D / A conversion circuit 26 phase error detection circuit (detection means) 29 reproduced stream generation circuit (second generation means) 30 phase comparator 34 loop filter 36 VCO 107 system controller

Claims (7)

[Claims] 1. A read channel circuit for binarizing a received channel stream and generating a reception clock synchronized with the channel stream, a first binarization for binarizing the channel stream at a first slice level. Means, a second binarizing means for binarizing the channel stream at a second slice level, and a receiving clock phase-synchronized with the binarized signal binarized by the first binarizing means. A first generation unit for generating a signal; and a phase difference between a binary signal binarized by the second binarization unit and a reception clock signal generated by the first generation unit, Changing means for changing the second slice level so as to be opposite to a phase difference between the binary signal binarized by the first binarizing means and the reception clock signal generated by the first generating means; And the first The binarized signal from the binarizing means second 2
A second generation means for generating a reproduction channel stream signal by combining the binary signal from the value conversion means with a binary signal. 2. A read channel circuit for binarizing a received channel stream and generating a reception clock synchronized with the channel stream, wherein the channel stream is binarized at a first slice level. Means, a second binarizing means for binarizing the channel stream at a second slice level, and a receiving clock phase-synchronized with the binarized signal binarized by the first binarizing means. A first generation unit for generating a signal; and a phase difference between a binary signal binarized by the second binarization unit and a reception clock signal generated by the first generation unit, Changing means for changing the second slice level so as to be opposite to a phase difference between the binary signal binarized by the first binarizing means and the reception clock signal generated by the first generating means; And the first The binarized signal from the binarizing means second 2
A second generation means for generating a reproduction channel stream signal by combining the binary signal from the value conversion means with a binary signal. 3. A read channel circuit for binarizing a reception channel stream whose digital sum value is controlled and generating a reception clock synchronized with the channel stream, wherein the channel stream is binarized at a first slice level. First binarizing means for converting the channel stream into binary data at a second slice level, and a binary value binarized by the first binarizing means. Of the coded signal
A first generation unit that generates a reception clock signal that is phase-synchronized so that a phase difference from the phase reference becomes zero, using the edge of the polarity as a phase reference, and binarized by the first binarization unit. DS of the binarized signal
Changing means for changing the first slice level so that V becomes zero; and a second signal of the binarized signal binarized by the second binarizing means.
Detecting means for detecting a correction level at which a phase difference between a polarity edge and a phase reference point of a received clock signal generated by the first generating means becomes zero; and a first slice level changed by the changing means And the correction level detected by the detection means, and the second
Adding means for setting a slice level of the first signal, and a first signal of the binarized signal binarized by the first binarizing means.
Second generation means for generating a reproduction channel stream signal having a polarity edge occurrence time and a second polarity edge occurrence time of the second binarized signal as a signal polarity inversion time. Read channel circuit. 4. A read channel circuit for binarizing a reception channel stream of which digital sum value is controlled and generating a reception clock synchronized with the channel stream, wherein the channel stream is binarized at a first slice level. First binarizing means for converting the channel stream into binary data at a second slice level, and a binary value binarized by the first binarizing means. Of the coded signal
A first generation unit that generates a reception clock signal that is phase-synchronized so that a phase difference from the phase reference becomes zero, using the edge of the polarity as a phase reference, and binarized by the first binarization unit. DS of the binarized signal
First changing means for changing the first slice level so that V becomes zero, and second changing of the binary signal binarized by the second binarizing means.
The edge of the polarity and the binarized binary data by the first binarizing means.
The second slice level is changed so that the phase difference between the received clock signal generated by the first generation means and the phase reference point which is closest to the edge of the second polarity of the digitized signal becomes zero. And a first binarized signal binarized by the first binarizing unit.
A second generation for generating a reproduction channel stream signal in which the polarity edge occurrence time and the second polarity edge occurrence time of the binarized signal binarized by the second binarization means are used when the signal polarity is inverted. Means, comprising: a read channel circuit. 5. A read channel circuit for binarizing a reception channel stream whose digital sum value is controlled and generating a reception clock synchronized with the channel stream, wherein the channel stream is binarized at a first slice level. First binarizing means for converting the channel stream into binary data at a second slice level, and a binary value binarized by the first binarizing means. Of the coded signal
A first generation unit that generates a reception clock signal that is phase-synchronized so that a phase difference from the phase reference becomes zero, using the edge of the polarity as a phase reference, and binarized by the first binarization unit. DS of the binarized signal
Changing means for changing the first slice level so that V becomes zero; and a second signal of the binarized signal binarized by the second binarizing means.
The edge of the polarity and the binarized binary data by the first binarizing means.
Detecting means for detecting a correction level at which a phase difference from a phase reference point of the received clock signal generated by the first generating means which is closest to the edge of the second polarity of the digitized signal is zero; The changed first slice level and the correction level detected by the detection means are added to obtain the second slice level.
Adding means for setting a slice level of the first signal, and a first signal of the binarized signal binarized by the first binarizing means.
A second generation for generating a reproduction channel stream signal in which the polarity edge occurrence time and the second polarity edge occurrence time of the binarized signal binarized by the second binarization means are used when the signal polarity is inverted. Means, comprising: a read channel circuit. 6. A reading means for irradiating an optical disk with light to read a signal, a first binarizing means for binarizing a signal read by the reading means with a first threshold value, and a reading means for reading the signal by the reading means. Second binarizing means for binarizing the received signal with a second threshold value, and a second binarizing means for generating a reception clock signal phase-synchronized with the binarized signal binarized by the first binarizing means. 1; and a phase difference between the binarized signal binarized by the second binarizing unit and the reception clock signal generated by the first generating unit is the first binary. Changing means for changing the second threshold value so as to correspond to a phase difference between the binarized signal binarized by the converting means and the received clock signal generated by the first generating means; A binarized signal from the binarizing means and the second binarized signal;
An optical disc device comprising: a second generation unit that generates a reproduction signal by combining a binarized signal from the binarization unit. 7. A reading means for irradiating an optical disk with light to read a signal, a first binarizing means for binarizing a signal read by the reading means with a first threshold value, and a reading means for reading the signal by the reading means. Second binarizing means for binarizing the output signal with a second threshold value, and a first binarized signal binarized by the first binarizing means.
A first generation unit that generates a reception clock signal that is phase-synchronized so that a phase difference from the phase reference becomes zero, using the edge of the polarity as a phase reference, and binarized by the first binarization unit. Changing means for changing the first threshold value in accordance with the value of the binarized signal, and a second signal of the binarized signal binarized by the second binarizing means.
Detecting means for detecting a correction value at which a phase difference between a polarity edge and a phase reference point of the received clock signal generated by the first generating means becomes zero; and a first threshold value changed by the changing means; An adding unit that adds the correction value detected by the detecting unit to the second threshold value, and a first binarized signal binarized by the first binarizing unit.
An optical disk, comprising: a second generation unit that generates a reproduction signal in which a polarity edge occurrence time and a second polarity edge occurrence time of the second binarized signal are signal polarity inversion times. apparatus.