JPH0433033A - Data processor and data processing system - Google Patents

Abstract

PURPOSE:To suppress the accumulation of jitter caused by increasing the number of data processors by selecting a clock suitable for a data to be transmitted as a third clock from a first clock generated on the inside and a second clock extracted from the input data, and defining the third clock as a reference when transmitting the data. CONSTITUTION:A clock generating means 103 generates a first clock and transmits it to a clock switching means 106, and a clock extracting means 102 extracts the second clock from the input data and transmits it to a data processing means 101 and the clock switching means 106. According to an instruction from the data processing means 101, the clock switching means 106 selects either the first clock or a second clock and outputs the selected one as the third clock. The data processing means 101 processes the input data with the second clock as a reference and prepares an output data to be transmitted with the third clock as a reference. Thus, the accumulation of jitter caused by increasing the number of data processors can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data processing device. More specifically, the present invention relates to data processing apparatuses that are interconnected using cables to form a system, and to a configuration that reduces data processing failures in each data processing apparatus caused by jitter contained in data.

2. Description of the Related Art In recent years, various data processing systems have become increasingly networked, and it has become more common for a plurality of data processing devices to be connected via a network to form one system. Accordingly, it is desired to improve the reliability of data transmitted over networks.

An example of the data processing system described above will be described below with reference to the drawings. FIG. 9 is a block diagram showing an example of a conventional data processing system.

In FIG. 9, 901 to 904 are first to fourth data processing devices constituting the system, 905 to 907 are input connectors, 908 to 911 are output connectors, 912 to 91
4 is an optical fiber connecting each data processing device.

Each data processing device processes data while exchanging data via optical fibers. For example, from the first data processing device 901 to the third data processing device 9
The data transmitted to the first data processing device 90
1 output connector 908 and passes through the second data processing device 902 to the third data processing device 903.
It is input from the input connector 906 of. The clock that serves as the reference for the data to be transmitted is the first data processing device 901.
occurs, and the remaining data processing devices perform processing such as data latching in accordance with the data extracted from the input data. Here, the data processing device that generates the clock is called the parent device, and the other data processing devices are called the slave devices.

FIG. 10 and FIG. 11 are block diagrams of a master device and a slave device, respectively, which constitute the data processing system of FIG. 9.

In FIG. 10, 1001 is a data processing means;
2 is a clock generation means, and 1003 is an output connector. The data processing means 1001 generates output data using the first clock generated by the clock generation means 1003 as a reference.

In FIG. 11, 1101 is a data processing means;
2 is a clock extraction means, 1103 is an input connector, 11
04 is an output connector. The data processing means 1101 executes all data processing according to the second clock extracted by the clock extraction means 1102.

Problems to be Solved by the Invention However, in the above configuration, each data processing device extracts a second clock from input data using a PLL or the like, and outputs data using this second clock as a reference. Therefore, as the data is sequentially propagated through a plurality of data processing devices, jitter included in the data increases, resulting in a problem of deterioration of the error rate.

In view of the above-mentioned problems, an object of the present invention is to provide a configuration that reduces propagation of jitter between data processing devices and reduces data processing failures within each data processing device caused by jitter contained in data. shall be.

Means for Solving the Problems In order to achieve the above object, the data processing device of the present invention (claim 1) comprises an input connector, a data processing means, a clock generation means, a clock extraction means, and a clock switching means. , an output connector, an external cable is connected to the input connector, input data is sent to the data processing means and the clock extraction means, the clock generation means generates a first clock, and the clock extraction means generates the first clock. The clock extracting means extracts a second clock included in the data input from the input connector, and the clock switching means selects a third clock from the first clock and the second clock, and the clock switching means selects a third clock from the first clock and the second clock. The data processing device generates output data based on the third clock, and the output connector sends the output data to a connected external cable.

Further, the data processing system of the present invention (claim 2) uses a plurality of the above data processing devices, and connects the input connector of one data processing device and the output connector of another data processing device sequentially with a cable, and It uses a configuration in which data is transmitted through a cable.

Further, the data processing device of the present invention (claim 3) includes, in addition to the above-mentioned data processing device, clock request generation means, and the clock request generation means sends a clock request command to the data processing device. The configuration is such that it generates.

Further, the data processing system of the present invention (claim 4) uses a plurality of the above data processing devices, and sequentially connects the input connector of one data processing device and the output connector of another data processing device in a loop shape with a cable. and transmits data through the cable.

Effect With the above configuration, the data processing device of the present invention (claim 1) selects the one suitable for the data to be sent out of the internally generated first clock and the second clock extracted from the input data. It is selected as the third clock and used as a reference when transmitting data.

Furthermore, in the data processing system of the present invention (claim 2), when a clock does not need to be preserved in data transmission from one data processing device to another data processing device constituting the system, the data processing system The internally generated first clock is used as a reference.

Further, the data processing device of the present invention (claim 3) generates a command requesting the transmission destination to send a clock as a reference for data transmission, prior to data transmission.

Further, in the data processing system of the present invention (claim 4), when transmitting data from one data processing device constituting the system to another data processing device, the data processing device of the transmission source transmits the data before starting the data transmission. A request is made to the destination data processing device to send a clock as a reference for data transmission, and the data is sent based on the clock transmitted from the destination data processing device via a loop. The data processing device at the transmission destination processes the data using the clock generated by itself.

Embodiment Hereinafter, a data processing apparatus according to an embodiment (first embodiment) of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a data processing device in an embodiment of the present invention (claim 1), in which 101 is a data processing means, 102 is a clock extraction means, 103 is a clock generation means, and 104 is an input 105 is an output connector, and 1.6 is a clock switching means.

In FIG. 1, clock generation means 103 generates a first clock and sends it to clock switching means 106.

The input connector 104 inputs input data from the connected cable to the data processing means 101 and the clock extraction means 1.
Tell 02. The clock extraction means 102 extracts a second clock from the input data and sends it to the data processing means 101 and the clock switching means 106. Clock switching means 10
6 selects either the first clock or the second clock and outputs it as the third clock according to an instruction from the data processing means 101. Data processing means 10
1 processes input data using the second clock as a reference, creates output data using the third clock as a reference, and sends it to the output connector 105.

Output connector 105 sends output data to a connected cable.

FIG. 2 is a block diagram of the data processing system of the present invention (claim 2), in which 201 to 204 are first to fourth data processing devices constituting the data processing system, and 205 to 20 are
8 is an input connector, 209 to 212 are output connectors, 2
13 to 215 are optical fibers connecting each data processing device. Each data processing device processes data while exchanging data via optical fibers. For example, data transmitted from the first data processing device 201 to the third data processing device 203 is output from the output connector 209 of the first data processing device 201, and is transmitted via the second data processing device 202. , is input from the input connector 207 of the third data processing device 203.

FIG. 3 is a block diagram showing an example of the configuration of the clock extraction means 102 in FIG. 1, in which 301 is a phase comparator;
02, the VCO 1303 is a frequency divider.

In FIG. 3, a phase comparator 301 receives input data and a frequency divider 30
Compare the phases of the outputs of 3 and set the difference as the error voltage to VC.
Send to O302. VCO 302 oscillates according to the error voltage. A frequency divider 303 divides the frequency of the output of the VCO 302 and sends it to the phase comparator 301. This clock extraction means is well known as a PLL, and for example, the frequency divider 303
When the frequency division ratio is set to 2, the VCo 302 synchronously oscillates at twice the frequency of the basic clock of input data.

FIG. 4 is a block diagram showing one configuration example of the clock switching means 106 in FIG. 1, and 401 is a switching control circuit;
402 to 405 are gate circuits constituting switches for switching clocks.

In FIG. 4, control inputs are provided from data processing means 101 of FIG. The switching control circuit 401 sends switching signals to the games 404 and 405 according to the control input. The first clock from the clock generation means 103 is sent to the gate 404.
Then, the second clock from the clock extraction means 102 is input to the gate 403. In this example, the control signal is "high" to open gate 404 to select the first clock, and "high" to select the second clock.
becomes low level. The output of the closed gate is fixed at a "low level", and the output of the open gate is outputted as the third clock via the gate 402.

FIG. 5a is a pad diagram showing the processing flow of the transmission source data processing device (in the example, the first data processing device 201) in FIG. 2, and 501 to 508 indicate the steps of each process.

FIG. 5b shows a data processing device (
It is a pad diagram showing the processing flow of the second data processing device 202 in the example) and the transmission destination data processing device (third data processing device 203 in the example), and 521 to 531 indicate the steps of each process. .

The operation of the data processing apparatus and data processing system configured as described above will be explained below with reference to FIG. Here, we will take as an example a system that includes audio transmission, which has recently become common.

Now, consider a case where the first data processing device 201 in FIG. 2 transmits audio data to the third data processing device 203. When reproducing audio data, it is necessary to accurately reproduce the sampling frequency at the time of recording. In other words, the clock of the first data processing device 201 must be preserved during data transmission (as shown in the pad diagram of FIG. 5, this type of data is referred to herein as real-time data).

First, the flow of processing of the first data processing device 201 will be explained as follows.
This will be explained using figure a. Step 501 is the start of the process. In step 502, it is determined whether the data is real-time data. In the case of real-time data such as audio, in step 503, in addition to the transmission destination (in the example, the third data processing device 203), attached information attached to the data (herein referred to as a header), information about the "real-time data" is added. Record something. If not, step 5
In step 04, the fact that it is "non-real-time data" is recorded. Since it is the data sending source, the clock switching means 106 is set to the first clock side in Stella 7'' 505, and data is sent in steps 506 and 507. After completion, the process ends in step 508.

Next, the flow of processing of the second data processing device 202 will be explained as follows.
This will be explained using figure b. Step 521 is the start of the process. In steps 522 and 523, necessary processing is applied to the input data. Next, in step 525, it is determined whether the data to be output is real-time data. If it is real-time data, the clock switching means 106 is set to the second clock side in step 526 in order to save the clock, and the transmission destination (in the example, the third data processing device 203) is written in the header in step 527. Record that the data is real-time data. If not, in step 528 the clock switching means 106 is set to the first clock side,
In step 529, the fact that the data is "non-real time data" is recorded. Step 530 depicts sending data. After repeating the above procedure as many times as necessary, as shown in step 524, the process ends in step 531. The processing flow of the third data processing device 203 can also be explained with reference to FIG. 5b, but since it is the destination data processing device, there is no data to be sent, and steps 524 to 530 regarding data sending are not executed.

As described above, in this embodiment, in the case of real-time data, the data processing device through which the data passes uses the second clock extracted from the input data to send the data, so the clock of the transmission source is saved. and normal data processing is possible.

On the other hand, when transmitting data other than real-time data, each data processing device detects this from the header and uses an internally generated first clock to send the data. As a result, clock jitter is not transmitted beyond the data processing devices, and it is possible to prevent the error rate from worsening due to an increase in the number of data processing devices through which data passes.

FIG. 6 is a block diagram showing the configuration of a data processing device in an embodiment (second embodiment) of the present invention (Claim 3), in which 601 is a data processing means, 602 is a clock extraction means, and 603 is a clock. generation means; 604 is an input connector;
605 is an output connector, 606 is a clock switching means, 6
07 is a clock generation requesting means. The clock extracting means 602 and the clock switching means 606 in FIG.
This is the same as Figure 1, and Figures 3 and 4 are quoted here.

In FIG. 6, the clock request generation means 6 is added to the embodiment of FIG.
07 has been added. The clock request generation means 607 generates a command to request the transmission destination to transmit a clock serving as a reference for transmission, as necessary, prior to transmission of data from the data processing means 601.

FIG. 7 is a block diagram of the data processing system of the present invention (M Gyuhi 4), and 701 to 704 are the first
~4th data processing device, 705 to 708 are input connectors, 709 to 712 are output connectors, and 713 to 716 are optical fibers connecting each data processing device. Each data processing device processes data while exchanging data via optical fibers. For example, data transmitted from the first data processing device 701 to the third data processing device 7゜3 is output from the output connector 709 of the first data processing device 701, and is transmitted via the second data processing device 702. and is input from the input connector 707 of the third data processing device 703.

FIG. 8a is a pad diagram showing the processing flow of the transmission source data processing device (in the example, the first data processing device) in FIG. 7, and 801 to 815 indicate the steps of each process.

Indicates the

FIG. 8b is a pad diagram showing the flow of the clock sending process of the destination data processing device (in the example, the third data processing device) in FIG. 7, and 821 to 826 indicate the steps of each process.

The operation of the data processing apparatus and data processing system configured as described above will be explained below with reference to FIG.

The second embodiment is characterized in that each data processing device is connected in a loop, and that the clock generation request means requests the data processing device at the transmission destination to send out a clock that is used as a reference for transmission. be. Here again, the transmission of audio data will be taken as an example.

Now, consider a case where the first data processing device 701 in FIG. 7 transmits audio data already recorded on a recording medium such as a CD to the third data processing device 703. In this case, the data sent is real-time data.

First, the flow of processing of the first (transmission source) data processing device 701 will be explained according to FIG. 8a.

Step 801 is the start. In step 802, it is checked whether the output data is real-time data. Steps 812 to 815 are for non-real-time data and are the same processing as in the first embodiment, so their explanation will be omitted. If the output data is real-time data, a clock transmission request is sent to the third (transmission destination) data processing device 703 in step 804 . Step 805,8
08 is the waiting time until the requested clock arrives. In step 807, the transmission destination and the fact that it is "real-time data" are set in the header. At step 808, the clock switching means 106 is set to the second clock side.

Steps 809 and 810 indicate sending data. In this embodiment, this second clock is used to read and transmit audio data recorded on a recording medium such as a CD.

After completion, in step 811, a request is made to the transmission destination to stop clocking and checking, and in step 803, the process ends. The processing procedure of the second data processing device 702 through which data passes is the same as that of the second data processing device 202 of the first embodiment.

Next, the flow of processing of the third (transmission destination) data processing device 703 will be explained according to FIG. 8b.

The procedure for processing input data is the same as that shown in FIG. 5b, and the processing for the clock transmission request will be described here. In FIG. 8b, step 821 is the start of interrupt processing for a request instruction. In step 822, it is determined whether the request is a clock transmission request, and if so, in step 823 clock transmission is started. In step 824, it is determined whether the request is a clock stop request, and if so, in step 825, clock transmission is stopped. Thereafter, in step 826, the interrupt processing is ended and the process returns.

As a result of the above, the first (transmission source) data processing device 701 reads and sends data based on the clock transmitted from the third (transmission destination) data processing device 703. In the above data processing device 703,
It is exactly the same as the first (transmission source) data processing device 701,
Data processing will be performed using a clock that does not contain any distortion or distortion, and the audio will be reproduced correctly and without distortion.

Effects of the Invention As described above, according to the present invention, jitter contained in data transmitted between data processing devices connected by cables can be suppressed from accumulating due to an increase in the number of data processing devices. It is possible to provide a data processing system in which failures due to the above are reduced. Further, since data is transmitted from the data processing device at the transmission source based on the clock supplied from the data processing device at the transmission destination, disturbances due to jitter can be reduced even in the case of real-time data transmission.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a data processing device according to a first embodiment of the present invention, FIG. 2 is a block diagram of a data processing system configured by connecting a plurality of data processing devices shown in FIG. 1, and FIG. FIG. 4 is a block diagram showing an example of the configuration of the clock extraction means in FIG. 1, FIG. 4 is a block diagram showing an example of the configuration of the clock switching means in FIG. 1, and FIG. 5 explains the operation of the data processing system in FIG. 2. 8 is a block diagram showing a data processing device according to a second embodiment of the present invention, and FIG. 7 is a block diagram of a data processing system configured by connecting a plurality of data processing devices shown in FIG. 6. 8 is a pad diagram explaining the operation of the data processing system shown in FIG. 7, FIG. 9 is a block diagram showing the configuration of a conventional data processing system, and FIGS. 10 and 11 are diagrams of the data processing device in the conventional example. FIG. 2 is a block diagram showing the configuration. 101.601...Data processing means, 102゜6
02... Clock extraction means, 103,603...
・Clock generation means, 104,205~208°7
05-708...Input connector, 105.209
~212,605,709~712-...Output connector, 106,606...Clock switching means, 201
．． 701...first data processing device, 202.702
...Second data processing device, 203.703...Third data processing device, 204.704...Fourth data processing device, 213-215, 713-715...Optical fiber, 301 ...Phase comparator, 302...
V.C.O. 303... Frequency divider, 401... Switching control circuit,
402-405...Gate circuit, 607...Clock request generation means. Name of agent: Patent attorney Shigetaka Awano Haka 1 person 213~
215 First plan C1y'7! w Te f9102 or 5 402-405 Guto Nikogori 07 Wa Pregnancy Rib 1031P et al. Figure Figure 713-716 Kabuto Fufui V Figure (b) Mouth

Claims (4)

[Claims] (1) An input connector for connecting a cable from an external device, a clock generation means for generating a first clock, and a clock extraction means for extracting a second clock from input data input through the input connector. and a clock switching means for selecting one of the first clock and the second clock and outputting it as a third clock, and processing the input data according to the second clock and processing the input data according to the third clock. A data processing device comprising: a data processing unit that generates output data; and an output connector that sends the output data of the data processing unit to a cable connected from the outside. (2) A data processing system comprising a plurality of data processing apparatuses according to claim 1, wherein an input connector of one data processing apparatus and an output connector of another data processing apparatus are sequentially connected by a cable, and data is transmitted through the cable. (3) An input connector for connecting a cable from an external device, a clock generation means for generating a first clock, and a clock extraction means for extracting a second clock from input data input through the input connector. and a clock switching means for selecting one of the first clock and the second clock and outputting it as a third clock, and processing the input data according to the second clock and processing the input data according to the third clock. A data processing means for generating output data, an output connector for sending the output data of the data processing means to a cable connected from outside, and a clock request generation means for generating a clock request instruction to the data processing means. Processing equipment. (4) A plurality of data processing devices according to claim 3 are provided, the input connector of one data processing device and the output connector of the other data processing device are sequentially connected in a loop shape with a cable, and data is transmitted through the cable. processing system.