JP3085420B2 - Transmission signal instantaneous interruption communication device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a communication processing device for wired communication having a loop-type or ring-type transmission path form such as an AN (local area network) system.

[0002]

2. Description of the Related Art In recent years, with the increase in capacity and reliability of communication, wired communication systems taking the form of loop or ring transmission lines have been increasing.

In the case of a wired communication system adopting such a loop-type or ring-type transmission path, the transmission paths are connected, that is, a "closed loop" (a state in which the apparatus can receive data transmitted by the apparatus itself). It is premised that the transmission path is disconnected due to some failure or the like, that is, an “open loop” (reverse to “closed loop”) may occur. In order to improve the reliability of the communication system, even if such an “open loop” occurs due to a transmission line disconnection, a device failure, or the like, it is necessary to eliminate instantaneous interruption of the system at a location other than the failure location.

FIG. 7 shows an example of a conventional wired communication processing apparatus having a loop-type transmission path. In this figure, 2
Reference numeral 01 denotes a wired communication processing device. A receiving unit 202 receives data from the optical transmission line, separates a reception clock from the data, and outputs the data as reception data and a reception clock. Reference numeral 203 denotes a clock oscillating unit that oscillates its own clock in the wired communication processing device 201.

[0005] Reference numeral 204 denotes a clock changing unit which changes the clock signal of the received data from the received clock to its own clock. A data processing unit 205 receives the received data output from the clock switching unit 204 and the self-clock output from the clock oscillation unit 203, transfers the received data to another communication processing device, and performs other communication processing. The data received from the device is output as operation data on the own clock.

A data delay unit 206 receives the received data and the received clock, delays the received data, and outputs the result as bypass data. An operation / bypass selector unit 207 receives the bypass data output from the data delay unit 206 and the operation data output from the data processing unit 205, selects one of them, and outputs it as transmission data together with a transmission clock. . A transmission unit 208 receives the transmission data and the transmission clock output from the operation / bypass selector unit 207, and transmits the transmission data to the optical transmission line with the transmission clock.

As shown in FIG. 1, in this communication processing device, if any failure occurs in the data processing unit 205 of the communication processing device 201, a bypass mode is selected to bypass received data. Is done.

When this bypass mode is selected, the signal path is as follows. That is, the optical signal received from the optical transmission line is first converted by the receiving unit 202 into received data. Next, the reception data becomes bypass data via the data delay unit 206, and after passing through the operation / bypass selector unit 207, the transmission unit 208
It is converted into an optical signal and sent out to an optical transmission line.

[0009]

However, in this type of conventional wired communication processing device, the data processing unit 2
When switching between the operation mode and the bypass mode when a failure occurs in the network 05, an instantaneous data interruption occurs because the operation system clock and the bypass system clock are different. This instantaneous interruption spreads to the downstream communication processing device and hinders normal operation as a system.

When a double fault such as a stoppage of an optical signal on an optical transmission line due to a failure of an upstream communication processing device or the like occurs while operating in the bypass mode, the communication processing device 201 The optical signal to be transmitted to the transmission line also stops, and, similarly to the above, the instantaneous interruption spreads to the downstream communication processing device, preventing normal operation as a system.

The present invention has been made in view of such circumstances, and any failure occurs in a transmission line to stop a reception clock or reception data, or a data processing unit or a transmission It is an object of the present invention to provide a transmission signal non-interruption communication device that eliminates an instantaneous interruption of a transmission signal on a transmission line even when a failure occurs in a unit.

[0012]

FIG. 1 is a block diagram showing the configuration of the present invention. As shown in FIG.
A receiving unit 101 that receives data from a transmission path and separates a reception clock from the data and outputs the data as reception data and a reception clock, a transmission clock oscillation unit 102 that outputs a transmission clock, and a reception clock that is output from the reception unit 101 A bypass memory unit 103 that receives the data and the reception clock, receives the transmission clock output from the transmission clock oscillating unit 102, replaces the reception data with the transmission clock, and outputs the data as processing data and bypass data;
Upon receiving the processing data output from the bypass memory unit 103 and the transmission clock output from the transmission clock oscillating unit 102, the processing data is transferred to another communication processing device, and the data received from the other communication processing device is transferred. Data processing unit 1 that outputs operation data on transmission clock
04, an operation / bypass selector unit 105 that receives bypass data output from the bypass memory unit 103 and operation data output from the data processing unit 104, selects one of them, and outputs the selected data as transmission data. A transmission unit for receiving the transmission data output from the bypass selector unit 105 and the transmission clock output from the transmission clock oscillating unit 102, transmitting the transmission data on the transmission clock, and transmitting the transmission data to a transmission path;
A transmission signal non-interruptible communication apparatus characterized in that the same delay amount as that of data processing added by the data processing unit 104 is added to bypass data and output to the operation / bypass selector unit 105. is there.

Incidentally, the bypass memory section 103 may be constituted by a large number of latch circuits, or may be constituted by a shift register or a RAM.

[0014]

According to the present invention, the received data received by the receiving unit 101 is output as processing data and bypass data after being replaced with a transmission clock by the bypass memory unit 103. Among them, the processing data is input to the data processing unit 104, and the data processing unit 104 outputs operation data.

In the bypass memory unit 103, a delay amount equal to the delay amount of the data processing added by the data processing unit 104 is added to the bypass data and output to the operation / bypass selector unit 105. The bypass data is stored in the operation / bypass selector unit 10 together with the operation data.
5, one of the bypass data and the operation data is selected and output as transmission data, and the transmission data output from the operation / bypass selector unit 105 is
The data is transmitted to the transmission path on the transmission clock.

That is, in the present invention, the transmission clock oscillating unit 102 is mounted inside the device, and the transmission system including the data processing unit 104 is operated by the output clock. That is, the components other than the receiving unit 101 are operated by the transmission clock output from the transmission clock oscillation unit 102, which is the own device clock.
Also, the bypass memory unit 10 at the next stage of the receiving unit 101
3, the received data operating in synchronization with the reception clock is synchronized with the transmission clock, a part of the data is sent to the data processing unit 104 as processing data, and another part is data added by the data processing unit 104. The bypass data having the same delay amount as the processing delay amount is output to the operation / bypass selector unit 105 as the bypass data.

Therefore, there is no instantaneous interruption of the clock when switching between the operation data and the bypass data, so that there is no instantaneous interruption of the signal output from the transmission unit 106 at the time of switching between the operation and the bypass. Further, even in the case of a reception clock failure due to a stop of a signal from a transmission line in the bypass mode, an instantaneous interruption of a signal output from the transmission unit 106 does not occur.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the drawings. The present invention is not limited by this.

FIG. 2 is a circuit block diagram showing a configuration of an embodiment of a transmission signal instantaneous interruption communication apparatus according to the present invention, which is applied to a communication processing apparatus constituting a loop type optical LAN (local area network) system. Is shown. In this figure, reference numeral 1 denotes a wired communication processing device. A receiving unit 2 receives data from the optical transmission line, converts the data into an electric signal, separates a reception clock from the data, and outputs it as reception data and a reception clock. A transmission clock generator 3 generates a transmission clock in the wired communication processing device 1.

Reference numeral 4 denotes a bypass memory unit which receives the reception data and the reception clock output from the reception unit 2, receives the transmission clock output from the transmission clock generation unit 3, and synchronizes the reception data with the transmission clock. Thereafter, it is output as processing data and bypass data.

Reference numeral 5 denotes a data processing unit which receives the processing data output from the bypass memory unit 4 and the transmission clock output from the transmission clock generation unit 3, and the contents of the received processing data are placed below the own device. If the data is for the communication terminal 6 located, the data is transferred to the communication terminal 6 as terminal reception data. When transmitting data, the communication terminal 6 notifies the data processing unit 5 of a transmission request and transmits terminal transmission data.
Upon receiving the transmission request from the communication terminal 6, the data processing unit 5 switches the data output from the data processing unit 5 to terminal transmission data and outputs the data as operation data.

Reference numeral 7 denotes an operation / bypass selector unit, and reference numeral 8 denotes a processor unit 8 for switching the operation / bypass selector unit 7. The operation / bypass selector unit 7 receives the bypass data output from the bypass memory unit 4 and the operation data output from the data processing unit 5, and receives the operation data from the processor unit 8.
In accordance with the switching signal output from the controller, one of the bypass data and the operation data is selected and output as transmission data.

A transmission unit 9 receives the transmission data output from the operation / bypass selector unit 7 and the transmission clock output from the transmission clock generation unit 3 and transmits the transmission data on the transmission clock to the optical transmission line. I do.

Here, the bypass memory unit 4 adds the same delay amount as that of the data processing added by the data processing unit 5 to the bypass data and outputs the same to the operation / bypass selector unit 7.

Hereinafter, the detailed configuration of the bypass memory unit 4 will be described with reference to four examples. FIG. 3 shows the bypass memory unit 4.
FIG. 3 is a circuit block diagram illustrating a first example of FIG. In this figure, reference numeral 11 denotes a write data counter which counts the number of received data based on a reception clock and transmits the count value to a read / write controller 12.

Reference numeral 13 denotes a multiplexer unit which receives the received data and transmits it to the SR latch unit 14 at the next stage. The SR latch section 14 is composed of a number of SR latches, and an arbitrary one is selected from the SR latches.
This selection is performed according to an instruction from the read / write control unit 12. The SR latch unit 14 includes the multiplexer unit 1
3 and sends out the latched data to the selector 15 for processing and the selector 16 for bypass.

The processing selector 15 is an SR latch 14
, And sequentially selects any one of the outputs from the SR latch unit 14 and outputs it as bypass data. . Selection of processing data and selection of bypass data are performed by a select signal from the read / write control unit 12.

Reference numeral 17 denotes a processing read data counter which counts the number of processing data from the transmission clock and the processing data, and transmits the count value to the read / write controller 12.

Reference numeral 18 denotes a bypass read data counter which counts the number of bypass data based on a transmission clock and bypass data and transmits the count value to the read / write controller 12.

The read / write control section 12 receives the count value of the write data from the write data counter section 11 and also receives the count value of the read data for processing from the read data counter section 17 for processing and reads the count value of the read data counter section for bypass. 18 to receive the count values of the bypass read data. Also, it receives data delay control instruction data from outside. Then, the signal is transmitted to the multiplexer unit 13, the processing selector unit 15, and the bypass selector unit 16.

The read / write control unit 12 compares the amount of write data from the write data counter unit 11 with the amount of read data from the processing read data counter unit 17 and the bypass read data counter unit 18. It checks if there is any unread data in the SR latch unit 14, and if there is no unread data, outputs an underflow notification signal indicating that it does not exist to the outside.

Further, after writing to the SR latch unit 14, data which has never been read is stored in the SR latch unit 14.
If it is present in the latch unit 14, it outputs an overflow notification signal to the outside.

In the first example of the bypass memory section 4, two blocks for outputting data are provided. That is, two blocks are provided: a block composed of the processing selector unit 15 and the processing read data counter unit 17, and a block composed of the bypass selector unit 16 and the bypass read data counter unit 18. It is configured to delay.

FIG. 4 is a circuit block diagram showing a second example of the bypass memory unit 4. In this figure, reference numeral 21 denotes a clock transfer unit which receives a reception clock and reception data, and sends out processing data synchronized with a transmission clock by a transmission clock.

Reference numeral 22 denotes a shift register unit which receives the processing data output from the clock transfer unit 21 to generate a data delay, and converts each delay data into a selector unit 23.
To send to. The selector unit 23 includes the shift register unit 22
, And selects the bypass data in accordance with an instruction signal from the bypass delay control unit 24. The bypass delay control unit 24 gives a selection instruction to the selector unit 23 in response to an external data delay control instruction, and adjusts the delay amount of bypass data.

In the second example of the bypass memory unit 4, the received data is converted into processing data synchronized with the transmission clock by changing the clock signal, and then the data is delayed by the shift register unit 22 and the selector unit 23. Is added to create bypass data.

FIG. 5 is a circuit block diagram showing a third example of the bypass memory unit 4. In this figure, reference numeral 31 denotes a clock transfer unit which receives a reception clock and reception data, and transmits processing data synchronized with a transmission clock by a transmission clock.

Numeral 32 denotes a memory unit composed of a RAM, in which processing data is written by the write address from the write / read data address control unit 33, and by-pass data by the read address from the write / read data address control unit 33. Is read.

Write / read data address control unit 33
Counts the number of processing data written in the memory unit 32, and determines a write address from the count value. Further, a data delay control instruction signal is externally received, and a read address of bypass data to be read from the memory unit 32 is determined based on the data delay control instruction and the write address. Further, as a warning such as the approach of the write address and the read address, a notice of overflow and underflow is output.

In the third example of the bypass memory unit 4, after converting the received data into processing data synchronized with the transmission clock, the processing data is written into the memory unit 32 and the write / read data address control unit is written. By controlling reading from the memory unit 32 by 33, the bypass data is delayed.

FIG. 6 is a circuit block diagram showing a fourth example of the bypass memory unit 4. In this figure, reference numeral 41 denotes a shift register unit, which delays data according to a reception clock and reception data.

Reference numeral 42 denotes a selector unit, which receives the output of each stage of the shift register unit 41 and receives a bypass delay control unit 43
, One of the outputs of each stage from the shift register section 41 is selected. Bypass delay controller 43
Receives a data delay control instruction signal from the outside, and supplies a selection signal to the selector unit 42 based on the data delay control instruction.

Reference numeral 44 denotes an operation data / clock changing unit, which converts data received from the shift register unit 41 into processing data synchronized with the transmission clock. Reference numeral 45 denotes a bypass data / clock changing unit which converts the delay data received from the selector unit 42 into bypass data synchronized with the transmission clock.

In the fourth example of the bypass memory unit 4, an operation data / clock changing unit 44 for changing the clock before performing the data delay processing, and changing the clock after performing the data delay processing. A bypass data / clock switching unit 45 is provided to delay the bypass data.

In the wired communication processing device 1 shown in FIG. 2, data is received from the optical transmission line, and the received data is transmitted to the communication terminal 6. Further, the data of the communication terminal 6 is transmitted to the transmission path in response to a transmission request from the communication terminal 6. Hereinafter, the operation of the wired communication processing device 1 will be described.

First, an optical signal from the optical transmission line is received by the receiving unit 1, and received data and a received clock are extracted from the received optical signal. Here, the reception data synchronized with the reception clock is input to the bypass memory unit 4 and converted into data synchronized with the transmission clock.

The received data synchronized with the transmission clock is transmitted to the data processing unit 5 without delay in the bypass memory unit 4 by the operation mode path and the data processing delay added by the data processing unit 5. It divides into a bypass mode path to which the same amount of delay is added.

In the data processing unit 5, if the received data is the data of the communication terminal 6, the data is transferred to the communication terminal 6, and the communication terminal 6 notifies the data processing unit 5 of a transmission request at the time of data transmission. Upon receiving the transmission request, the data processing unit 5 switches the output data from the data processing unit 5 to terminal transmission data and outputs it as operation data.

The output data from the bypass memory unit 4 and the data processing unit 5 are input to the operation / bypass selector unit 7, and the operation / bypass selector unit 7 switches the output path according to an instruction from the processor unit 8. Either the bypass data or the operation data is selected and sent to the transmission unit 9 as transmission data.

The transmission unit 9 converts the transmission data received from the operation / bypass selector unit 7 into an electric / optical signal, and transmits the converted data as an optical signal to the transmission line in synchronization with a transmission clock.

In the wired communication processing device 1, as a normal operation, an operation mode for transmitting and receiving data to and from the communication terminal 6 is normally selected. That is, the operation mode in which the operation data is output as the transmission data is selected by the operation / bypass selector unit 7.

If a failure occurs in the data processing unit 5, the communication terminal 6, or the like during the normal operation, sending the transmission signal of the own device to the transmission path may cause a failure in the entire system. Therefore, the mode is switched to the bypass mode in order to disconnect the wired communication processing device 1 from the entire system. Specifically, the operation / bypass selector 7 selects a bypass mode in which bypass data is output as transmission data.

Even if the operation / bypass selector unit 7 switches between the operation data and the bypass data, the same delay amount as the delay amount added by the data processing unit 5 is added in the bypass memory unit 4. The device delay as a system does not change, and does not affect downstream communication processing devices such as loss of frame synchronization of the transmission path.

Further, even when the reception light on the transmission line is stopped due to a failure of the upstream communication processing device or a transmission line failure, the bypass memory unit 4, the data processing unit 5, and the transmission unit 9 keep the transmission clock generation unit 3 Since the operation is performed by the transmission clock, the transmission signal is not stopped, and the downstream communication processing device is not affected by the loss of frame synchronization of the transmission path.

As described above, the transmission frame from the wired communication processing device 1 is apparently output normally,
Prevents the transmission of interference to communication processing devices downstream of the optical transmission path,
Normal operation as a communication system can be maintained.

In the above embodiment, a circuit for generating a synchronous frame pattern of a transmission line format may be provided at a stage subsequent to the operation / bypass selection circuit of the operation / bypass selector unit 7. The synchronization frame pattern generation circuit may be provided at a stage subsequent to the transmission clock synchronization circuit of the bypass memory unit 4.

[0057]

As described above, according to the present invention, it is possible to guarantee instantaneous interruption of the transmission side of the communication processing apparatus. This can be easily performed, and the reliability of the system can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of the present invention.

FIG. 2 is a circuit block diagram showing a configuration of an embodiment of a transmission signal hitless communication device of the present invention.

FIG. 3 is a circuit block diagram illustrating a first example of a bypass memory unit.

FIG. 4 is a circuit block diagram illustrating a second example of the bypass memory unit.

FIG. 5 is a circuit block diagram illustrating a third example of the bypass memory unit.

FIG. 6 is a circuit block diagram illustrating a fourth example of the bypass memory unit.

FIG. 7 is a circuit block diagram illustrating an example of a conventional wired communication processing device having a loop transmission path configuration.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 wired communication processing device 2 reception unit 3 transmission clock generation unit 4 bypass memory unit 5 data processing unit 6 communication terminal 7 operation / bypass selector unit 8 processor unit 9 transmission unit 11 write data counter unit 12 read / write control unit 13 multiplexer unit Reference Signs List 14 SR latch section 15 Processing selector section 16 Bypass selector section 17 Processing read data counter section 18 Bypass read data counter section 21, 31 Clock transfer section 22, 41 Shift register section 23, 42 Selector section 24, 43 Bypass Delay control unit 32 memory unit 33 write / read data address control unit 44 operation data / clock transfer unit 45 bypass data / clock transfer unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 12/437

Claims (4)

(57) [Claims] 1. A receiving unit (101) for receiving data from a transmission line, separating a receiving clock from the data, and outputting the receiving clock as a receiving data and a receiving clock, and a transmitting clock oscillating unit (102) for outputting a transmitting clock.
Receiving the reception data and the reception clock output from the reception unit (101),
And a bypass memory unit (103) that receives the transmission clock output from the controller and replaces the received data with the transmission clock, and then outputs the processed data and bypass data as processing data and processing data output from the bypass memory unit (103). Receiving the transmission clock output from the transmission clock oscillating unit (102), transferring the processing data to another communication processing device, and outputting the data received from the other communication processing device on the transmission clock as operation data. Receiving the bypass data output from the bypass memory unit (103) and the operation data output from the data processing unit (104), and selects one of them to output as transmission data. Operation / bypass selector (105) and transmission output from operation / bypass selector (105) And a transmission unit (106) for receiving the transmission clock output from the transmission clock oscillating unit (102), transmitting transmission data on the transmission clock, and transmitting the transmission data to the transmission path. The bypass memory unit (103) Processing unit (10
A transmission signal non-interruptible communication device characterized in that a delay amount equal to the delay amount of data processing added in 4) is added to bypass data and output to the operation / bypass selector unit (105). 2. The communication device according to claim 1, wherein the bypass memory unit comprises a plurality of latch circuits. 3. The device according to claim 1, wherein the bypass memory section comprises a shift register.
The communication device without transmission signal instantaneous interruption described in the above. 4. The RAM according to claim 1, wherein the bypass memory unit is a RAM.
2. The transmission signal hitless communication device according to claim 1, comprising: