JP3070546B2 - Alarm transfer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an alarm transfer circuit for a digital communication system comprising a transmitting section and a receiving section.

[0002]

2. Description of the Related Art Conventionally, in an alarm transfer circuit of this type, an alarm transfer bit is assigned by configuring a frame unique to a wireless section, and an alarm is transferred using the bit, or a data signal is transmitted. Is fixed to a predetermined state, and the lower station detects this predetermined state to transmit an alarm.

[0003] For example, in the technique disclosed in Japanese Patent Laid-Open Publication No. Hei 3-226036 (first conventional example), information of an input signal disconnection detected by a transmission unit is inserted into a time slot in a predetermined frame. It describes that the detection information is transferred to the receiving side.

In the technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-264212 (second conventional example), a plurality of slave units other than the master unit receive a clock signal from one master unit among the plurality of units. It describes that when any one of the units detects a clock loss, the slave unit that detects the clock loss becomes a master unit and can continue communication.

[0005]

However, the prior art described above has the following drawbacks.

[0006] The first problem is that the signal transmission efficiency is reduced according to the first conventional example.

The reason is that a specific bit is prepared in advance in a radio frame in case of a failure,
This is because it is necessary to perform signal transmission in a state where this bit is included even in the normal transmission state.

[0008] The second problem is that the circuit size becomes large according to the second conventional example.

The reason is that, when an alarm is transmitted with a data signal fixed in a predetermined state, the data signal cannot be fixed in a predetermined state when the input clock signal is cut off. This is because a clock signal generation circuit or another unit having exactly the same configuration as itself needs to be provided in the system in order to obtain another clock signal for achieving the following.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional circumstances, and has been made in order to solve the above-mentioned drawbacks inherent in the conventional technology. Therefore, an object of the present invention is to reduce the signal transmission efficiency without reducing the signal transmission efficiency. It is another object of the present invention to provide a new alarm transfer circuit that can easily transfer an alarm when a failure occurs without increasing the circuit scale.

[0011]

In order to achieve the above object, an alarm transfer circuit according to the present invention comprises a storage circuit for converting a speed for forming a frame for a radio section, and a synchronous circuit for synchronizing with an input clock signal. PLL (Phase Locked Loop) that generates a clock signal after speed conversion
p) circuit, a timing generation circuit for generating timing signals of various timings based on the clock signal generated by the PLL circuit, and an input signal to the storage circuit in advance based on a detection result of a clock disconnection detection circuit described later. A data fixing circuit for fixing a fixed data signal, a clock signal disconnection detecting circuit for detecting a signal disconnection of an input clock signal, and a data fixing circuit, a storage circuit, and a PLL circuit based on a detection result of the clock disconnection detecting circuit. A clock selection circuit for switching a clock signal to be output from an input clock signal to a timing signal generated by a timing generation circuit.

The data fixing circuit outputs an input signal to the storage circuit as it is during a normal operation. However, when the clock signal disconnection detecting circuit detects the disconnection of the input clock signal, or when the input signal disconnection is detected. In this case, a data signal written to the storage circuit is fixed to a predetermined data signal.

[0013] The storage circuit has a function of forming a frame for a radio section with respect to the input signal and converting a transmission rate in order to add various types of information. And generating a clock signal after the speed conversion in synchronism with the clock signal, reading out a data signal for a wireless section from the storage circuit by the clock signal, and outputting the data signal to a receiving side.

[0014]

According to the present invention, when an input signal is interrupted, data is fixed to a predetermined data signal, so that the transmission efficiency of the line does not decrease.

Further, even if the clock signal is interrupted among the input signals, the clock is reselected to another clock, so that the alarm state can be transferred.

[0016]

Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a digital communication system using an alarm transfer circuit according to the present invention.

Referring to FIG. 1, an alarm transfer circuit according to the present invention includes a storage circuit 11, a PLL (Phase Lock).
ed Loop) circuit 12, timing generation circuit 13,
It comprises a data fixing circuit 14, a clock disconnection detection circuit 15, and a clock selection circuit 16.

The clock disconnection detecting circuit 15 is constituted by, for example, a flip-flop.
Is easily constituted by, for example, a logic circuit composed of three NAND circuits or the like, or a selector or the like.

The storage circuit 11 forms a frame for a radio section with respect to an input signal, and plays a role of a buffer for converting a transmission rate in order to add various information. During normal operation, the input signal is written to this storage circuit and
It is read by the clock signal generated by the L circuit 12.

The PLL circuit 12 generates a clock signal after the speed conversion in synchronization with the input clock signal, and reads the data signal for the radio section from the storage circuit 11 by the clock signal after the speed conversion as described above. Output to the side. The clock signal generated by the PLL circuit 12 is also input to a timing generation circuit 13, and the timing signal generation circuit 13 generates various timing signals synchronized with a frame phase for a wireless section.

The data fixing circuit 14 outputs an input signal to the storage circuit 11 as it is during normal operation, but determines a data signal to be written to the storage circuit 11 in advance when an input signal disconnection is detected. Fixed to the received data signal. By detecting the predetermined fixed data on the receiving side, an alarm is transferred to the receiving side.

The clock disconnection detecting circuit 15 detects an abnormal state when the input clock signal is disconnected due to a failure or the like, and outputs clock disconnection information to the data fixing circuit 14 and the clock selecting circuit 16. The data fixing circuit 14 outputs predetermined data to the storage circuit 11 based on the clock loss information from the clock loss detection circuit 15.

In the clock selection circuit 16, a clock signal to be output to the data fixing circuit 14, the storage circuit 11, and the PLL circuit 12 is generated by the timing generation circuit 13 from the input clock signal based on the detection result of the clock cutoff detection circuit 15. Switch to the specified timing signal.

Next, the operation of the embodiment of the present invention will be described in detail.

Here, two examples will be described, and in each case how the alarm is forwarded in the digital communication system will be described.

The first example considers a case in which an input data signal becomes an obstacle, thereby transmitting an alarm. At this time, it is assumed that the input clock signal remains normal.

In this case, since the input clock signal is normal, no clock loss is detected by the clock loss detection circuit 15, and no clock failure is reported to the data fixing circuit 14 and the clock selection circuit 16. , And remains in a normal operating state. That is, the data fixing circuit 14 outputs the input data signal to the storage circuit 11 as it is. In this case, since the input data signal is disconnected,
A fixed pattern is output.

The clock selection circuit 16 also selects the input clock selected in the normal operation state, whereby the output data of the data fixing circuit 14 is written to the storage circuit 11. The written fixed pattern is read by the output clock from the PLL circuit 12 and sent to the wireless section.

The second example considers a case in which an input clock signal becomes an obstacle, thereby transmitting an alarm. In this case, since an abnormality of the input clock is detected by the clock loss detection circuit 15, the data fixing circuit 14 fixes the data signal to a predetermined data signal such as all "1" or all "0". The clock selection circuit 16 selects a clock signal from the timing generation circuit 13 and outputs the clock signal to the data fixing circuit 14, the storage circuit 11, and the PLL circuit 12.

At this time, the data predetermined by the data fixing circuit 14 is correctly written into the storage circuit 11, and the PLL circuit 12 is a clock signal generated from the clock signal generated by the PLL circuit itself. It is in a free run state. Thereby, the output clock signal of the clock selection circuit 16 operates stably,
The data fixed state in which the interruption of the input signal is transferred to the receiving side is maintained.

Here, a case is considered where the clock selection state by the clock selection circuit 16 does not change when the input clock is cut off, that is, when the clock selection circuit 16 does not exist.

In this case, the clock to the data fixing circuit 14, the storage circuit 11, and the PLL circuit 12, to which the output clock of the clock selection circuit 16 is supplied, is cut off. Thereby, on the writing side of the storage circuit 11,
The state immediately before the clock is cut off remains stored, and even if the output data signal of the data fixing circuit 14 is fixed, the data read from the storage circuit 11 is the data content for transferring an alarm to the receiving side. It is not always possible to notify the receiving side of the alarm state correctly.

As described above, even if the input clock signal is interrupted, the alarm signal can be transferred regardless of any failure by always supplying the clock signal to the storage circuit 11. become.

FIG. 2 is a time chart for explaining the operation of the present invention.

Referring to FIG. 2, when the clock loss is detected by the clock loss detection circuit 15 at the point A, the detection signal is supplied to the data fixing circuit 14 and the clock selection circuit 16. This detection signal causes the clock selection circuit 16
Is started, and switches the input clock signal a to the timing signal c generated from the timing generation circuit 13 at the point B. Therefore, the timing signal c is selectively output from the clock selection circuit 16, and the storage circuit 11, the PLL circuit 12
And supplied to the data fixing circuit 14. by this,
In the section C of FIG. 2, the clock is not cut off, and the data write operation to the storage circuit 11 is performed.

When the clock is restored at the point D, the output of the clock selection circuit 16 becomes the input clock signal a.

[0038]

The present invention is constructed and operates as described above. According to the present invention, the following effects can be obtained.

The first effect is that the transmission efficiency of the line can be increased.

The reason is that not only when the input data signal becomes abnormal but also when the input clock signal becomes abnormal, the alarm state can be correctly transferred to the receiving side.
In addition, the means can perform the transfer without having to prepare special bits on the radio frame.

The second effect is that the function can be realized with a minimum circuit scale.

The reason is that the alarm transfer can be performed in any case by using the timing signal originally existing in the apparatus as the clock signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment according to the present invention.

FIG. 2 is a time chart for explaining an example of the operation of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Storage circuit 12 ... PLL circuit 13 ... Timing generation circuit 14 ... Data fixing circuit 15 ... Clock cutoff detection circuit 16 ... Clock selection circuit

Claims (4)

(57) [Claims] A transmitting unit for transmitting an input signal to an opposite station;
A storage unit for converting a speed for forming a frame for a radio section in a transmission unit of a digital communication system comprising a reception unit for receiving a signal from the transmission unit; and a speed conversion unit synchronized with an input clock signal. PLL (Phase Locked Loop) that generates the subsequent clock signal
p) a circuit, a timing generation circuit for generating timing signals of various timings based on the clock signal generated by the PLL circuit, and an input signal to the storage circuit in advance based on a detection result of a clock disconnection detection circuit described later. A data fixing circuit for fixing a fixed data signal; a clock signal loss detecting circuit for detecting a signal loss of the input clock signal; and a data fixing circuit, a storage circuit, and a PLL based on a detection result of the clock loss detecting circuit. A clock selection circuit that switches a clock signal to be output to a circuit from the input clock signal to a timing signal generated by a timing generation circuit, so that an alarm can be transferred even when the input clock signal is interrupted. An alarm transfer circuit, comprising: 2. The data fixing circuit outputs an input signal to the storage circuit as it is during a normal operation. However, when the clock signal loss detection circuit detects a disconnection of the input clock signal or when the input signal disconnection is detected. 2. The alarm transfer circuit according to claim 1, further comprising fixing a data signal to be written to the storage circuit to a predetermined data signal in a case where the error occurs. 3. The storage circuit has a function of forming a frame for a radio section with respect to the input signal and converting a transmission rate in order to add various types of information. The method according to claim 1, further comprising: generating a clock signal after the speed conversion in synchronization with a clock signal, reading a data signal for a wireless section from the storage circuit by the clock signal, and outputting the data signal to a receiving side. Alarm transfer circuit. 4. The clock selection circuit comprises three NANs.
2. The alarm transfer circuit according to claim 1, further comprising a logic circuit formed by combining D circuits.