JP2603608B2 - Propagation time difference correction circuit for switched space diversity digital wireless communication. - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switched space diversity digital radio communication system in which received data propagated through a first propagation path and received data propagated through a second propagation path are combined. TECHNICAL FIELD The present invention relates to an improvement in a technique for correcting a time difference caused by a difference in a propagation path between the two.

[0002]

2. Description of the Related Art The space diversity system is a space division reception system in which one transmission system is provided with two reception systems having different propagation paths to receive a transmission wave. In general, a propagation path changes depending on weather conditions, so that a reception distortion is caused by a decrease in reception level and interference fading, and as a result, a data error occurs. Therefore, the space diversity method,
One of the two receiving systems, which has less data error, is selected and switched.

However, there is a problem just switching. The reason is that when two receiving systems having different propagation paths are switched from one to the other, the respective propagation times are different, so that a certain portion of the received waveform received by one receiving system and the other receiving This is because there is a time difference between the received waveform and the portion of the received waveform, and if switching is performed ignoring this time difference, discontinuity occurs in the output waveform at the time of the switching. In the PCM communication, such a discontinuous portion spreads to a digital signal processing unit and a digital terminal device at a subsequent stage, and causes a malfunction. Therefore, it is necessary to match the timings of the received data of the two receiving systems before switching, and therefore, a correction circuit for reducing the propagation time difference between the data of the two receiving systems to zero has been used.

Conventionally, in this kind of technique, a transmitting side inserts a synchronization pulse (for example, a frame synchronization signal) of a fixed pattern into transmission data, and the receiving side extracts the frame synchronization signal and uses this signal. Then, the propagation time difference between the demodulated digital signals is detected, whereby the delay time of the digital signal of either one of the two receiving systems is controlled to match the time of the received data of the two receiving systems (that is, the time difference is determined). To zero).

FIG. 4 is a block diagram showing a simple configuration of a switchable space diversity receiver using the prior art. The received data d ₁ of the first receiver 12 is delayed for a predetermined time by the delay unit 14 and becomes d ₁ -1 as the first received clock c.
_It is sent to the switch 19 and the time difference detector 20 together with ₁ . The received data d ₂ of the second receiver 13 is sent to the memory 15, and the received clock c ₂ is sent to the write clock generator 16 and to the read clock delay adjuster 18. Read clock delay adjuster read clock generator 17 to 18 as a delayed received clock c ₂ -1 delays the received clock c ₂ accordingly is input signal corresponding to the time difference from the time difference detector 20, the time difference detector 20 and It is sent to the switch 19.

The read clock generator 17 generates a read clock based on the delayed receive clock c ₂ -1 and reads out the received data d ₂ -1 from the memory. Therefore, the reception data d ₂ -1 is delayed from the reception data d ₂ by the delay of the read clock. Then, the received data d ₂ -1 is added to the time difference detector 20 and sent to the switch 19. The time difference detector 20 extracts a frame synchronization signal from both received data based on the received data d ₁ -1, received clock c ₁ , received data d ₂ -1 and received clock c ₂ -1 thus input. A time difference between the two received data is detected by utilizing the same, a control signal corresponding to the time difference is read out and sent to the clock delay adjuster 18 to constitute a negative feedback system, thereby automatically operating so that the time difference becomes zero.

The reason why the delay unit 14 is provided is that the reception data d ₁ of the first receiver 12 is delayed in advance in accordance with the time delay in writing and reading of the memory 15. The received data d ₁ -1 and d
₂ -1, receive clock c _1, the c ₂ -1 since being sent to the switch 19, switching is also missing or duplication of data is performed (referred to discontinuous data, including both) does not occur It turns out that.

[0008]

However, in the above-mentioned prior art, the frame synchronization signal, which is extracted and reproduced from the demodulated digital signal, is used together with the clock signal reproduced and extracted. If frequency selective fading or the like occurs in the propagation path, the demodulated digital signal contains extreme distortion and the frame phase between the extracted frame synchronization signal and the frame synchronization signal in the normal propagation path A case occurs where synchronization is not achieved. In such a case, the time difference detector 20 does not operate normally, and control for making the time difference zero cannot be performed.

Further, even if the fading is restored and the demodulated digital signal becomes normal, there is a slight time delay until the frame synchronization is restored. During that time, the time difference detector 20 cannot operate normally, so that the time difference control cannot be performed. .

In view of the above-mentioned problems of the prior art, an object of the present invention is not to detect a time difference by comparing signals having a very narrow time width with respect to a repetition period as in a synchronization pulse, but to detect a time difference between two propagation paths. First, the bit timing of the received data is matched, and the delay from one of the received data is 1
Propagation that generates multiple pieces of received data that differ by bit, and compares the difference with the other received data for each bit and, when the number of matching bits equal to or greater than the specified ratio is obtained, extracts the two received data as being in time. It is to provide a time difference correction circuit.

[0011]

The present invention has the following means in order to achieve the above object. That is, the propagation time difference correction circuit of the present invention uses the reception clock (first
A shared clock output circuit that receives a received clock) and a received clock of the second receiving system (second received clock) and outputs a shared clock by gently switching from one to the other or from the other to one by a switching signal; A first delay adjustment memory circuit for writing reception data (first reception data) of the reception system with a first reception clock and reading the reception data with the common clock; and receiving the reception data (second reception data) of the second reception system with a second reception clock. A second delay adjustment memory circuit that reads in with the shared clock; and a first shift register that delays the first reception data read from the first delay adjustment memory circuit by a predetermined number of data bits. The second received data read from the second delay adjustment memory circuit is shifted by a shift register having a greater number of stages than the first shift register. A second shift register for inputting and outputting a plurality of second received data strings having delay amounts different by one bit each; and a first received data output from the first shift register and a delay amount from the second shift register. A plurality of comparators for comparing each of the plurality of different second received data in parallel with each other; and a comparison indicating that there is a match of data bits of a predetermined number of bits or more among the plurality of comparators. A data selection synchronization holding circuit for selecting the second reception data input to the device, and thereafter holding the synchronization with the data and outputting the selected data, and a circuit for correcting the propagation time difference in the switched space diversity digital wireless communication. It is.

[0012]

The operation of the present invention in the above configuration will be described below. Since the first reception data and the second reception data have different propagation paths, there is a time difference in the reception. The time difference is due to the distance difference between the two paths, and is not necessarily an integral multiple of the data bit width. The received data is stored in the first delay adjustment memory circuit, and the second received data is stored in the second delay adjustment memory circuit at the reception clock of each reception system.
Is stored in the delay adjustment memory circuit. Each of the received data stored in this manner is sequentially read out from the previously stored one by the same clock from the common clock output circuit.

As described above, since the read clocks are the same, the time positions of the bits match between the first received data and the second received data read. As a result, the time difference between the two received data becomes an integral multiple of the bit width time. For example, if the time difference at the time of reception is 2.5 bits, it will be a 3 bit difference, and the 1.9 bit difference will be a 2 bit difference.

The first reception data, which is one of the reception data whose delay has been adjusted in this way, is delayed by a first shift register that delays by a predetermined number of bits from the distance difference of the propagation path and other conditions. 2 received data is
Input is made to a second shift register having more stages than the first shift register, and an output is taken out from each stage. Therefore, a plurality of second received data strings whose delay amount increases by one bit are extracted.

[0015] Each of the plurality of second received data thus extracted is input to a corresponding comparator, and is compared with the first received data which is the output of the first shift register. Here, if the time matches the first received data, the data contents should be the same over all bits because the data contents are originally the same. However, it is possible that there are actually a few erroneous bits,
For example, if a match of 245 bits in 250 bits of one frame is obtained, it means that the times match.

On the other hand, if there is a time difference even for one bit, the data does not match. Therefore, the second received data input to the comparator that has output the coincidence signal has the same time as the first received data. The output of each comparator and the second received data input thereto are input to the data selection synchronization holding circuit, where the comparators are checked for coincidence / mismatch, and are input to the comparators that have indicated a match. Second
Select the received data and hold its output. As described above, the second reception data whose time coincides with the first reception data can be taken out, so that even when both are switched, discontinuity such as data loss or duplication does not occur.

As described above, in the correction circuit of the present invention, the time difference between the reception data determined by the path difference between the two propagation paths is once adjusted to an integer multiple of the bit width time by the delay adjustment memory circuit, and then one of the reception data is converted. The other received data is delayed by a predetermined number of bits, and the other received data generates a large number of received data strings with delays different by one bit, and the two are compared, so that the entire received data can be used for comparison, and a fixed period As compared with a case where a synchronization pulse that appears only once is compared, a stable time correction that is less affected by fading or the like can be performed.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a switchable space diversity receiving apparatus to which an embodiment of the present invention is applied, and a portion surrounded by a dotted line is a configuration of the embodiment of the present invention.
FIG. 2 is a detailed diagram of the synchronization detection circuit 6 of FIG. 1, and FIG. 3 is a signal timing chart for explaining the operation of the synchronization detection circuit of FIG.

In FIG. 1, received data D ₁ ,
The clock CK ₁ is input to the fixed delay circuit 3a. Similarly, the reception data D ₂ and the clock CK ₂ of the receiver 2b are input to the fixed delay circuit 3b. The fixed delay circuits 3a and 3b
A delay from the receiving antenna 1a to the fixed delay circuit 3a;
It is used for adjusting the delay difference from the receiving antenna 1b to the fixed delay circuit 3b.

The received data D ₁ and the clock CK ₁ from the fixed delay circuit 3 a are supplied to the delay adjustment circuit 4 a and further to the clock C
K ₁ is also input to the common clock generation circuit 5. Also,
Received data D ₂ and the clock CK from the fixed delay circuit 3b
₂ is input to the delay adjustment circuit 4b, and the clock CK ₂ is also input to the common clock generation circuit 5.

In the delay adjusting circuits 4a and 4b, the received data D ₁ is a clock CK ₁ and the received data D ₂ is a clock C
The K ₂ are written into the memory. Reading is sequentially performed by the common clock CK, and becomes D ₁ -1 and D ₂ -1 and is output to the synchronization detection circuit 6. At this time, data having a bit number or more corresponding to the maximum delay time difference is stored in the memory, and data having the bit number or more can be stored. By doing so, D ₁
Or even if changes either phase of D _2, data loss, discontinuous duplicate such data is eliminated. This circuit is realized by a first-in first-out (FIFO) register.

[0022] In the common clock generator circuit 5, without fixing to either of the clock, the clock CK ₁ or clock CK ₂ of the receiving system towards which is selected by the switching circuit 7 is selected. However, simply switching the clock CK ₁ and the clock CK _2, there is a possibility that discontinuity occurs in the common clock CK. Therefore, when switching, it is necessary to match the phase of the other clock with that of the selected clock. Here, the non-selected clock is controlled to match the phase of the selected clock. However, when the clocks are switched, if the phases are not completely matched, jitter occurs at the time of the switching. Therefore, a PLL circuit is used to absorb the jitter.

The data D ₁ -1 and the data D ₂ -1 is have a time difference of an integral multiple of the common clock CK at a bit width time data bits because synchronization is The time difference is the Tore not is zero doing. Where the data D ₁ -1 and the data D ₂ -1 is sent together with the common clock CK to the synchronization detection circuit 6. Data D ₁ -1 data receiving is of 3 bits delayed input to the shift register 8 in advance the number-determined bits, for example 3 bits (first shift register) D
Output as _1-2 .

On the other hand, the data D ₂ -1 is stored in the shift register 8
For example, a five-stage shift register 9 (second
And the output is taken out from each stage. The output of the first stage D ₂ -2a, the output of the second stage D _2-2b, similarly to the output of the fifth stage follows the D ₂ -
Output as 2e. It can be seen that these outputs have the same data content, but the amount of delay increases by one bit in later stages. Then, the data D ₂ -2a is to comparator 10a, the data D _2-2b is to comparator 10b, the data D ₂ -2c is to the comparator 10c, similarly the data D ₂ -2e following addition to the comparator 10e Can be Data D _1-2 is simultaneously applied to each comparator.

Each comparator is an exclusive OR circuit (Exclusive O
R: EXOR), outputs logic "0" (also referred to as "L") if both inputs match, and logic "1" (also referred to as "H") if both inputs do not match. ) Is output.
Such an operation is performed for each bit of data. Therefore, data D ₁ -2 and time matches (i.e. the time difference is zero) the output of the comparator data D ₂ -2 is input will be from both data is What originally the same "L" is continuous , the data D ₂ -2 to another comparator 1
Since there will be a time difference of a bit or several bits,
The coincidence or non-coincidence of data for each bit becomes random, and "H" and "L" appear at random.

Therefore, by checking whether or not "L" appears continuously, it can be determined whether or not the times of both input data to the comparator coincide. Actually, even if the time coincides, an error bit may be generated. Therefore, taking into account this, for example, if one frame is 250 bits, if "L" appears in 245 bits, it is determined that the time coincides. Means are taken.

The output and the data D ₂ -2a~D ₂ -2e being input to their respective comparators are input to the data selection synchronization holding circuit 11, wherein observing the output of each comparator, the time matching the selected data D ₂ -2 being input to the determined comparator to maintain synchronization in this state is output as data D ₂ -3. A simple example of the above operation will be described with reference to FIG.

[0028] in FIG. 3 (1) represents a data D ₁ -1. 1
The section represents one bit, the number in each section is a data number given for convenience, and the data itself is “H” or “L”.
It is. (2) shows a case where the data D ₂ -1 is one bit ahead of the data D ₁ -1. (3)-(1
Data 0) indicates data 5 clocks after the data 1) and 2). Since the data D _1-2 of (3) is the output of the shift register 8, the output data number after 5 clocks is 3. (4) Data D ₂ -2a begins fifth clock signals bit number 6 of the data D ₂ -1 because it is the output of the first stage flip-flop of the shift register 9.

Hereinafter, the data (5), (6), (7), and (8) become signals as shown in FIG. Then it can be seen that data D ₂ -2d matches data D ₁ -2 (3) (7). Where the data D ₂ -2d (7) is output as data D ₂ -3 of being selected as the data that matches the time (10).

Thus, data D _1-2 and data D _2-
3 is sent to the switching circuit 7 and is switched from one to the other depending on the state of the propagation path of the radio wave. However, since the time of both data coincides, discontinuity such as data loss or duplication does not occur due to the switching. Will be.

[0031]

As described above, in the time difference correction circuit according to the present invention, the time difference between the two received data due to the difference in the path of the propagation path is adjusted so that the time difference becomes an integral multiple of the bit width time. The data is fixedly delayed by a predetermined number of bits, and a plurality of pieces of reception data whose delay increases by one bit from one bit delay to a delay of more bits than the predetermined number of bits of the other reception data are determined. Generated, it is configured to select the received data of the same time by comparing with the fixed delayed received data from among them, since the comparison for selection is performed by comparing the received data, The information for comparison is much more stable when comparing a synchronization pulse (for example, 1 bit out of 250 bits per frame) inserted at a fixed period. Comparison selection can fading can be advantageously performed even stable time correction than conventional in the event of a.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a switchable space diversity receiver to which an embodiment of a time difference correction circuit according to the present invention is applied.

FIG. 2 is a detailed block diagram of a synchronization detection circuit 6 of FIG.

FIG. 3 is a timing chart for explaining the operation of the synchronization detection circuit 6 of FIG. 2;

FIG. 4 is a block diagram showing a simple configuration of a switchable space diversity receiver using a conventional time difference correction technique.

[Explanation of symbols]

 1a, 1b Receiving antennas 2a, 2b Receivers 3a, 3b Fixed delay circuits 4a, 4b Delay adjustment circuits 5 Common clock generation circuits 6 Synchronization detection circuits 7 Switching circuits 8, 9 Shift registers 10a, 10b, 10c, 10d, 10e Comparators Reference Signs List 11 data selection synchronization holding circuit 12 first receiver 13 second receiver 14 delay unit 15 memory 16 write clock generator 17 read clock generator 18 read clock delay adjuster 19 switch 20 time difference detector

Claims (1)

(57) [Claims] 1. A reception clock (first reception clock) of a first reception system and a reception clock (second reception clock) of a second reception system are input, and a switching signal is used to slowly change from one to the other or from the other to one. A shared clock output circuit that switches and outputs a shared clock; a first delay adjustment memory circuit that writes received data of a first receiving system (first received data) with the first received clock and reads out the shared data with the shared clock;
The second reception data (second reception data) of the second reception system is written with the second reception clock and is read with the shared clock.
A first shift register that delays the first reception data read from the first delay adjustment memory circuit by a predetermined number of data bits;
A shift register having a greater number of stages than the first shift register, receiving as input the second received data read from the second delay adjustment memory circuit, and outputting a plurality of second received data strings having delay amounts different by one bit. A second shift register that performs parallel comparison of first received data, which is an output of the first shift register, with each of a plurality of second received data having different delay amounts from the second shift register; A plurality of comparators; and selecting the second received data input to the comparator indicating that there is a match of data bits of a predetermined number of bits or more among the plurality of comparators, and thereafter synchronizing with the second received data. A data selection synchronization holding circuit for holding and outputting;
A propagation time difference correction circuit for switched space diversity digital wireless communication, comprising: