CA1283726C - Switching arrangement with automatic data alignment over a + 3.5-bit range - Google Patents
Switching arrangement with automatic data alignment over a + 3.5-bit rangeInfo
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- CA1283726C CA1283726C CA000466319A CA466319A CA1283726C CA 1283726 C CA1283726 C CA 1283726C CA 000466319 A CA000466319 A CA 000466319A CA 466319 A CA466319 A CA 466319A CA 1283726 C CA1283726 C CA 1283726C
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Abstract
PHF. 83 584 10 ABSTRACT:
An arrangement ensuring the change-over of two channels (1, 2) through which the same digital informa-tion is conveyed with automatic data alignment over a ? 3.5 bit range comprises for each channel an array of buffer stores operating at a write rate Hi/Ni (where i = 1, 2), an oscillator operating at a rate H which provides reading of the buffer stores at the rate H/N
and being synchronized in phase-opposition with one or the other of the write rates, and a logic comparator controlling the write rates Hi/Ni, the routing of the write rates to the input of the oscillator, as well as a change-over switch for the data. In the buffer store of the channel 2 assumed to be the one whose quality degrades, the data are converted into N parallel streams at the rate H2/N and are read at the rate H/N of the oscillator. In the other, higher-quality channel 1 the write rate of the buffer store is forced to the rate H1/N-1, the read rate remaining unchanged, until there is a coincidence of N bits in the two channels; there-upon the data stream is switched, the write rate is locked at H1/N and this write rate is applied to the oscillator.
An arrangement ensuring the change-over of two channels (1, 2) through which the same digital informa-tion is conveyed with automatic data alignment over a ? 3.5 bit range comprises for each channel an array of buffer stores operating at a write rate Hi/Ni (where i = 1, 2), an oscillator operating at a rate H which provides reading of the buffer stores at the rate H/N
and being synchronized in phase-opposition with one or the other of the write rates, and a logic comparator controlling the write rates Hi/Ni, the routing of the write rates to the input of the oscillator, as well as a change-over switch for the data. In the buffer store of the channel 2 assumed to be the one whose quality degrades, the data are converted into N parallel streams at the rate H2/N and are read at the rate H/N of the oscillator. In the other, higher-quality channel 1 the write rate of the buffer store is forced to the rate H1/N-1, the read rate remaining unchanged, until there is a coincidence of N bits in the two channels; there-upon the data stream is switched, the write rate is locked at H1/N and this write rate is applied to the oscillator.
Description
1~37,',~6 PHF 83-584 l 0137563 The presen~ invention relates t.o a method ensuring the automati.c correction of the relative positions of data signals transmitted via two channels throuqh which the same digital informat-on is conveyed but with a phase difference which may amount to a few bits, said correction being followed by a switch from the lesser-quality channel to the higher-quality channel, each of s~td channels being connected to the write input of a buffer store whose read output is connected to an input of the change-over switch for the data signals, each of the said buffer stores comprising a set of registers performing a series-to-parallel conversion over Ni bits at a write rate equal to the quotient of the clock rate Hi of the corresponding channel divided by Ni, the write rates being transmitted in-phase between the said channels by means of a phase-locked loop, the read rate thus be1ng controlled by the write rate and brought out or phase with respect to the latter in order to ensure between the writing and reading operations a time interval which is sufficiently long for effecting the switching to the higher-quality channel, the write information streams of each buffer store being transmitted to a logic comparator which controls, according to the current wish from a change-over switch, the said write rates and the position of thechange-over switch for the data signals.
The invention also relates to the change-over switch means realized in accordance with this method.
Such a switch means can be used each time the same digital information is transmitted through two different channels in order to ensure an improved reliability of the transmission.
On transmission, a coupler or a separat.or routes the information to the channels. On reception, external evaluation criteria are applied to a logic circuit which determines the choice of the higher-quality channel; the problem then arising is how to effect a change-over from one channel to the other without loss of information.
This switch means is used more specifically for ;
, ~
. ~
37~6 PHF 83.584 2 0137563 t.ransmission y~ ~icrowave li.nks in diversity-reception systems, whi.ch are based on the hypothesis that the probability that two transmission channels fail simultaneously is very low. The sole auxiliary channel, ommon to _ normal channels (n usually being equal to 7), conveys the information of the channel which deqrades at a gi.ven instant. When this channel improves again, the auxiliary channel is released, so that it can again be temporarily substituted for another failing channel.
The binary information processing equipment located downstream of the change-over swltch means (for example automatic switching networks in the case of telephone transmission) synchronize themselves with the signal itself. ~ut the propagation times of the same information transmitted via two different transmission channels are not absolutely ldentical; there is a delay difference between the two data streams which depends on the atmospheric conditions and which is larger for greater information rates (from 2 Mbit/s to 140 Mbitls). This difference may be sufficient to introduce, on reception, an additional transition in the clock signal and a shift between the respective information streams transmitted _~ the two channels which may fluctuate by several bits. At the instant the change-over from one channel to the other is effected, the message is truncated and one portion is transmitted via the first channel and the other portion is transmitted ~i~ the second channel. When no precautions are taken, a discontinuity occurs in the message due to the fact that bits have been lost or added. The result is that all the material downstream has lost its synchronization. This causes the loss of a considerable number of bits.
In order to obviate these disadvantages several channel change-over swltch means have been proposed, for example the means described in European Patent Application no. 0 060 751, which comprises inter alia the buffer store associated with each channel as mentioned above and which includes two taps merging into one at the level of the _ parallel change-over switches.
In these known means, the switching of the data takes place with respect to fictive data, that is to say data whose duration is n times longer than that of the real data. This switching takes place "approximately in the middle of the integration time of the phase-locked loop~ which causes a "compromise between speed and quality" of lZ837Z6 PHF a3.s84 3 0137563 synchronization and makes the switch means specifically suitable for the bit rate.
In addition, with respect to the phase shift commands, one expects to count a difference in identity between the two fictive ~i data streams for causinq a phase shift of one clock pulse on the new channel Moreover, the counting of the differences is performed with the aid of a measuring window obtained by means of a monostable circuit which causes a time delay equal to the delay required for a phase shift of 2~/n.
The present invention has for its object to provide another method by means of which it is possible to switch from one channel to the other with a shorter delay without losing or adding rnformation over a + 3.5-bit range, and which switch occurs with respect to the real data, that is to say at the output of the buffer store, so that this store may be of a simpler structure.
For this purpose, in accordance with the invention the method is characterized in that the search operation for restoring the previous synchronism (before change-over) is effected by systematically forcing the said write rate to an increased rate equal to the quotient of the said clock rate Hi divided by Ni-1 in the buffer store of the higher-quality channel, while in the buffer store of the lesser-quality channel to be aided the said operation is continued at the normal rate Hi/Ni, until the data from the two channels coincide, which, in the absence of a transmission error, will necessarily occur after a maximum of Ni~(Ni-1) bits, the switching of the rate of the lesser-quality channel to that of the higher-quality channel corresponding to the switching of the write rate to the rate of the phase-locked loop and the switching of the data signals with respect to the real data at the read output of the said buffer stores occurring simultaneously.
Features of the invention will be more fully appreciated from the following description of an exemplary embodiment when considered in conjunction with the accompanying drawings, in which Fig. 1 is a block diagram of the change-over switch means according to an embodiment of the present invention; and Fig. 2 is a time diagram showing several signals appearing in the switch circuit according to the invention.
- 3a - 20104-7842 In the block diagram of Figure 1, two channels con-vey at a given instant the same digital information with however a phase shift which may amount to a few bits. Each channel carries a bit stream Bini, where i = 1 for one of the channels and i = 2 for the other channel.
l'Z~37~
Criteria external to the switch:ing arrangement are instru-mental in determining the higher-quality channel.
The arrangement which enables the switch from one channel to the other without 1099 of information i9 constituted by:
1) A buffer store arrangement for each of the two channels.
This arrangement comprises two registers 1 and 2 which effect a series-to-parallel conversion of Ni bits. To this end the registers 1 and 2 respectively receive the clock signal Hi of the bit stream Bini and, via a frequency divider 3, the same clock signal divided by Ni. The Ni parallel bits at the write rate Hi/Ni are transmitted to the input of a register 4, in which a parallel-to-series conversion is effected for reading the bit stream Bin via lS a change-over switch 5. The array of registers 1, 2 and 4 thus constitutes said buffer store.
The invention also relates to the change-over switch means realized in accordance with this method.
Such a switch means can be used each time the same digital information is transmitted through two different channels in order to ensure an improved reliability of the transmission.
On transmission, a coupler or a separat.or routes the information to the channels. On reception, external evaluation criteria are applied to a logic circuit which determines the choice of the higher-quality channel; the problem then arising is how to effect a change-over from one channel to the other without loss of information.
This switch means is used more specifically for ;
, ~
. ~
37~6 PHF 83.584 2 0137563 t.ransmission y~ ~icrowave li.nks in diversity-reception systems, whi.ch are based on the hypothesis that the probability that two transmission channels fail simultaneously is very low. The sole auxiliary channel, ommon to _ normal channels (n usually being equal to 7), conveys the information of the channel which deqrades at a gi.ven instant. When this channel improves again, the auxiliary channel is released, so that it can again be temporarily substituted for another failing channel.
The binary information processing equipment located downstream of the change-over swltch means (for example automatic switching networks in the case of telephone transmission) synchronize themselves with the signal itself. ~ut the propagation times of the same information transmitted via two different transmission channels are not absolutely ldentical; there is a delay difference between the two data streams which depends on the atmospheric conditions and which is larger for greater information rates (from 2 Mbit/s to 140 Mbitls). This difference may be sufficient to introduce, on reception, an additional transition in the clock signal and a shift between the respective information streams transmitted _~ the two channels which may fluctuate by several bits. At the instant the change-over from one channel to the other is effected, the message is truncated and one portion is transmitted via the first channel and the other portion is transmitted ~i~ the second channel. When no precautions are taken, a discontinuity occurs in the message due to the fact that bits have been lost or added. The result is that all the material downstream has lost its synchronization. This causes the loss of a considerable number of bits.
In order to obviate these disadvantages several channel change-over swltch means have been proposed, for example the means described in European Patent Application no. 0 060 751, which comprises inter alia the buffer store associated with each channel as mentioned above and which includes two taps merging into one at the level of the _ parallel change-over switches.
In these known means, the switching of the data takes place with respect to fictive data, that is to say data whose duration is n times longer than that of the real data. This switching takes place "approximately in the middle of the integration time of the phase-locked loop~ which causes a "compromise between speed and quality" of lZ837Z6 PHF a3.s84 3 0137563 synchronization and makes the switch means specifically suitable for the bit rate.
In addition, with respect to the phase shift commands, one expects to count a difference in identity between the two fictive ~i data streams for causinq a phase shift of one clock pulse on the new channel Moreover, the counting of the differences is performed with the aid of a measuring window obtained by means of a monostable circuit which causes a time delay equal to the delay required for a phase shift of 2~/n.
The present invention has for its object to provide another method by means of which it is possible to switch from one channel to the other with a shorter delay without losing or adding rnformation over a + 3.5-bit range, and which switch occurs with respect to the real data, that is to say at the output of the buffer store, so that this store may be of a simpler structure.
For this purpose, in accordance with the invention the method is characterized in that the search operation for restoring the previous synchronism (before change-over) is effected by systematically forcing the said write rate to an increased rate equal to the quotient of the said clock rate Hi divided by Ni-1 in the buffer store of the higher-quality channel, while in the buffer store of the lesser-quality channel to be aided the said operation is continued at the normal rate Hi/Ni, until the data from the two channels coincide, which, in the absence of a transmission error, will necessarily occur after a maximum of Ni~(Ni-1) bits, the switching of the rate of the lesser-quality channel to that of the higher-quality channel corresponding to the switching of the write rate to the rate of the phase-locked loop and the switching of the data signals with respect to the real data at the read output of the said buffer stores occurring simultaneously.
Features of the invention will be more fully appreciated from the following description of an exemplary embodiment when considered in conjunction with the accompanying drawings, in which Fig. 1 is a block diagram of the change-over switch means according to an embodiment of the present invention; and Fig. 2 is a time diagram showing several signals appearing in the switch circuit according to the invention.
- 3a - 20104-7842 In the block diagram of Figure 1, two channels con-vey at a given instant the same digital information with however a phase shift which may amount to a few bits. Each channel carries a bit stream Bini, where i = 1 for one of the channels and i = 2 for the other channel.
l'Z~37~
Criteria external to the switch:ing arrangement are instru-mental in determining the higher-quality channel.
The arrangement which enables the switch from one channel to the other without 1099 of information i9 constituted by:
1) A buffer store arrangement for each of the two channels.
This arrangement comprises two registers 1 and 2 which effect a series-to-parallel conversion of Ni bits. To this end the registers 1 and 2 respectively receive the clock signal Hi of the bit stream Bini and, via a frequency divider 3, the same clock signal divided by Ni. The Ni parallel bits at the write rate Hi/Ni are transmitted to the input of a register 4, in which a parallel-to-series conversion is effected for reading the bit stream Bin via lS a change-over switch 5. The array of registers 1, 2 and 4 thus constitutes said buffer store.
2) A phase-locked loop common to the two channels and com-prising a voltage-controlled oscillator 6 producing a clock signal H The output of oscillator 6 is connected to the 20 registers 4 and its input to a mixer 7, which in addition receives via a change-over switch 8 the clock signal Hi divided by Ni and via a frequency divider 9 the signal H
divided by N. Thus, according to the invention this pro-vides that the operation of oscillator 6 is controlled in dependence on one or the other of the write clocks and that the buffer store is read at the rate H/N.
divided by N. Thus, according to the invention this pro-vides that the operation of oscillator 6 is controlled in dependence on one or the other of the write clocks and that the buffer store is read at the rate H/N.
3) A logic comparator 10 commanding:
- the write clocks Hi/Ni which, according to the invention, can optionally be forced to Hi/(Ni-1), 30 - the change-over switch 8 for routing the clock signals to the input of the phase-locked loop by means of a signal 1 ' - the change-over switch 5 for routing the data by means of a signal S2 These commands are executed in response to the current switching request D and the written information of each buffer store transmitted to the comparator 10.
The mode of operation of the switching arrangement 3~fi P~ 83 58~ 5 13-9-1984 according to the embodiment of the present invention will be described with reference to the time diagrams shown in Fig. 2.
The Figs. 2a and 2b are the respective time diagrams relating to the channels 2 and 1 in their initial states at the instant the switching request is received;
Fig. 2c is the time diagram relating to a channel 1 after switching.
Let it be assumed that channel 2 is the channel whose quality is degraded and that a switch to the channel 1, whose quality is better, is desired.
In Fig. 2a the line A2 shows the data of the channel 2, ... a 1~ b 1~ ... h 1~ a ~ b , ... h , a1~ b1 ... h1, ... converted in the buffer store into 8 parallel data streams, (N2 = 8) at the write rate H2/8 shown at line B2. The line C2 represents the read rate H/8 (N = 8) of the voltage-controlled oscillator, which is synchronized in phase opposition with the write rate H2/8 of channel 2.
The line D2 shows the data of channel 2 which are read 20 at the rate H/8 = H2/8.
Let it be assumed that the data of channel 1, shown in line A1 of Fig. 2b, have at the write instant t a 1-bit phase lead relative to those of channel 2 and that the write rate H1/8 (N1 = 8) shown on line B1 of the same 25 Figure has a 2-bit phase lag relative to the write rate The read rate of the voltage-controlled oscilla-tor is shown on line C1, always in phase opposition relative to the rate H2/8.
Upon the request for a switch from channel 2 to a channel 1, the buffer store function is forced, at the write instant t1~ to the write rate H1/7 as shown by the dotted line in the Figure, the read rate remaining un-changed.
The write instant then shifts through one bit at each writing operation (t2, t3, ...) while transferring the 8 bits received last. In this case there is of necessi-ty one position amongst the 8 possible positions which :~Z837 'G
P~ 83 58~ 6 13-9-198~
results in coincidence of these 8 bits between the outputs of the two buffer stores.
This coincidence, which occurs when the write instant in memory 1 appears at the same bit as that for which the write instant appears in memory 2, is obtained after a shift through 3 bits for the case shown in Fig. 2.
The write rate for channel 1 is maintained at H1/7 during the whole search phase during which the data in the channel 1 evolve as follows:
lO d 1 c 1 b 1 a e 1 d 1 c 1 b f 1 e 1 d 1 c g 1 f 1 e 1 d 1 h-1 g-1 f-1 e 1 15 a h 1 g_1 -1 bo aO h 1 g-1 cO bo aO h 1 initial after a shift after a shift after a shift stage through 1 bit through 2 bits through 3 bits Moreover, it is necessary that the delay or advance of this write instant relative to the other write instant does not exceed half the size of the buffer store.
From the moment the coincidence over 8 bits is 25 acquired, the write clock signal H1/8 occupies the position represented on line ~1 of Fig. 2c. The following operations are then performed:
- switching of the data by means of the change-over switch 5;
- locking the write rate at H1/8;
30 - applying the write elock H1/8 to the voltage-controlled oscillator 6 by means of the ehange-over switeh 8.
After the switehing operation, the voltage-eontrolled oscillator slowly returns to a stable position of the read instant which is in phase opposition with the 35 write instant; this may cause some jitter. This position is shown on line C'l of Fig. 2e.
Remarks:
1. The switehing of the data takes place from the instant lZ8;~7'76 at which, for 8 bits,a coincidence between the two paths is detected. Without detracting from the general nature of the invention, a counting device may be added which does not authorize the switching of the data until a coincidence over 8 bits has been detected a predetermined number of times.
2. The phase jitter caused when the clock signals are switched can be reduced to any optional low value. Actu-ally, as the jitter does not appear until after switching of the data, it is therefore sufficient to realize a nar-row-band loop-filter for the phase-locked oscillator, which will adjust the read clock H/8 to its rest position after a sufficiently long time.
3. The theoretical alignment range is ~ 4 bits, but be-cause of the propagation time of the signals through thelogic circuits, this range is reduced to ~ 3.5 bits.
- the write clocks Hi/Ni which, according to the invention, can optionally be forced to Hi/(Ni-1), 30 - the change-over switch 8 for routing the clock signals to the input of the phase-locked loop by means of a signal 1 ' - the change-over switch 5 for routing the data by means of a signal S2 These commands are executed in response to the current switching request D and the written information of each buffer store transmitted to the comparator 10.
The mode of operation of the switching arrangement 3~fi P~ 83 58~ 5 13-9-1984 according to the embodiment of the present invention will be described with reference to the time diagrams shown in Fig. 2.
The Figs. 2a and 2b are the respective time diagrams relating to the channels 2 and 1 in their initial states at the instant the switching request is received;
Fig. 2c is the time diagram relating to a channel 1 after switching.
Let it be assumed that channel 2 is the channel whose quality is degraded and that a switch to the channel 1, whose quality is better, is desired.
In Fig. 2a the line A2 shows the data of the channel 2, ... a 1~ b 1~ ... h 1~ a ~ b , ... h , a1~ b1 ... h1, ... converted in the buffer store into 8 parallel data streams, (N2 = 8) at the write rate H2/8 shown at line B2. The line C2 represents the read rate H/8 (N = 8) of the voltage-controlled oscillator, which is synchronized in phase opposition with the write rate H2/8 of channel 2.
The line D2 shows the data of channel 2 which are read 20 at the rate H/8 = H2/8.
Let it be assumed that the data of channel 1, shown in line A1 of Fig. 2b, have at the write instant t a 1-bit phase lead relative to those of channel 2 and that the write rate H1/8 (N1 = 8) shown on line B1 of the same 25 Figure has a 2-bit phase lag relative to the write rate The read rate of the voltage-controlled oscilla-tor is shown on line C1, always in phase opposition relative to the rate H2/8.
Upon the request for a switch from channel 2 to a channel 1, the buffer store function is forced, at the write instant t1~ to the write rate H1/7 as shown by the dotted line in the Figure, the read rate remaining un-changed.
The write instant then shifts through one bit at each writing operation (t2, t3, ...) while transferring the 8 bits received last. In this case there is of necessi-ty one position amongst the 8 possible positions which :~Z837 'G
P~ 83 58~ 6 13-9-198~
results in coincidence of these 8 bits between the outputs of the two buffer stores.
This coincidence, which occurs when the write instant in memory 1 appears at the same bit as that for which the write instant appears in memory 2, is obtained after a shift through 3 bits for the case shown in Fig. 2.
The write rate for channel 1 is maintained at H1/7 during the whole search phase during which the data in the channel 1 evolve as follows:
lO d 1 c 1 b 1 a e 1 d 1 c 1 b f 1 e 1 d 1 c g 1 f 1 e 1 d 1 h-1 g-1 f-1 e 1 15 a h 1 g_1 -1 bo aO h 1 g-1 cO bo aO h 1 initial after a shift after a shift after a shift stage through 1 bit through 2 bits through 3 bits Moreover, it is necessary that the delay or advance of this write instant relative to the other write instant does not exceed half the size of the buffer store.
From the moment the coincidence over 8 bits is 25 acquired, the write clock signal H1/8 occupies the position represented on line ~1 of Fig. 2c. The following operations are then performed:
- switching of the data by means of the change-over switch 5;
- locking the write rate at H1/8;
30 - applying the write elock H1/8 to the voltage-controlled oscillator 6 by means of the ehange-over switeh 8.
After the switehing operation, the voltage-eontrolled oscillator slowly returns to a stable position of the read instant which is in phase opposition with the 35 write instant; this may cause some jitter. This position is shown on line C'l of Fig. 2e.
Remarks:
1. The switehing of the data takes place from the instant lZ8;~7'76 at which, for 8 bits,a coincidence between the two paths is detected. Without detracting from the general nature of the invention, a counting device may be added which does not authorize the switching of the data until a coincidence over 8 bits has been detected a predetermined number of times.
2. The phase jitter caused when the clock signals are switched can be reduced to any optional low value. Actu-ally, as the jitter does not appear until after switching of the data, it is therefore sufficient to realize a nar-row-band loop-filter for the phase-locked oscillator, which will adjust the read clock H/8 to its rest position after a sufficiently long time.
3. The theoretical alignment range is ~ 4 bits, but be-cause of the propagation time of the signals through thelogic circuits, this range is reduced to ~ 3.5 bits.
Claims (2)
1. A method ensuring the automatic correction of the relative positions of data signals transmitted via two channels (BIN1, BIN2) through which the same digital information is conveyed but with a phase difference which may amount to a few bits, said correction being followed by a switch from the lesser-quality channel to the higher-quality channel, each of said channels being connected to the write input of a buffer store whose read output is connected to an input of the change-over switch for the data signals, each of the said buffer stores comprising a set of regis-ters performing a series-to-parallel conversion over Ni bits at a write rate equal to the quotient of the clock rate Hi of the corres-ponding channel divided by Ni, the write rates for each of the said channels being restored to the in-phase condition by means of a phase-locked loop, the read rate thus being controlled by the write rate and brought out of phase with respect to the latter in order to ensure between the writing and the reading operations a time interval which is sufficiently long for effecting the switching to the channel having a higher quality, the write information streams of each buffer store being transmitted to a logic comparator which controls, according to the current wish from the change-over switch, the said write rates and the position of the change-over switch for the data signals, characterized in that the search operation for restoring the previous synchronism (before change-over) is effected by systematically forcing the said write rate to an increased rate equal to the quotient of the said clock rate Hi divided by Ni-1 in the buffer store of the higher-quality channel, while in the buffer store of the lesser-quality channel to be aided, the said operation is continued until the data from the two channels coin-cide, which in the absence of a transmission error will necessarily occur after a maximum of Ni*(Ni-1) bits, the switching of the rate of the lesser-quality channel to that of the higher-quality channel corresponding to the switching of the write rate to that of the phase-locked loop and the simultaneously occurring switch of the data signals on a level with the real data at the read output of the said buffer stores.
2. A change-over switch means realized in accordance with the method as claimed in Claim 1, with automatic correction of the relative position of the data signals transmitted through two channels (BIN1, BIN2) conveying the same digital information but with a phase difference that can consist of several bits, and also a switching from the lesser-quality channel to the higher-quality channel, the said switch means comprising a buffer store whose write input is connected to each of the said channels and whose read output is connected to an input of the change-over switch for the data signals, each of the said buffer stores comprising a set of registers effecting a series-to-parallel conversion over Ni bits at the write rate equal to the quotient of the clock rate Hi of the corresponding channel divided by Ni, a phase-locked loop ensuring the restoration of the in-phase condition of the write rates for each of the said channels, the read rate thus being used for the write rate and brought out of phase relative to the latter in order to ensure between the reading and the writing a time interval which is sufficiently long for effecting the switch to the higher-quality channel, a logic comparator receiving the write information streams from each buffer store and controlling, accord-ing to the wish from the change-over switch on the way, the said write rates and the position of the change-over switch for the data signals, characterized in that the said logic comparator controls the write rates at an increased rate equal to the quotient of the said clock rate Hi divided by Ni-1 in the buffer store of the higher-quality channel, and to a normal rate Hi/Ni in the buffer store of the lesser-quality channel to be aided until data coincidence occurs between the two channels, that is to say after a maximum of Ni*(Ni-1) bits in the absence of a transmission error, the switching of the rate of the lesser-quality channel to that of the higher-quality channel corresponding to the switching of the write rate to the rate of the phase-locked loop and the switching of the data signals with respect to the real data at the read output of the said buffer stores occurring simultaneously.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000466319A CA1283726C (en) | 1984-10-25 | 1984-10-25 | Switching arrangement with automatic data alignment over a + 3.5-bit range |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000466319A CA1283726C (en) | 1984-10-25 | 1984-10-25 | Switching arrangement with automatic data alignment over a + 3.5-bit range |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1283726C true CA1283726C (en) | 1991-04-30 |
Family
ID=4129001
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000466319A Expired - Lifetime CA1283726C (en) | 1984-10-25 | 1984-10-25 | Switching arrangement with automatic data alignment over a + 3.5-bit range |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1283726C (en) |
-
1984
- 1984-10-25 CA CA000466319A patent/CA1283726C/en not_active Expired - Lifetime
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