JPH06252906A - Synchronization control system - Google Patents

Abstract

PURPOSE:To prevent the complication of control operations for a synchronous data processor included in a communication network which transmits the data containing the synchronous and asynchronous data. CONSTITUTION:The node devices 2-4 are connected to a transmission line 1 where a synchronous data processor is contained in a synchronous data circuit and the data containing both synchronous and asynchronous data are transmitted. A synchronous data processing part 7 excludes the control data out of a transmission frame by means of an elastic memory to transmit the transmission frame sent from the line 1 to the synchronous data circuit. Then the part 7 converters only the information part of a cell into the formats which are closed forward and continuous. Thus the synchronous data processor can easily specify the positions of cells and channels and can facilitate its control operations. Furthermore a warning signal is produced before the write/read phase difference affects the elastic memory. So that the jitters and the phase difference caused between the node independent synchronous clocks and the network synchronous clocks can be absorbed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous control system,
In particular, in a transmission system such as an independent synchronous multimedia LAN in which synchronous data and asynchronous data are mixed, it is used for accommodating the synchronous data in the transmission system and for delivering the data to the network synchronous clock operation unit. The present invention relates to a suitable synchronization control method.

[0002]

2. Description of the Related Art Generally, in a node device for transmission processing in which synchronous data and asynchronous data are mixed, such as in a multimedia LAN, when synchronous data is network-synchronized and accommodated in a communication network, switching of operation clocks is realized. The elastic memory is used only for the purpose.

However, when changing the operation clock, when the clock is changed while the frame format circulating in the transmission path is preserved and the data is transmitted to the synchronous data processing device, the synchronous data processing device is synchronized. In order to retrieve or transfer data, it is necessary to perform complicated control in consideration of an invalid area inserted in a frame.

In order to avoid the need for such complicated control, it is easy to perform control as synchronous data processing by eliminating the invalid area of the frame format circulating in the transmission line at the time of changing the operation clock. It is necessary to convert to a different frame format.

In order to change the operating clock,
When the elastic memory is inserted, overflow or underflow of the elastic memory occurs due to the jitter of the clock and the phase shift.

[0006] As a conventional technique relating to the synchronous control for detecting the overflow or underflow of the elastic memory and changing the clocks,
For example, the technique described in JP-A-62-86933 is known.

This prior art is to detect the overflow and underflow of the elastic memory caused by the jitter of the clock and the phase shift by comparing the phase of the write frame with the phase of the read frame.

However, according to this conventional technique, even when the phase of the write frame and the phase of the read frame suddenly come close to each other due to a hardware failure, the phase between the operation clock on the writing side and the operation clock on the reading side is changed. A hardware failure cannot be detected by determining that overflow or underflow has occurred due to the shift or the jitter.

[0009]

As described above, in a node device of a transmission system such as an independent synchronous multimedia LAN, a frame in which a frame format circulating in a transmission path is retained is network-synchronized to obtain synchronization data. In the conventional technique of transmitting to the processing device, the synchronous data processing device must perform control in consideration of invalid data inserted in the middle of the frame, and must perform complicated control such as extraction of synchronous data and transmission control. It has the problem of not becoming.

Further, in the above-mentioned conventional technique for detecting an overflow or underflow failure of the elastic memory from the phase difference between the write frame and the read frame, when an abnormality is detected, the phase between the write frame and the read frame is initialized. Data transmission / reception is restarted after correction to the time phase, but if hardware malfunctions or failures cause overflow or underflow, data transmission / reception is restarted in the same manner as described above, and in some cases restarted / recovered. There is a problem that the transmission system is repeatedly brought into an unstable state.

An object of the present invention is to solve the above-mentioned problems of the prior art and not to complicate the control operation in a synchronous data processing device accommodated in a communication network in which synchronous data and asynchronous data are mixed. Further, in the node device in the transmission system, when overflow or underflow of the elastic memory is detected, it is detected that the phase shift between the operation clock on the writing side and the operation clock on the reading side, jitter, that is, It is an object of the present invention to provide a synchronization control method capable of easily discriminating between a defective reproduction of a network synchronization clock and a hardware failure of elastic memory control.

[0012]

According to the present invention, the above object is to limit the data to be written in the elastic memory only to the cell information part and to continuously read the data from the frame head signal so that only the cell information part is read. By converting the order of the cells arranged in a concentrated sequence into a saved format and transmitting it to the synchronous data processing device, the elastic memory overflow and underflow warnings can be generated from the phase difference between the write frame and the read frame. ,
This is achieved by allowing the overflow and underflow to occur before they become obstacles.

[0013]

[Function] The data to be written to the elastic memory is limited to the information part of the cell, and the invalid area randomly inserted,
By deleting the cell control information part unnecessary for the synchronous data processing, the synchronous data processing device can easily specify the cell position and the channel position, retrieve the data,
Also, the transmission control can be simply realized.

Further, the warning of overflow or underflow of the elastic memory is generated before the trouble of overflow or underflow occurs, so that the warning is issued when the occurrence of the trouble of overflow or underflow is detected. It is possible to easily determine whether the failure occurs due to the phase shift of the clock or the jitter, the hardware failure, or the malfunction by checking whether or not the error occurred.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a synchronization control system according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a structure of an independent synchronous multimedia LAN according to an embodiment of the present invention, FIG. 2 is a block diagram showing a structure of a synchronous data processing unit, and FIG. 3 is a frame conversion in the synchronous data processing unit. Figure explaining the example of
FIG. 4 is a diagram for explaining a method of detecting elastic memory overflow and underflow. 1 and 2, 1 is a transmission line, 2 to 4 are node devices, 6 is a transmission line access control unit, 7 is a synchronous data processing unit, 701 and 71.
3 is a write control unit, 702 and 703 are data width conversion units,
704 and 710 are read control units, 705 is an elastic memory management unit, 706 and 707 are receiving elastic memories, 708 and 709 are transmitting elastic memories,
Reference numeral 711 is a read data retiming unit, and 712 is a data latch.

In a multimedia LAN according to an embodiment of the present invention shown in FIG. 1, node devices 2 to 4 are connected in a ring shape by a transmission line 1 for transmitting data in which synchronous data and asynchronous data are mixed, and The node devices 2 to 4 are configured by accommodating a synchronous data processing device (not shown) via a synchronous data line. Each of the node devices 2 to 4 has a transmission line access control unit 6 that controls the transmission line 1 that constitutes the communication network, and a synchronization that controls a synchronous data line to which a synchronous data processing device (not shown) is connected. The interface unit 8 and the synchronous data processing unit 7 that performs the process of synchronization between the transmission line 1 and the synchronous data line are configured.

In the illustrated embodiment, the node device 2 operates as a clock master node. Therefore, in addition to the data transmission unit, the reception unit, and the relay control unit, the node device 2 is configured to include a clock information generation unit. ing. Node device 2
Inserts the operation clock of its own node device 2 as the basic clock of the network synchronization clock into the control information area of the transmission frame and transmits it to the transmission line 1.

The node devices 3 and 4 receive the transmission frame including the basic clock at each node device with an independent internal clock and perform relaying. During this relay, the node devices 3, 4
Adjusts the clock difference between the clock master node and each node by inserting / deleting stuffing data in the transmission frame.

Each of the node devices 3 and 4 is configured to include a network synchronization clock reproduction unit for reproducing the network synchronization clock from the clock information in the transmission frame and supplying it to the synchronization data processing unit 7. In the nodes 3 and 4, the operation clock of the transmission path access control unit 6 is an internal clock independent for each node device, and in order to pass data to the synchronous interface unit 8 which operates with the regenerated network synchronous clock,
It is necessary to change the operation clock from the internal clock to the network synchronization clock, and this operation clock is changed in the synchronous data processing unit 7.

The synchronous data processing unit 7 is constituted by including elastic memories for transmission and reception, and its detailed constitution is shown in FIG.

As shown in FIG. 2, the synchronous data processing unit 7
Is a pair of elastic memories 706 to 709 for reception and transmission, data width conversion units 702 and 703 for reception and transmission data, and a write control unit 70 for controlling writing and reading to and from the elastic memory.
1, 713, read control units 704 and 710, and a data latch 7 for temporarily storing data from the synchronous data line.
12, a read data retiming unit 711 that adjusts the output timing of data to the synchronous data line, and an elastic memory management unit 705.

FIG. 3 shows a frame format (hereinafter referred to as a transmission frame) received by the synchronous data processing unit 7 from the transmission path access control unit 6, and the synchronous data processing unit 7.
The structure of a frame format (hereinafter referred to as a network synchronization frame) transmitted from the communication interface unit 8 to the synchronization interface unit 8 is shown, and these frame formats will be described below.

In the transmission frame, 44 cells are arranged in one frame, each cell consisting of a header portion (control information portion) of 5 bytes and a data portion of 48 bytes, which are synchronized with the internal clock (19.44 MHz) of the node device. , Stuffing data is inserted at unspecified positions between these cells. However, if the stuffing data is inserted at an unspecified position in this way, the processing in the synchronous data processing device connected to the synchronous data line, which is premised on the periodic arrival of the data, becomes complicated.

Therefore, in the embodiment of the present invention, the synchronous data processing unit 7 uses the elastic memory to change the clocks and remove the stuffing data.

The process of changing the clock and removing the stuffing data in the synchronous data processing unit 7 when receiving the transmission frame will be described below.

In the transmission frame received from the transmission access control unit 6 in FIG. 2, only the data in the cell is converted by the data width conversion unit 702 into 2-byte width data, which is created as write data. Then, the data of the first transmission frame received is the reception elastic memory 706 initialized under the control of the write control unit 701.
The data is written in (ES0) sequentially from the beginning of the transmission frame in synchronization with the internal clock. Therefore, in the elastic memory 706, only the data portion from the 0th address is written for 44 cells from the first cell.

The shape of the transmission frame for one frame is checked, and if there is no abnormality in the frame format,
The data part of the second transmission frame is written in the reception elastic memory 707 (ES1) in the same manner as described above. At the same time when the writing of the data of the second transmission frame is started, under the control of the read controller 710, the data reading from the reception ES0 is started in synchronization with the network synchronization clock (9.72 MHz). After the reading of the data for the cells is completed, the invalid area is inserted and the length of the network synchronization frame is adjusted.

Therefore, as shown in FIG. 3, the frame format of the network synchronization frame is composed of a data portion of 44 cells and an invalid area, which are arranged from the beginning of the frame to the beginning. There is a frame delay.

On the other hand, when the transmission data is given from the synchronous data line to the synchronous data processing unit 7 via the synchronous interface unit 8, the synchronous interface unit 8 determines the position of the cell and channel to be replaced according to the timing of the network synchronization frame. Then, the transmission data is transmitted to the synchronous data processing unit 7. Under the control of the write control unit 713, the synchronous data processing unit 7 writes the received data in the transmission elastic memory 708 (ES0) in synchronization with the network synchronization clock. After writing one frame of the network synchronization frame, the data of the next frame is similarly written to the transmission elastic memory 709 (ES1).

Simultaneously with the start of writing to the transmission ES1, the reading of data from the transmission ES0 in synchronization with the internal clock is started under the control of the read controller 704. The read data is sent to the transmission path access control unit 6 with a 1-byte width via the data width conversion unit 703.

Writing and reading to / from the elastic memories for reception and transmission of the two surfaces described above are repeatedly executed by alternately using the memories of the two surfaces. As a result, the clock phase difference between the internal clock and the network synchronization clock can be absorbed and data can be transmitted and received.

Next, a method for detecting overflow / underflow of the elastic memory will be described with reference to FIG. The overflow / underflow is detected by the elastic memory management unit 705 of the synchronous data processing unit 7 by the reception elastic memory 706,
This is performed by comparing the write / read timings of 707.

The elastic memory management unit 705 has 2
The signals indicating the first and second cells of the transmission frame to be written in the reception ES0 by switching the reception elastic memories 706 and 707 of the surface in frame units are set as the failure area A signal,
A signal indicating the first to seventh cells is generated as the warning area A signal. Further, the elastic memory management unit 705 generates a signal indicating the first and second cells of the network synchronization frame read from the reception ES0 as a failure area B signal and a signal indicating the first to seventh cells as a warning area B signal. To do.

During normal operation, as shown in FIG. 4 (1), the failure area A signal and the warning area A signal do not overlap with the failure area B signal and the warning area B signal.

Due to the phase shift between the node clock, that is, the internal clock and the network synchronization clock, and the jitter, the phases of the transmission frame and the network synchronization frame come close to each other. As shown in FIG. When the B signal overlaps, the elastic memory management unit 705 outputs a warning signal as a warning before the underflow of the elastic memory occurs. Similarly, when the failure area A signal and the warning area B signal overlap, the elastic memory management unit 705 outputs a warning signal as a warning before the elastic memory overflows.

When the phase of the transmission frame and the phase of the network synchronization frame further approach each other and the fault area A signal and the fault area B signal overlap with each other as shown in FIG. 4C, the elastic memory management unit 705 causes the elastic memory management unit 705. When the occurrence of memory overflow or underflow failure is detected, the synchronization data processing unit 7 is reinitialized, and the phase between the transmission frame and the network synchronization frame is returned to the phase difference of one frame as in the initial state. Resume reading data.

As described above, according to one embodiment of the present invention, the warning about the occurrence of overflow or underflow of the elastic memory is issued by the phase difference between the transmission frame and the network synchronization frame, that is, the writing and reading of the elastic memory. It is reported when the phase difference between and is within 7 cells, and the occurrence of overflow and underflow failures is reported when the phase difference is within 2 cells.

Therefore, according to one embodiment of the present invention, when the elastic memory overflow or underflow is detected, whether or not the warning signal is output is monitored before the elastic memory overflow or underflow is detected.
The cause of the underflow is determined as to whether it is caused by jitter, poor reproduction of the network synchronization clock, that is, failure of the network synchronization clock recovery section of the transmission path access control section or failure of the synchronous data processing section 7. It can be done easily.

That is, when the cause is jitter or defective reproduction of the network synchronization clock, the phase of the transmission frame and the network synchronization frame are continuously deviated, resulting in overflow,
When underflow is detected, the warning signal should always be output before that. Therefore, when the warning signal is detected, it can be understood that the causes are jitter and poor reproduction of the network synchronization clock.

On the other hand, the cause is the synchronous data processing unit 7,
That is, in the case of a failure of the control line of the elastic memory, the write / read address for the elastic memory suddenly shifts, resulting in an overflow,
No warning signal is output before the underflow is detected. Therefore, when the warning signal is not detected, it is understood that the cause is the failure of the synchronous data processing unit 7.

As a result, according to the embodiment of the present invention, it is possible to easily discriminate between the failure of the transmission line access control section and the failure of the synchronous data processing section. By separating the synchronous data processing unit, the influence on the transmission path can be avoided.

According to the above-described embodiment of the present invention, since the network information frame is constructed by centrally arranging 44 cell information parts from the head thereof, the synchronous data processing device connected to the node device. In processing this frame, the cell position and the channel position can be easily specified, and the data is taken out by the synchronization adapter device.
Transmission control can be easily executed.

Further, according to the above-described embodiment of the present invention, the node device compares the write phase and the read phase with respect to the elastic memory to generate the warning information before the failure of the elastic memory. Therefore, whether the memory failure occurred due to the phase shift between the write clock and the read clock, or
It is possible to identify whether the error occurred due to a hardware failure and perform subsequent processing.

[0045]

As described above, according to the present invention, the control operation in the synchronous data processing device accommodated in the communication network in which the synchronous data and the asynchronous data are mixed is not complicated, and the communication network is not provided. When the overflow or underflow of the elastic memory is detected in the node device inside, it is due to the phase shift between the operation clock on the write side and the operation clock on the read side, jitter, or the hardware It is possible to easily distinguish whether it is due to an obstacle.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an independent synchronous multimedia LAN according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a synchronous data processing unit.

FIG. 3 is a diagram illustrating an example of frame conversion in a synchronous data processing unit.

FIG. 4 is a diagram illustrating a method of detecting elastic memory overflow and underflow.

[Explanation of symbols]

 1 Transmission Line 2-4 Node Device 6 Transmission Line Access Control Unit 7 Synchronous Data Processing Unit 701, 713 Write Control Unit 702, 703 Data Width Conversion Unit 704, 710 Read Control Unit 705 Elastic Memory Management Unit 706, 707 Reception Elastic Memory 708, 709 Transmission elastic memory 711 Read data retiming unit 712 Data latch

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical display location H04L 12/42 (72) Inventor Koji Wada 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Ltd. (72) Inventor Yuko Motoki, 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Ltd.

Claims (2)

[Claims] 1. A plurality of node devices accommodating a synchronous data processing device, and a transmission path connecting these in a ring shape, each node device operating by an independent synchronous clock, and synchronous data and asynchronous data. In an independent synchronous transmission system that performs communication using transmission frames in which information units called cells are mixed, the node device is operated by an independent synchronous clock to accommodate synchronous data synchronized with a network synchronous clock. Equipped with an elastic memory between the part that operates with the network synchronization clock and the network synchronization clock to prevent data loss due to jitter and phase shift between the independent synchronization period clock and the network synchronization clock, and to control the cell control information part. Pass the frame that has been deleted and converted to a format in which only the information part is continuously arranged in advance to the synchronous data processing device A synchronous control method characterized in that 2. Signs of overflow and underflow of the elastic memory due to jitter and phase shift between the independent synchronous clock and the network synchronous clock are detected by phase comparison between a write frame and a read frame for the elastic memory, 2. The synchronous control system according to claim 1, wherein a failure of the stick memory control circuit and a defective reproduction of the network synchronous clock are separated from each other.