JPH0879214A - Switching method without interruption - Google Patents

Abstract

PURPOSE: To provide a switching method without interruption capable of preventing the scale increase of a hardware by arithmetic operations and adjusting the frame phase difference of an active system and a standby system. CONSTITUTION: For an RAC for which write is performed in an order from the same memory address at the same time to the memory circuits of both active system and standby system or the write is performed to the different memory addresses at the same time and adjustment is performed, in the case of advancing for α, the adjustment is performed by loading the value of the memory address 5 of the standby system read by a read address counter when the memory address of the active system or the standby system read by the read address counter is '0'. In the case of delaying for α, the adjustment is performed by loading the value of the memory address '0' of the standby system read by the read address counter when the memory address of the active system or the standby system read by the read address counter is α.

Description

Detailed Description of the Invention

[0001]

The present invention relates to SDH (Synchronus D
The present invention relates to a transmission path switching device of a transmission system.

[0002]

2. Description of the Related Art In order to ensure the reliability of communication, in a conventional transmission system, one spare system is prepared for one or N systems on the same route, and when a failure occurs in an active system or maintenance and operation purposes. If the transmission line is disconnected due to, a redundant system configuration is adopted in which the system is manually or automatically switched to the standby system. However, at the time of actual switching from the active system to the standby system, notification of failure information from the receiving side to the transmitting side, checking of the spare system availability and normal operating status, switching operation, synchronization recovery operation, and switching back Data is lost due to this momentary interruption because a complicated process is required and the signal is interrupted during the recovery time from failure to normal operation due to each protection time. As the transmission rate increases, the amount of lost data also increases in proportion.

A transmission line switching method that solves the above-mentioned problems by switching without interruption has already been proposed (Japanese Patent Application No. 6-165573 “Transmission line switching device proposed by the inventors of the present application). "reference). FIG. 3 shows the transmission path switching means according to this prior application. In order to perform switching without interruption, it is possible to match the phases of the active system and the standby system and perform switching within 1 bit. However, the frame phases of the two incoming input signals do not always pass through the same transmission path and the same path. Therefore, a time difference, that is, a phase difference occurs between the two input signals arriving at the transmission path switching device on the receiving side.

In the above-mentioned transmission path switching method, the frame phases are matched by synchronizing the multi-frame phase of the active system and the standby system with the J1 byte. FIG. 4 shows the structure of the VC-3 frame stored in the STM0 frame. J1 byte is ITU (International Telecommunication Union)
-TG. STM (Synchronous) conforming to the synchronous digital hierarchy recommended in 707, 708, and 709.
POH (Path Over He) in Transport Module frame
It exists at the beginning of ad). In the method according to the above-mentioned prior application, this byte repeatedly transmits a fixed pattern signal having a multi-frame structure in order to confirm VC (Vertual Container) path continuity. Therefore, if the J1 bytes of both systems are synchronized, the heads of the multiframes can be aligned. For example, the J1 byte has a 64 multi-frame structure, and peculiar data is inserted in the 63rd and 64th frames in advance. Therefore, by detecting this, it is possible to obtain the delay time difference due to passage of different routes, that is, the phase difference between the 0-system and the 1-system. For example, in the case of the 64 multi-frame structure, one frame is 125 μs, so that even a phase difference of 8 ms can be absorbed.

When adjusting the frame phase, it is possible to obtain the effect of adding a delay by adjusting the timing of writing once to the memory and then reading. For that purpose, an elastic store memory capable of independently performing the write operation and the read operation is required. FIG. 5 shows the structure of the elastic store memory. f _i represents the write clock and f ₀ represents the read clock. MEM is a memory circuit, DAT
A-IN is data input, DATA-OUT is data output, WAC is write address counter (Write Addr
ess Counter), RAC is read address counter
(Read Address Counter, hereinafter referred to as RAC).
Delay indicates the delay. ITU-TG. 707, 708,
In the SDH transmission method compliant with 709, the head of the VC path is AU-PTR (Admi (Admi) in the STM-0 frame shown in FIG.
nistrative unit pointer). H1 and H2 bytes present in the nistrative unit pointer). Since the elastic store memory is generally used to transfer the input signal coming from the transmission line to the internal clock, even in the synchronous network, the clock speed average values of f _i and f ₀ are usually equal, but they are mutually equal. The phase of changes with time. However, in general, a signal that has been once terminated and transferred to the in-station clock has already been terminated with a pointer that indicates the beginning of the VC path, so that f _i = f ₀ and the signal is synchronized with the in-station clock. ing. A write address counter (hereinafter referred to as WAC) counts each time writing is performed,
The control can be performed independently of the RAC. Conversely, R
AC counts each time it reads, and its control is WA
It can be done independently of C. Here, the 0-system WAC is expressed as "WAC0", and if the memory address to be pointed is address 0, it is expressed as "= 0". Hereinafter, the same applies to RAC. However, when the 0/1 system memory addresses are written to the same memory address at the same time, it can be realized by one WAC, and is therefore expressed as “WAC”.

[0006]

When absorbing the phase difference between two inputs in the elastic store memory, it is necessary to adjust the RAC of the phase matching system to match the read phases of both systems. However, in order to adjust the RAC of the system in which the phase difference between the 0-system and the 1-system is detected and the phases are matched, it is necessary to add or subtract the value of the phase difference to the current RAC value for adjustment. For that purpose, processing must be performed by an arithmetic circuit including an adder. Moreover, when performing the operation, the overflow and underflow of the operation result must be taken into consideration at the same time, which further increases the circuit scale.

FIG. 6 shows a conventional example in which the calculation result is considered.
For example, the adjustment of the phase difference is performed by the memory circuit. Therefore, if the memory amount is 12240 bytes (16 frames in the VC-3 pass), if the address display is in byte units, the RAC indicating the data stored therein is displayed. Value of 0 to 1
There are up to 2239. Considering that the phase difference changes, J1 # 1 which is the head of the VC path is not always stored from RAC = 0. Therefore, J
The data of 1 # 1 is stored.

The left side of FIG. 6 shows a conventional example in which overflow is taken into consideration. Assuming that the data of J1 # 1 of system 1 is read from RAC = 12000, the relative delay with respect to the switching source is 500 μs, and in terms of bytes. If it is delayed by 3060 bytes, RAC = 150 at 12000 + 3060
3 if read from RAC = 12000 at 60
This means that a delay of 060 bytes, that is, 500 μs is added. However, since the actual value of RAC is only 12239, if 12240 is subtracted from 15060 to read from RAC = 12000 when RAC = 2820, a delay of 500 μs is added. That is, it is necessary to consider overflow.

Further, the right side of FIG. 6 shows a conventional example in which underflow is taken into consideration. If the data of JI # 1 of system 1 is read from RAC = 2820, the relative delay with respect to system 0 is 500 μs, byte If it is advanced by 3060 bytes in terms of conversion, reading from RAC = 2820 when RAC = −240 in 2820-3060 adds 3060 bytes, that is, a delay of 500 μs.
However, there is no minus address in the actual address. Therefore, if 240 is subtracted from 12240 and RAC = 2820 is read when RAC = 12000, a delay of 500 μs is added. That is, it is necessary to consider underflow.

Therefore, since the object of the present invention is to calculate the delay amount by calculation, the calculation circuit itself, its peripheral circuits necessary for considering overflow or underflow, and the calculation algorithm are necessary. An object of the present invention is to provide a non-instantaneous interruption switching method capable of adjusting the frame phase difference between the active system and the standby system by solving the problem that the scale of the wear becomes large.

[0011]

The present invention provides an ITU-T
G. 707, 708, and 709, which are compatible with the synchronous digital hierarchy recommended, and which receive signals arriving from two transmission paths including different paths, including a delay means including a memory circuit including an elastic store memory, , In the non-interruptive switching method that switches without loss of bits, the system that can match the frame phase is the current system and the remaining 1
One is the spare system that matches the frame phase to the working system, and RA
Assuming that the difference between the memory addresses storing the frame synchronization patterns of both systems read by C is the phase difference α between the active system and the standby system, the memory circuits of both the active system and the standby system sequentially start from the same memory address at the same time. When it is desired to advance α with respect to the RAC to be written and adjusted, when the memory address of the active system or the standby system read by the RAC is 0, the value of the memory address α of the standby system read by the RAC is set. If you want to delay by loading α, and if you want to delay α, when the active or standby system memory address read by the RAC is α, load the value of the standby system memory address 0 read by the RAC and make the adjustment. It is characterized by

In the non-instantaneous-interruption switching system, if the system in which the frame phase can be adjusted is the active system and the other one is the standby system in which the frame phase is adjusted to the active system, the memory circuits of the active system and the standby system are respectively At the same time, write to different memory addresses and
When it is desired to proceed, when the memory address of the standby system read by the RAC is 0, the value of the memory address α of the standby system read by the RAC is loaded and adjusted, and when delayed by α, the value is read by the RAC. When the memory address of the spare system is α, the value of the memory address 0 of the spare system read by the RAC is loaded and adjustment is performed.

[0013]

In the frame phase difference adjusting method of the present invention, the RAC
Since the addition or subtraction is not performed using the arithmetic circuit when adjusting, the arithmetic circuit itself and its peripheral circuits and calculation algorithms necessary for considering the overflow or underflow are not required, so the hardware scale can be reduced. It can be reduced.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings with a system capable of phase matching as a current system and a system capable of phase matching as a spare system. Example 1 corresponding to claim 1 of the present invention is shown and described in FIG. 1 and Table 1.

[0015]

[Table 1]

FIG. 1 and Table 1 show an example in which the active system 0 is ahead of the standby system 1 by 4 bytes in the memory. By writing the 0-system and 1-system memory addresses in order from the same memory address, the memory address of the WAC at the same time is the same. That is, as shown in Table 1, "address 0/1" in the table indicates the memory address of both systems, and "data 0" or "data 1" indicates when the WAC or RAC0 / 1 indicates each memory address. Data examples are shown. For example, it means that the 0-system data indicates "M" when the 0-system RAC reads the memory address "E" at a certain time.
Therefore, the phase difference is detected, for example, when the 0-system RAC whose phase is advanced by using the counter circuit reads the memory address “2” at which the frame synchronization pattern is detected, that is, RAC0 = 2 to 1 byte. When the RAC of the 1st system, which has a delayed phase, reads the memory address “6” at which the frame synchronization pattern is detected, that is, when RAC1 = 6, the phase difference α
Can be requested.

According to the contents described above, when the delayed spare system is matched with the working system, RAC1 of the spare system needs to be advanced by the phase difference α. Therefore, when RAC0 = 0, RA
If C1 = 4 (α value) is loaded, the phase of the standby system can be matched with the active system. Further, when the phase is adjusted by the spare system itself, similarly, the spare system RAC1
Since it is only necessary to advance the phase difference by α, it is possible to match the phase of the standby system with the active system by loading RAC1 = 4 (α value) when RAC1 = 0. Therefore, when the memory address of the active system or the spare system read by the RAC is 0, the phase of the signal read from the memory can be matched by loading the value of the memory address α of the spare system read by the RAC. is there.

A second embodiment corresponding to claim 2 of the present invention will be shown and described in FIG. 2 and Table 2. 2 and Table 2 show an example in which the active system is delayed by 4 bytes from the standby system in the memory.

[0019]

[Table 2]

In the following, when the backup system, which is proceeding similarly to the first embodiment, is matched with the active system, it is sufficient to delay RAC0 by the phase difference α, so that it is already written when RAC1 = 4 (α value). The phase can be matched by loading the data of RAC0 = 0. Further, when the phase is adjusted by the spare system itself, similarly, the spare system RAC0
RAC0 = 4 (α
If the data of RAC0 = 0 already written at the time of (value) is loaded, the phases can be matched. Therefore, when the memory address of the active system or the standby system read by the RAC is α, it is possible to match the phase of the signal read from the memory by loading the value of the memory address 0 of the standby system read by the RAC. is there.

Table 3 shows a third embodiment corresponding to claim 3 of the present invention.

[0022]

[Table 3]

Table 3 shows an example in which the active system is ahead of the standby system by 4 bytes on the memory. In the first and second embodiments, an example is shown in which writing is sequentially performed from the same memory address at the same time to the memory circuits of the active system and the standby system. An example will be described in which the phase adjustment can be performed even when writing is sequentially performed to the memory circuit from different memory addresses at the same time. The phase difference can be detected in the same manner as in the first and second embodiments by using the counter circuit to detect RAC0 = 2 and then count by 1 byte, and when RAC1 = 6 is detected, the phase can be stopped and the phase difference α can be obtained. . next,
As shown in the first and second embodiments, the phase difference can be adjusted by the means for adjusting the phase by the auxiliary system itself. That is, when the delayed backup system is matched with the working system, RAC1 may be advanced by the phase difference α.
The phases can be matched by loading a memory address of RAC1 = 4 (α value) when C1 = 0.

Table 4 shows and describes Example 4 corresponding to claim 4 of the present invention.

[0025]

[Table 4]

Table 4 shows an example in which the active system is delayed by 4 bytes from the standby system in the memory. As in the case of the third embodiment, when the advancing spare system is matched with the active system, it is sufficient to delay the spare system RAC0 by the phase difference α. Therefore, when the spare system RAC0 = 4 (α value), it is already written. The phase can be matched by loading the memory address of the spare system RAC0 = 0. As described above, even when writing to the active memory circuit and the standby memory circuit sequentially from different memory addresses at the same time, if it is desired to advance α to the RAC to be adjusted, RAC
When = 0, the data of RAC = α of the spare system is loaded and adjusted, and when it is desired to delay α, the RAC of the spare system = α
At this time, the data of RAC = 0 of the spare system is loaded and adjusted, so that the phase can be matched by performing the adjustment by the spare system itself.

[0027]

As described above, according to the present invention, it is possible to match the phases of both systems without directly performing calculation. Therefore, the arithmetic circuit itself, its peripheral circuits necessary for considering overflow or underflow, and the calculation algorithm are unnecessary, and the hardware scale can be reduced accordingly.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment corresponding to claim 1.

FIG. 2 is a diagram showing a second embodiment corresponding to claim 2;

FIG. 3 is a block diagram of a transmission path switching means according to the prior application.

FIG. 4 is a diagram showing a frame structure of STM0 and VC-3 according to CCITT recommendation.

FIG. 5 is a diagram showing a configuration example of an elastic store memory.

FIG. 6 is a diagram showing an example in which overflow or underflow is considered.

[Explanation of symbols]

RAC read address counter WAC write address counter f _i write clock f ₀ read clock MEM memory circuit DATA-IN data input DATA-OUT Data output

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshiaki Yamabayashi 1-1-6 Uchisaiwai-cho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation (72) Inventor Tadanobu Nikaido 1-1-14 Kichijojihonmachi, Musashino-shi, Tokyo No. 5 NTT Electronics Technology Co., Ltd. (72) Inventor Motoharu Ikeda 1-14-5 Kichijojihonmachi, Musashino-shi, Tokyo NTT Electronics Electronics Co., Ltd.

Claims (4)

[Claims] 1. ITU-T G.I. 707, 708, 70
Compliant with the Synchronous Digital Hierarchy recommended in No. 9, and is composed of a memory circuit including first and second elastic store memories for respectively receiving frame signals transmitted by two transmission paths including different paths. In a hitless switching method for switching between first and second receiving means including a delay means without loss of bits, one of the first receiving means and the second receiving means is currently operated. The active system that is being used, and the remaining one is a standby system for adjusting the frame phase to the active system, and the memory circuits of the active system and the standby system are sequentially ordered from the same memory address at the same time. The frame synchronization pattern of the active system read by the read address counter when writing is performed and the frame phase of the active system is ahead of the standby system. And a memory address for storing the frame synchronization pattern of the spare system, and the difference between the memory addresses is defined as the phase difference α, the active system or the spare system read by the read address counter. When the memory address of the system is 0, the frame phase of the signal read from the memory is matched by loading the value of the memory address α of the spare system read by the read address counter. Instantaneous interruption switching method. 2. The ITU-T G.I. 707, 708, 70
Compliant with the Synchronous Digital Hierarchy recommended in No. 9, and is composed of a memory circuit including first and second elastic store memories for respectively receiving frame signals transmitted by two transmission paths including different paths. In a hitless switching method for switching between first and second receiving means including delay means without loss of bits, one of the first receiving means and the second receiving means is set to a frame phase. The active system to be matched and the other one are used as a standby system for adjusting the frame phase to the active system, and are sequentially written to the memory circuits of the active system and the standby system from the same memory address at the same time. And a frame phase of the active system is read by a read address counter when the frame phase of the active system is behind that of the standby system. When a memory address for storing a turn and a memory address for storing the frame synchronization pattern of the spare system are acquired and the memory address difference is set as a phase difference α, the working system or the read system read by the read address counter is used. When the memory address of the spare system is α, the frame phase of the signal read from the memory is adjusted by loading the value of the memory address 0 of the spare system read by the read address counter. Switch without interruption. 3. The ITU-T G.I. 707, 708, 70
Compliant with the Synchronous Digital Hierarchy recommended in No. 9, and is composed of a memory circuit including first and second elastic store memories for respectively receiving frame signals transmitted by two transmission paths including different paths. In a hitless switching method for switching between first and second receiving means including delay means without loss of bits, one of the first receiving means and the second receiving means is set to a frame phase. The active system to be combined and the other one are used as a standby system for adjusting the frame phase to the active system, and are sequentially written to the memory circuits of the active system and the standby system from different memory addresses at the same time. And the frame synchronization of the working system read by the read address counter when the frame phase of the working system is ahead of that of the protection system. When the memory address for storing the pattern and the memory address for storing the frame synchronization pattern of the spare system are acquired and the difference between the memory addresses is set as the phase difference α, the spare memory is read by the read address counter. When the address is 0, the frame phase of the signal read from the memory is adjusted by loading the value of the memory address α of the spare system read by the read address counter. . 4. The ITU-T G.I. 707, 708, 70
Compliant with the Synchronous Digital Hierarchy recommended in No. 9, and is composed of a memory circuit including first and second elastic store memories for respectively receiving frame signals transmitted by two transmission paths including different paths. In a hitless switching method for switching between first and second receiving means including delay means without loss of bits, one of the first receiving means and the second receiving means is set to a frame phase. The active system to be combined and the other one are used as a standby system for adjusting the frame phase to the active system, and are sequentially written to the memory circuits of the active system and the standby system from different memory addresses at the same time. Frame synchronization of the working system read by the read address counter when the frame phase of the working system lags behind that of the protection system. When the memory address for storing the pattern and the memory address for storing the frame synchronization pattern of the spare system are acquired and the difference between the memory addresses is set as the phase difference α, the memory address of the spare system read by the read address counter. Is the read address
A hitless switching method characterized in that a frame phase of a signal read from the memory is matched by loading a value of the memory address 0 of the spare system read by a counter.